K6F1616R6C-FF700 [SAMSUNG]
Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, FBGA-48;
| 型号： | K6F1616R6C-FF700 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6F1616R6C Family
CMOS SRAM
Document Title
1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
November 17, 2003 Preliminary
0.1
Revised
November 21, 2003 Preliminary
- Changed ball name of E3 (Vss) & H6 (DNU) to NC.
- Deleted 85ns Speed bin.
1.0
Finalize
May 24, 2004
Final
- Deleted 55ns Speed bin.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 1M x16
The K6F1616R6C families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
• Power Supply Voltage: 1.65~1.95V
• Low Data Retention Voltage: 1.0V(Min)
• Three State Outputs
• Package Type: 48-FBGA-6.00 x 7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
1µA1)
K6F1616R6C-F
Industrial(-40~85°C)
1.65~1.95V
70ns
3mA
48-FBGA-6.00x7.00
1. Typical value are measured at VCC=1.8V, TA=25°C and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CS2
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
Vcc
Vss
I/O9
I/O10
Vss
CS1
I/O2
I/O4
I/O5
I/O6
WE
Row
Addresses
Memory
Cell Array
Row
select
I/O11
I/O12
I/O13
I/O14
A19
A5
A6
A17
NC
A14
A12
A9
A7
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Vcc
A16
A15
A13
A10
Data
cont
I/O9~I/O16
I/O15
I/O16
A18
Data
cont
G
H
Column Addresses
A8
A11
CS1
CS2
OE
WE
UB
48-FBGA: Top View (Ball Down)
Control Logic
Name
Function
Name
Function
LB
CS1, CS2 Chip Select Inputs
Vcc Power
Vss Ground
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
UB
LB
Upper Byte(I/O9~16)
A0~A19
Lower Byte(I/O1~8)
No Connection
I/O1~I/O16 Data Inputs/Outputs
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F1616R6C-FF70
48-FBGA, 70ns, 1.8V
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselected
Deselected
X1)
H
Deselected
X1)
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X1)
L
L
H
H
H
Active
L
H
L
H
H
Active
Active
Active
Active
Active
Active
L
H
L
H
H
L
High-Z
Dout
L
H
L
H
L
L
Dout
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
H
L
H
L
High-Z
Din
L
H
L
L
L
Din
1. X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN,VOUT
VCC
Ratings
Unit
-0.2 to VCC+0.3V(Max. 2.6V)
V
V
-0.2 to 2.6
1.0
PD
W
°C
°C
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
1.65
0
Typ
Max
Unit
V
Supply voltage
Ground
1.8
1.95
0
Vss
0
-
V
Vcc+0.22)
0.4
Input high voltage
Input low voltage
Note:
VIH
1.4
V
-0.23)
VIL
-
V
1. TA=-40 to 85°C, otherwise specified
2. Overshoot: VCC+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and Undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Typ1)
Item
Symbol
Test Conditions
Min
Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
1
µA
µA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or
LB=UB=VIH, VIO=Vss to Vcc
Output leakage current
ILO
-1
-
-
-
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V,
LB≤0.2V or/and UB≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V or
VIN≥VCC-0.2V
Average operating current
ICC1
ICC2
-
3
mA
mA
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,
LB=VIL or/and UB=VIL, VIN=VIL or VIH
-
22
Output low voltage
Output high voltage
VOL
VOH
IOL = 0.1mA
IOH = -0.1mA
-
-
-
0.2
-
V
V
1.4
Other input =0~Vcc
Standby Current(CMOS)
ISB1
1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0V≤CS2≤0.2V(CS2 controlled)
-
1
20
µA
1. Typical value are measured at VCC=1.8V, TA=25°C and not 100% tested.
4
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 0.9V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =1.8V
AC CHARACTERISTICS (Vcc=1.65~1.95V, TA=-40 to 85°C)
Speed Bin
70ns
Parameter List
Symbol
Units
Min
70
-
Max
Read cycle time
tRC
tAA
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO1, tCO2
tOE
-
Output enable to valid output
LB, UB valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Write cycle time
-
tBA
-
tLZ1, tLZ2
tOLZ
10
5
Read
-
tBLZ
10
10
0
-
tOH
-
tHZ1, tHZ2
tOHZ
tBHZ
25
25
25
-
0
0
tWC
70
60
0
Chip select to end of write
Address set-up time
tCW1, tCW2
tAS
-
-
Address valid to end of write
Write pulse width
tAW
60
50
0
-
tWP
-
Write
Write recovery time
tWR
-
Write to output high-Z
tWHZ
tDW
0
20
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
30
0
tDH
-
tOW
5
-
tBW
60
-
DATA RETENTION CHARACTERISTICS
Typ2)
Item
Symbol
Test Condition
Min
1.0
-
Max
1.95
12
-
Unit
V
CS1≥Vcc-0.2V1), VIN≥0V
Vcc=1.2V, CS1≥Vcc-0.2V1), VIN≥0V
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
-
1.0
-
IDR
µA
tSDR
0
See data retention waveform
ns
tRDR
tRC
-
-
1. 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0≤CS2≤0.2V(CS2 controlled)
2. Typical values are measured at TA=25°C and not 100% tested.
5
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
tAW
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS1
tWR(4)
tCW(2)
tAW
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
1.65V
1.4V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
1.65V
CS2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 1.0
May 2004
K6F1616R6C Family
CMOS SRAM
Unit: millimeters
PACKAGE DIMENSION
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.45
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are ±0.050 unless
specified beside figure.
B1
C
-
6.90
7.10
-
C1
D
-
0.40
-
4. Typ: Typical
0.50
1.00
-
5. Y is coplanarity
E
E1
Y
0.27
-
-
-
0.10
9
Revision 1.0
May 2004
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