K6F1016V4B-FF55 [SAMSUNG]
Standard SRAM, 64KX16, 55ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, FBGA-48;型号: | K6F1016V4B-FF55 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 64KX16, 55ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, FBGA-48 静态存储器 |
文件: | 总9页 (文件大小:158K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
K6F1016V4B Family
CMOS SRAM
Document Title
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
Remark
May 8, 2000
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.0
May 2000
- 1 -
Preliminary
K6F1016V4B Family
CMOS SRAM
64K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Full CMOS
· Organization: 64K x16 bit
The K6F1016V4B families are fabricated by SAMSUNG¢s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with
low data retention current.
· Power Supply Voltage: 3.0~3.6V
· Low Data Retention Voltage: 1.5V(Min)
· Three state output status and TTL Compatible
· Package Type: 48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
551)/70ns
K6F1016V4B-F
Industrial(-40~85°C)
3.0~3.6V
0.5mA
4mA
48-FBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
DNU
I/O1
I/O3
Vcc
Vcc
Vss
I/O9
CS
Row
Addresses
Memory array
1024 rows
64 ´ 16 columns
Row
select
I/O10
Vss
I/O11
I/O12
I/O13
I/O14
DNU
A8
A5
A6
I/O2
I/O4
I/O5
I/O6
WE
A11
DNU
DNU
A14
A12
A9
A7
Vcc
DNU
A15
A13
A10
Vss
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Data
cont
I/O9~I/O16
I/O15
I/O16
DNU
I/O7
I/O8
DNU
Data
cont
G
H
Column Addresses
48-CSP - Top View
CS
OE
WE
UB
LB
Name
CS
Function
Chip Select Input
Name
Function
Control Logic
Vcc
Vss
UB
Power
OE
Output Enable Input
Write Enable Input
Address Inputs
Ground
WE
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
Do Not Use
A0~A15
LB
I/O1~I/O16 Data Inputs/Outputs
DNU
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 0.0
May 2000
- 2 -
Preliminary
K6F1016V4B Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Function
Part Name
K6F1016V4B-FF55
K6F1016V4B-FF70
48-FBGA, 55ns, 3.3V
48-FBGA, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS
H
X1)
L
OE
X1)
X1)
H
WE
X1)
X1)
H
LB
X1)
H
L
UB
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Deselected
X1)
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
L
L
H
H
L
L
H
H
L
L
High-Z
Dout
L
L
H
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
L
High-Z
Din
L
L
L
Din
1. X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
-0.2 to VCC+0.5V
-0.2 to 4.6V
1.0
Unit
V
VIN, VOUT
VCC
V
PD
W
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
°C
°C
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 0.0
May 2000
- 3 -
Preliminary
K6F1016V4B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
3.0
0
Typ
Max
3.6
Unit
V
Supply voltage
Ground
3.3
Vss
0
-
0
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
VIH
2.2
-0.23)
V
VIL
-
V
Note :
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Symbol
ILI
Item
Test Conditions
Min Typ Max Unit
Input leakage current
Output leakage current
Operating power supply current
VIN=Vss to Vcc
-1
-
1
1
2
4
mA
mA
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIH or VIL
-1
-
ICC
-
-
mA
mA
ICC1
ICC2
VOL
VOH
ISB
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or VIN³ VCC-0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
-
-
Average operating current
-
-
40 mA
Output low voltage
-
2.4
-
-
-
0.4
-
V
V
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
IOH =-1.0mA
CS=VIH or LB=UB=VIH, Other inputs=VIH or VIL
CS³ Vcc-0.2V or LB=UB³ Vcc-0.2V, CS£0.2V, Other inputs=0~Vcc
-
0.3 mA
mA
51)
ISB1
-
0.5
1. Super low power product=1mA with special handling.
Revision 0.0
May 2000
- 4 -
Preliminary
K6F1016V4B Family
CMOS SRAM
3)
AC OPERATING CONDITIONS
VTM
TEST CONDITIONS (Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right) :CL= 100pF+1TTL
CL=30pF+1TTL
2)
2)
R1
1)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=3.0~3.6V, Industrial product:TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
55ns1)
70ns
Min
55
-
Max
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
55
-
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
tBA
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
20
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
25
0
30
0
-
-
tOW
5
-
5
-
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
VDR
Test Condition
Min
1.5
-
Typ
Max
Unit
V
CS³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
-
-
-
-
3.6
Vcc= 1.5V, CS³ Vcc-0.2V1)
IDR
mA
1
-
tSDR
tRDR
0
See data retention waveform
ns
tRC
-
1. CS³ Vcc-0.2V(CS controlled) or LB=UB³ Vcc-0.2V, CS£0.2V(LB, UB controlled)
Revision 0.0
May 2000
- 5 -
Preliminary
K6F1016V4B Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 0.0
May 2000
- 6 -
Preliminary
K6F1016V4B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 0.0
May 2000
- 7 -
Preliminary
K6F1016V4B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
Data Retention Mode
tSDR
tRDR
VCC
3.0V
2.2V
VDR
CS³ VCC - 0.2V or LB=UB³ Vcc-0.2V
CS, LB/UB
GND
Revision 0.0
May 2000
- 8 -
Preliminary
K6F1016V4B Family
CMOS SRAM
Unit: millimeters
PACKAGE DIMENSION
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
B
Bottom View
B
A1 INDEX MARK
0.50
B1
0.50
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.10
0.85
0.25
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
-
6.90
7.10
-
C1
D
-
4. Typ : Typical
0.30
0.40
1.20
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.20
-
0.30
0.08
Revision 0.0
May 2000
- 9 -
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