K4T56163QI-ZLD50 [SAMSUNG]
Synchronous DRAM, 16MX16, 0.5ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84;
| 型号： | K4T56163QI-ZLD50 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 16MX16, 0.5ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84 动态存储器 内存集成电路 |
| 文件： | 总42页 (文件大小：727K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR2 SDRAM
K4T56163QI
256Mb I-die DDR2 SDRAM Specification
84FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 October 2007
1 of 42
DDR2 SDRAM
K4T56163QI
Table of Contents
1.0 Ordering Information ....................................................................................................................4
2.0 Key Features .................................................................................................................................4
3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5
3.1 x16 package pinout (Top View) : 84ball FBGA Package .......................................................................5
3.2 FBGA Package Dimension(x16) .......................................................................................................6
4.0 Input/Output Functional Description ..........................................................................................7
5.0 DDR2 SDRAM Addressing ...........................................................................................................8
6.0 Absolute Maximum DC Ratings ...................................................................................................9
7.0 AC & DC Operating Conditions ...................................................................................................9
7.1 Recommended DC Operating Conditions (SSTL - 1.8) .........................................................................9
7.2 Operating Temperature Condition ..................................................................................................10
7.3 Input DC Logic Level ....................................................................................................................10
7.4 Input AC Logic Level ....................................................................................................................10
7.5 AC Input Test Conditions ..............................................................................................................10
7.6 Differential input AC logic Level .....................................................................................................11
7.7 Differential AC output parameters ..................................................................................................11
8.0 ODT DC electrical characteristics .............................................................................................11
9.0 OCD default characteristics ......................................................................................................12
10.0 IDD Specification Parameters and Test Conditions ..............................................................13
11.0 DDR2 SDRAM IDD Spec ...........................................................................................................15
12.0 Input/Output capacitance .........................................................................................................16
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................16
13.1 Refresh Parameters by Device Density ........................................................................................16
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................16
13.3 Timing Parameters by Speed Grade ............................................................................................17
14.0 General notes, which may apply for all AC parameters ........................................................19
15.0 Specific Notes for dedicated AC parameters..........................................................................21
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
Revision History
Revision
Month
Year
History
1.0
October
2007
- Initial Release
Rev. 1.0 October 2007
3 of 42
DDR2 SDRAM
K4T56163QI
1.0 Ordering Information
Org.
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Package
16Mx16 K4T56163QI-ZC(L)E7 K4T56163QI-ZC(L)F7
K4T56163QI-ZC(L)E6
K4T56163QI-ZC(L)D5 K4T56163QI-ZC(L)CC
84 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP
2. RoHS Compliant
2.0 Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
tCK
ns
5
6
5
4
3
12.5
12.5
57.5
15
15
60
15
15
60
15
15
60
15
15
55
ns
tRC(min)
ns
•
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/
pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/
sec/pin
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6
Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
The 256Mb DDR2 SDRAM is organized as a 4Mbit x 16 I/Os x 4
banks device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 256Mb(x16) device receive
13/9/2 addressing.
•
•
•
•
•
•
•
•
The 256Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 256Mb DDR2 device is available in 84ball FBGAs(x16).
•
•
•
Special Function Support
Note : The functionality described and the timing specifications included in
-PASR(Partial Array Self Refresh)
this data sheet are for the DLL Enabled mode of operation.
-50ohm ODT
-High Temperature Self-Refresh rate enable
•
•
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95 °C
All of Lead-free products are compliant for RoHS
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
3.0 Package Pinout/Mechanical Dimension & Addressing
3.1 x16 package pinout (Top View) : 84ball FBGA Package
1
2
3
7
8
9
A
VSSQ
UDQS
VDDQ
DQ10
VSSQ
UDQS
VSSQ
VDDQ
VDD
NC
VSS
UDM
VDDQ
DQ11
VSS
DQ14
VSSQ
B
C
DQ15
VDDQ
VDDQ
DQ12
VDD
DQ9
DQ8
D
E
F
VSSQ
LDQS
VSSQ
DQ13
VSSQ
NC
VDDQ
DQ6
VSSQ
DQ1
LDM
LDQS
VDDQ
DQ2
DQ7
VDDQ
DQ4
VDDQ
DQ3
DQ0
VSSQ
CK
VDDQ
G
H
J
VSSQ
VREF
CKE
DQ5
VDDL
VSS
WE
VSSDL
RAS
VDD
ODT
K
CK
NC
L
BA0
A10/AP
A3
BA1
A1
CAS
A2
CS
A0
A4
A8
M
N
P
R
VDD
VSS
VSS
A5
A6
A7
A9
A11
VDD
A12
NC
NC
NC
Note :
1. VDDL and VSSDL are power and ground for the DLL.
2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
+ + +
Ball Locations (x16)
: Populated Ball
: Depopulated Ball
+
G
H
J
Top View
(See the balls through the Package)
K
L
+
+
+
+
+
+
M
N
P
R
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
3.2 FBGA Package Dimension(x16)
Unit : mm
9.00 ± 0.10
0.80 x 8 = 6.40
3.20
A
# A1 INDEX MARK
B
0.80
1.60
4
9
8
7
6
5
3
2
1
(Datum A)
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(0.95)
84-∅0.45 Solder ball
MOLDING AREA
(1.90)
(Post reflow 0.50 ± 0.05)
0.2 M
A
B
Bottom
9.00 ± 0.10
#A1
0.35
1.10
±
0.05
0.10
±
Top
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
4.0 Input/Output Functional Description
Symbol
Type
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
CK, CK
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit. After V
has become stable during the power on and initialization
REF
CKE
CS
Input
Input
swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V
must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during
self refresh.
REF
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-
tems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal for x16 configuration.
The ODT pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT.
ODT
Input
Input
Input
RAS, CAS, WE
(L)UDM
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only,
the DM loading matches the DQ and DQS loading.
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines if the mode register or extended mode register is to be accessed during
a MRS or EMRS cycle.
BA0 - BA1
Input
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for
Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs also provide the op-
code during Mode Register Set commands.
A0 - A12
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data strobes
LDQS and UDQS may be used in single ended mode or paired with optional complementary signals LDQS and UDQS
to provide differential pair signaling to the system during both reads and writes. A control bit at EMRS(1)[A10] enables
LDQS, (LDQS)
UDQS, (UDQS)
or disables all complementary data strobe signals.
Input/Output
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x16 LDQS and UDQS
NC
No Connect: No internal electrical connection is present.
V
/V
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
Supply
Supply
Supply
Supply
Supply
DD DDQ
V
/V
SS SSQ
V
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
DDL
V
SSDL
V
Reference voltage
REF
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
5.0 DDR2 SDRAM Addressing
256Mb
Configuration
# of Banks
16Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A8
* Reference information: The following tables are address mapping information for other densities
512Mb
Configuration
# of Banks
128Mb x4
4
64Mb x 8
4
32Mb x16
4
Bank Address
Auto precharge
Row Address
Column Address
BA0,BA1
A10/AP
BA0,BA1
A10/AP
A0 ~ A13
A0 ~ A9
BA0,BA1
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
1Gb
2Gb
4Gb
Configuration
# of Banks
256Mb x4
8
128Mb x 8
8
64Mb x16
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A13
A0 ~ A9,A11
Configuration
# of Banks
512Mb x4
8
256Mb x 8
8
128Mb x16
8
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 ~ A14
A0 ~ A9
BA0 ~ BA2
A10/AP
A0 ~ A13
A0 ~ A9
A0 ~ A14
A0 ~ A9,A11
Configuration
# of Banks
1 Gb x4
8
512Mb x 8
8
256Mb x16
8
Bank Address
BA0 ~ BA2
A10/AP
BA0 ~ BA2
A10/AP
A0 - A15
A0 - A9
BA0 ~ BA2
A10/AP
A0 - A14
A0 - A9
Auto precharge
Row Address
A0 - A15
A0 - A9,A11
Column Address/page size
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DDR2 SDRAM
K4T56163QI
6.0 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
DDQ
pin relative to V
V
V
1
SS
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
7.0 AC & DC Operating Conditions
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
TT
REF
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DD
DDQ
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
REF
DDQ
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
TT
REF
DDQ
4. AC parameters are measured with V , V
and V
tied together.
DD
DDL
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DDR2 SDRAM
K4T56163QI
7.2 Operating Temperature Condition
Symbol
TOPER
Parameter
Operating Temperature
Rating
0 to 95
Units
°C
Notes
1, 2
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
7.3 Input DC Logic Level
Symbol
IH(DC)
VIL(DC)
Parameter
Min.
VREF + 0.125
Max.
VDDQ + 0.3
Units
V
Notes
V
DC input logic high
DC input logic low
- 0.3
VREF - 0.125
V
7.4 Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
V
(AC)
(AC)
VREF + 0.250
-
VREF + 0.200
V
V
AC input logic high
AC input logic low
IH
V
-
VREF - 0.250
VREF - 0.200
IL
7.5 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
V
Input reference voltage
0.5 * V
V
1
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
V
1
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Note :
1. Input waveform timing is referenced to the input signal crossing through the V
(AC) level applied to the device under test.
IH/IL
2. The input signal minimum slew rate is to be maintained over the range from V
to V (AC) min for rising edges and the range from V
to V (AC)
REF
IH
REF IL
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
(AC) max
IL
SS
delta TF
V
delta TR
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
Rising Slew =
delta TF
< AC Input Test Signal Waveform >
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DDR2 SDRAM
K4T56163QI
7.6 Differential input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VID(AC)
0.5
VDDQ + 0.6
V
1
AC differential input voltage
AC differential cross point voltage
VIX(AC)
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Note :
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS)
and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC)
indicates the voltage at which differential input signals must cross.
VDDQ
VTR
VCP
Crossing point
VID
VIX or VOX
VSSQ
< Differential signal levels >
7.7 Differential AC output parameters
Symbol
Parameter
Min.
Max.
Units
Note
VOX(AC)
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
AC differential cross point voltage
Note :
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ .
VOX(AC) indicates the voltage at which differential output signals must cross.
8.0 ODT DC electrical characteristics
PARAMETER/CONDITION
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm
Deviation of VM with respect to VDDQ/2
SYMBOL
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
delta VM
MIN
60
NOM
75
MAX
90
UNITS
ohm
ohm
ohm
%
NOTES
1
1
1
1
120
40
150
50
180
60
- 6
+ 6
Note :
1. Test condition for Rtt measurements
Measurement Definition for Rtt(eff) : Apply V (ac) and V (ac) to test pin separately, then measure current I(V (ac)) and I( V (ac)) respectively.
IH
IL
IH
IL
V
(ac), V (ac), and VDDQ values defined in SSTL_18
IL
IH
VIH (ac) - VIL (ac)
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
2 x Vm
- 1
x 100%
delta VM =
VDDQ
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.
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DDR2 SDRAM
K4T56163QI
9.0 OCD default characteristics
Description
Parameter
Min
Nom
Max
Unit
Notes
Normal 18ohms
See full strength default driver characteristics
Output impedance
ohms
1,2
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
0
0
1.5
4
ohms
ohms
V/ns
6
1,2,3
Sout
1.5
5
1,4,5,6,7,8
Note :
1. Absolute Specifications (0°C ≤ T
≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
CASE
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V (AC) to V (AC).
IL
IH
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin, 667Mb/sec/pin and 800Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
10.0 IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
Proposed Conditions
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Units
Notes
t
t
t
t
t
t
IDD0
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pat-
tern is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
= RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-
lowing page for detailed timing conditions
mA
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
Note :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
For purposes of IDD testing, the following parameters are utilized
DDR2-800
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Parameter
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
CL(IDD)
5
6
5
4
3
tCK
t
12.5
57.5
15
60
15
60
15
60
15
55
7.5
5
RCD(IDD)
ns
ns
t
RC(IDD)
t
ns
RRD(IDD)-x16
7.5
2.5
7.5
2.5
7.5
3
7.5
t
3.75
CK(IDD)
ns
ns
t
45
45
15
45
15
45
15
40
15
105
RASmin(IDD)
t
12.5
105
ns
ns
RP(IDD)
t
105
105
105
RFC(IDD)
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) and FAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
t
t
t
Timing Patterns for 4 bank devices x16
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-667 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-DDR2-800 6/6/6
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-DDR2-800 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
11.0 DDR2 SDRAM IDD Spec
16Mx16 (K4T56163QI)
667@CL=5
Symbol
Unit
Notes
800@CL=5
CE7 LE7
800@CL=6
CF7 LF7
533@CL=4
CD5 LD5
400@CL=3
CCC LCC
CE6
LE6
IDD0
IDD1
85
100
10
80
95
80
90
75
85
70
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5
10
10
10
10
35
35
30
30
30
45
40
38
35
35
35
35
30
30
30
10
10
10
10
10
60
55
55
50
50
160
180
100
10
150
190
95
140
170
90
135
160
90
130
150
90
IDD6
10
10
10
10
IDD7
220
215
210
205
200
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DDR2 SDRAM
K4T56163QI
12.0 Input/Output capacitance
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Units
Symbol
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Min
1.0
x
Max
2.0
Input capacitance, CK and CK
CCK
CDCK
CI
pF
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
0.25
2.0
0.25
2.0
0.25
1.75
0.25
3.5
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
2.5
x
CDIO
0.5
0.5
0.5
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
Symbol
256Mb
75
512Mb
105
1Gb
127.5
7.8
2Gb
195
7.8
4Gb
327.5
7.8
Units
ns
tRFC
tREFI
0 °C ≤ T
≤ 85°C
7.8
7.8
µs
CASE
Average periodic refresh interval
85 °C < T
≤ 95°C
3.9
3.9
3.9
3.9
3.9
µs
CASE
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tCK, CL=6
tRCD
DDR2-800(E7)
5-5-5
DDR2-800(F7)
6-6-6
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
5
max
8
min
-
max
-
min
5
max
8
min
5
max
8
min
5
max
8
ns
ns
ns
ns
ns
ns
ns
ns
3.75
2.5
-
8
3.75
3
8
3.75
3
8
3.75
3.75
-
8
5
8
8
8
8
8
-
-
-
2.5
15
15
60
45
8
-
-
-
-
-
12.5
12.5
57.5
45
-
-
15
15
60
45
-
15
-
15
15
55
40
-
tRP
-
-
-
-
-
-
15
-
-
-
-
tRC
60
tRAS
70000
70000
70000
45
70000
70000
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DDR2 SDRAM
K4T56163QI
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Notes
min
- 400
- 350
0.45
0.45
max
400
min
max
+450
+400
0.55
0.55
min
max
+500
+450
0.55
0.55
min
max
+600
+500
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
-500
-450
0.45
0.45
-600
-500
0.45
0.45
ps
ps
tDQSCK
tCH
350
0.55
0.55
tCK
tCK
CK low-level width
tCL
min(tCL,t
CH)
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
8000
x
x
8000
x
x
8000
x
x
8000
x
ps
ps
ps
20,21
24
Clock cycle time, CL=x
DQ and DM input hold time
tCK
2500
3000
3750
5000
15,16,
17,20
tDH(base)
125
175
225
275
15,16,
17,21
DQ and DM input setup time
tDS(base)
50
x
100
x
100
x
150
x
ps
Control & Address input pulse width for each input tIPW
0.6
0.35
x
x
x
0.6
0.35
x
x
x
0.6
0.35
x
x
x
0.6
0.35
x
x
x
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
tDIPW
tHZ
tAC max
tAC max
tAC max
tAC max
tLZ(DQS)
tAC min tAC max tAC min tAC max
tAC min tAC max tAC min tAC max
ps
27
27
2* tAC
min
2*tAC
min
DQ low-impedance time from CK/CK
tLZ(DQ)
tAC max
tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
DQS-DQ skew for DQS and associated DQ sig-
nals
tDQSQ
tQHS
tQH
x
200
300
x
x
240
340
x
x
x
300
400
x
x
x
350
450
x
ps
ps
ps
22
21
DQ hold skew factor
x
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
x
x
x
x
tDSH
x
x
x
x
tMRD
x
x
x
x
tWPST
tWPRE
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
0.4
0.35
0.6
x
19
Write preamble
14,16,
18,23
Address and control input hold time
Address and control input setup time
tIH(base)
tIS(base)
250
175
x
x
275
200
x
x
375
250
x
x
475
350
x
x
ps
ps
14,16,
18,22
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
28
28
Active to active command period for 1KB page
size products
tRRD
7.5
x
7.5
x
7.5
x
7.5
x
ns
12
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Notes
min
max
min
max
min
max
min
max
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
35
45
37.5
50
37.5
50
37.5
ns
ns
50
2
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
x
x
x
2
2
tCK
ns
15
15
x
x
x
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge time tDAL
WR+tRP
7.5
WR+tRP
7.5
WR+tRP
7.5
WR+tRP
10
tCK
ns
23
33
11
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
7.5
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
x
x
x
tCK
Exit precharge power down to any non-read com-
mand
tXP
2
2
2
2
x
x
2
2
x
x
2
2
x
x
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
9
Exit active power down to read command
(slow exit, lower power)
8 - AL
7 - AL
6 - AL
6 - AL
9, 10
CKE minimum pulse width
(high and low pulse width)
t
CKE
3
2
3
2
3
2
3
2
tCK
tCK
ns
36
t
ODT turn-on delay
AOND
2
2
2
2
tAC(max)
+ 0.7
tAC(max)
+0.7
tAC(max)
+1
tAC(max)
+1
t
ODT turn-on
AON
tAC(min)
tAC(min)
tAC(min)
tAC(min)
13, 25
2tCK +
tAC(max)
+1
2tCK+tA
C(max)+
1
tAC(min)+
2
tAC(min)+ 2tCK+tAC tAC(min)+
tAC(min)+ 2tCK+tAC
t
ODT turn-on(Power-Down mode)
AONPD
ns
2
(max)+1
2
2
(max)+1
t
ODT turn-off delay
ODT turn-off
AOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ns
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(max)
+ 0.6
t
AOF
tAC(min)
tAC(min)
tAC(min)
tAC(min)
26
24
2.5tCK +
tAC(max)
+1
2.5tCK+t
AC(max)
+1
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
tAC(min)+
2
tAC(min)+
2
tAC(min)+
2
tAC(min)+
2
t
ODT turn-off (Power-Down mode)
AOFPD
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
12
Minimum time clocks remains ON after CKE asyn-
chronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
14.0 General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load
Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre
sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally
a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ
DQS
DQS Output
DUT
V
= V
/2
TT
DDQ
RDQS
RDQS
25Ω
Timing
reference
point
Figure 1 - AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential
signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
2. Slew Rate Measurement Levels
a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to - 500 mV
for falling edges).
c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure 2.
VDDQ
DUT
DQ
Output
Test point
DQS, DQS
RDQS, RDQS
V
= V
/2
DDQ
TT
25Ω
Figure 2 - Slew Rate Test Load
Rev. 1.0 October 2007
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DDR2 SDRAM
K4T56163QI
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS
through a 20 Ω to 10 kΩ resistor to insure proper operation.
tDQSH
tDQSL
DQS
DQS/
DQS
DQS
tWPRE
tWPST
V
IH(dc)
V
IH(ac)
DQ
DM
D
D
D
D
V
IL(ac)
VIL(dc)
tDH
tDH
tDS
DMin
tDS
V
IH(ac)
V
IH(dc)
DMin
DMin
DMin
V
IL(ac)
V
IL(dc)
Figure 3 - Data Input (Write) Timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Figure 4 - Data Output (Read) Timing
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
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15.0 Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in
differential strobe mode and a slew rate of 1.0 V/ns in single ended mode.
8. Data setup and hold time derating.
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
45
21
0
-
-
-
-
-
-
125
83
0
-11
-
-
-
-
-
45
21
0
-14
-
-
-
-
-
125
83
0
-11
-25
-
-
-
-
45
21
0
-14
-31
-
-
-
-
-
95
12
1
-13
-31
-
-
33
12
-2
-19
-42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
0
-
-
-
-
-
-
24
13
-1
-19
-43
-
24
10
-7
-30
-59
-
DQ
Siew
rate
25
11
-7
-31
-74
-
22
5
-18
-47
-89
-
-
17
-6
-35
-77
17
-7
-50
6
-23
-65
-
5
-38
-
V/ns
-19
-62
-11
-53
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
45
21
0
-
-
-
-
-
-
100
45
21
0
-14
-
-
-
-
-
100
67
0
-5
-13
-
-
-
-
45
21
0
-14
-31
-
-
-
-
-
79
12
7
-1
-10
-
-
33
12
-2
-19
-42
-
-
-
24
19
11
2
-10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
-6
-35
-77
-140
-
-
-
-
-
38
26
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67
0
-
-
-
-
-
-
67
0
-5
-
-
-
24
10
-7
-30
-59
-
DQ
Slew
rate
31
23
14
2
-24
-
22
5
-18
-47
-89
-
-
35
26
14
-12
-52
6
-
-
V/ns
-23
-65
-128
38
12
-28
-11
-53
-116
-
-
-
-
-
-
-
-40
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Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe
∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)
DQS Single-ended Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
0.9 V/ns
0.8 V/ns
0.7 V/ns
0.6 V/ns
0.5 V/ns
0.4 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
1
188
1
188
1
167
125
42
31
-
1
146
125
83
69
-
1
125
83
0
1
63
42
0
1
-
1
-
1
-
1
-
1
-
1
-
1
-
-
1
-
1
-
1
-
1
-
-
-
-
-
-
1
-
-
-
-
-
-
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
146
167
81
-2
-13
-27
-45
-
43
1
-
-
-
-
-
-
-
-
63
-
125
-7
-18
-32
-50
-74
-
-13
-27
-44
-67
-96
-
-
-
-
-
-
DQ
Slew
rate
-
-
-
-
-
-
-11
-25
-
-14
-31
-
-13
-30
-53
-
-29
-43
-61
-85
-45
-62
-85
-
-
-
-
-
-60
-78
-86
-
-
-
-
-
-109 -108 -152
V/ns
-
-
-
-
-
-114 -102 -138 -138 -181 -183 -246
-
-
-
-
-
-
-
-128 -156 -145 -180 -175 -223 -226 -288
-210 -243 -240 -286 -291 -351
-
-
-
-
-
-
-
-
-
-
-
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the
∆tDS and ∆tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for derating value (See
Figure 5 for differential data strobe and Figure 6 for single-ended data strobe.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 7 for differential data strobe and Figure 8 for single-ended data strobe)
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold
(tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the
actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(dc) region’, use nominal slew rate for derating value (see
Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere
between shaded ’dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value
(see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe)
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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DQS
DQS
tDH
tDH
tDS
tDS
V
DDQ
V
min
min
IH(ac)
VREF to ac
region
V
IH(dc)
nominal
slew rate
V
REF(dc)
nominal slew
rate
V
max
IL(dc)
VREF to ac
region
V
max
IL(ac)
tVAC
V
SS
∆TF
∆TR
V
- Vil(ac)max
Vih(ac)min - V
REF(dc)
Setup Slew Rate
Rising Signal
REF(dc)
Setup Slew Rate
=
=
Falling Signal
∆TR
∆TF
Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS)
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VDDQ
VIH(ac) min
VIH(dc) min
DQS
Note1
V
REF(dc)
VIL(dc) max
VIL(ac) max
VSS
tDH
tDS
tDS
tDH
V
DDQ
V
min
IH(ac)
VREF to ac
region
V
min
IH(dc)
nominal
slew rate
V
REF(dc)
nominal slew
rate
V
max
IL(dc)
VREF to ac
region
V
max
IL(ac)
V
SS
∆TF
∆TR
V
- Vil(ac)max
∆TF
Vih(ac)min - V
REF(dc)
REF(dc)
Setup Slew Rate
Rising Signal
Setup Slew Rate
=
=
Falling Signal
∆TR
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS)
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DQS
DQS
tDH
tDH
tDS
tDS
V
DDQ
nominal
line
V
V
min
IH(ac)
V
to ac
REF
region
min
IH(dc)
tangent
line
V
REF(dc)
tangent
line
V
V
max
IL(dc)
IL(ac)
V
to ac
REF
region
max
nominal
line
∆TR
V
SS
tangent line[Vih(ac)min - V
]
REF(dc)
Setup Slew Rate
=
Rising Signal
∆TF
∆TR
tangent line[V
- Vil(ac)max]
Setup Slew Rate
REF(dc)
=
Falling Signal
∆TF
Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS)
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VDDQ
VIH(ac) min
VIH(dc) min
DQS
Note1
V
REF(dc)
VIL(dc) max
VIL(ac) max
VSS
tDH
tDS
tDS
tDH
V
DDQ
nominal
line
V
V
min
IH(ac)
V
to ac
REF
region
min
IH(dc)
tangent
line
V
REF(dc)
tangent
line
V
V
max
IL(dc)
IL(ac)
V
to ac
REF
region
max
nominal
line
∆TR
V
SS
tangent line[Vih(ac)min - V
]
REF(dc)
Setup Slew Rate
=
Rising Signal
∆TR
∆TF
tangent line[V
- Vil(ac)max]
Setup Slew Rate
REF(dc)
=
Falling Signal
∆TF
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 8 - IIIustration of tangent line for tDS (single-ended DQS)
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DQS
DQS
tDH
tDH
tDS
tDS
V
DDQ
V
V
min
IH(ac)
IH(dc)
min
dc to V
region
REF
nominal
slew rate
V
REF(dc)
nominal
dc to V
region
REF
slew rate
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
Hold Slew Rate
V
- Vil(dc)max
∆TR
Hold Slew Rate
Rising Signal
REF(dc)
Vih(dc)min - V
REF(dc)
=
=
Falling Signal
∆TF
Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS)
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VDDQ
VIH(ac) min
VIH(dc) min
DQS
Note1
V
REF(dc)
VIL(dc) max
VIL(ac) max
VSS
tDH
tDS
tDS
tDH
V
DDQ
V
V
min
min
IH(ac)
IH(dc)
dc to V
REF
nominal
region
slew rate
V
REF(dc)
nominal
dc to V
region
REF
slew rate
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
Hold Slew Rate
V
- Vil(dc)max
∆TR
Hold Slew Rate
Rising Signal
REF(dc)
Vih(dc)min - V
REF(dc)
=
=
Falling Signal
∆TF
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS)
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DQS
DQS
tDH
tDH
tDS
tDS
V
DDQ
V
V
min
min
IH(ac)
IH(dc)
nominal
line
dc to V
region
REF
tangent
line
V
REF(dc)
tangent
dc to V
region
REF
line
nominal
line
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
- Vil(dc)max ]
tangent line [ V
REF(dc)
Hold Slew Rate
=
Rising Signal
∆TR
tangent line [ Vih(dc)min - V
]
REF(dc)
Hold Slew Rate
=
Falling Signal
∆TF
Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS)
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VDDQ
VIH(ac) min
VIH(dc) min
DQS
Note1
V
REF(dc)
VIL(dc) max
VIL(ac) max
VSS
tDH
tDS
tDS
tDH
V
DDQ
V
V
min
min
IH(ac)
IH(dc)
nominal
line
dc to V
REF
tangent
line
region
V
REF(dc)
tangent
dc to V
region
REF
line
nominal
line
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
- Vil(dc)max ]
tangent line [ V
REF(dc)
Hold Slew Rate
Rising Signal
=
∆TR
tangent line [ Vih(dc)min - V
]
REF(dc)
Hold Slew Rate
=
Falling Signal
∆TF
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 12 - IIIustration of tangent line for tDH (single-ended DQS)
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9. tIS and tIH (input setup and hold) derating
Table 4 - Derating values for DDR2-400, DDR2-533
∆tIS, ∆tIH Derating Values for DDR2-400, DDR2-533
CK, CK Differential Slew Rate
1.5 V/ns 1.0 V/ns
2.0 V/ns
Units
Notes
∆tIS
+187
+179
+167
+150
+125
+83
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+217
+209
+197
+180
+155
+113
+30
∆tIH
+124
+119
+113
+105
+75
∆tIS
+247
+239
+227
+210
+185
+143
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
0
+30
+60
-11
-14
+19
+16
+49
+46
Command/
AddressSlew
rate(V/ns)
-25
-31
+5
-1
+35
+29
-43
-54
-13
-24
+17
+6
-67
-83
-37
-53
-7
-23
-110
-175
-285
-350
-525
-800
-1450
-125
-188
-292
-375
-500
-708
-1125
-80
-95
-50
-65
-145
-255
-320
-495
-770
-1420
-158
-262
-345
-470
-678
-1095
-115
-225
-290
-465
-740
-1390
-128
-232
-315
-440
-648
-1065
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Table 5 - Derating values for DDR2-667, DDR2-800
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK, CK Differential Slew Rate
1.5 V/ns 1.0 V/ns
2.0 V/ns
Units
Notes
∆tIS
+150
+143
+133
+120
+100
+67
0
∆tIH
+94
+89
+83
+75
+45
+21
0
∆tIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
∆tIH
+124
+119
+113
+105
+75
∆tIS
+210
+203
+193
+180
+160
+127
+60
∆tIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51
+30
+60
-5
-14
+16
+55
+46
Command/
Address Slew
rate(V/ns)
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min.
Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for derating value (see
Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to
the actual signal from the ac level to dc level is used for derating value (see Figure 14).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold
(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the
actual signal is always later than the nominal slewrate line between shaded ’dc to VREF(dc) region’, use nominal slew rate for derating value (see Figure
15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(dc) region’, the slew rate of a tangent line to the
actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 16).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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CK
CK
tIH
tIH
tIS
tIS
V
DDQ
V
min
IH(ac)
VREF to ac
region
V
min
IH(dc)
nominal
slew rate
V
REF(dc)
nominal slew
rate
V
max
IL(dc)
VREF to ac
region
V
max
IL(ac)
V
SS
∆TF
∆TR
V
- Vil(ac)max
Vih(ac)min - V
REF(dc)
REF(dc)
Setup Slew Rate
Rising Signal
Setup Slew Rate
Falling Signal
=
=
∆TF
∆TR
Figure 13 - IIIustration of nominal slew rate for tIS
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CK
CK
tIH
tIH
tIS
tIS
V
DDQ
nominal
line
V
V
min
IH(ac)
V
to ac
REF
region
min
IH(dc)
tangent
line
V
REF(dc)
tangent
line
V
V
max
IL(dc)
IL(ac)
V
to ac
REF
region
max
nominal
line
∆TR
V
SS
tangent line[Vih(ac)min - V
]
REF(dc)
Setup Slew Rate
=
Rising Signal
∆TR
∆TF
tangent line[V
- Vil(ac)max]
REF(dc)
Setup Slew Rate
Falling Signal
=
∆TF
Figure 14 - IIIustration of tangent line for tIS
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CK
CK
tIH
tIH
tIS
tIS
V
DDQ
V
V
min
IH(ac)
IH(dc)
min
dc to V
region
REF
nominal
slew rate
V
REF(dc)
nominal
dc to V
region
REF
slew rate
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
Hold Slew Rate
V
- Vil(dc)max
∆TR
Hold Slew Rate
Rising Signal
REF(dc)
Vih(dc)min - V
REF(dc)
=
=
Falling Signal
∆TF
Figure 15 - IIIustration of nominal slew rate for tIH
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CK
CK
tIH
tIH
tIS
tIS
V
DDQ
V
V
min
IH(ac)
IH(dc)
nominal
line
min
dc to V
region
REF
tangent
line
V
REF(dc)
tangent
dc to V
region
REF
line
nominal
line
V
V
max
IL(dc)
IL(ac)
max
V
SS
∆TF
∆TR
- Vil(dc)max ]
tangent line [ V
REF(dc)
Hold Slew Rate
Rising Signal
=
∆TR
tangent line [ Vih(dc)min - V
]
REF(dc)
Hold Slew Rate
Falling Signal
=
∆TF
Figure 16 - IIIustration of tangent line for tIH
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10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be
greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP))
of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
12. tQH = tHP - tQHS, where :
tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due
to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
mismatch between DQS/ DQS and associated DQ in any given cycle.
14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.
WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tCK refers to the application clock period.
Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
15. The clock frequency is allowed to change during self refresh mode or precharge power-down mode.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT
resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns)
after the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a
first ODT HIGH counting the actual input clock edges.
17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are mea-
sured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that regis-
tered a first ODT LOW if tCK = 5 ns. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock
edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Figure 17 shows a method to calculate the point when device is no
longer driving (tHZ), or beginsdriving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as
long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQS and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each treated as
single-ended signal.
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
or begins driving (tRPRE). Figure 17 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consis-
tent.
VOH + x mV
VOH + 2x mV
VTT + 2x mV
VTT + x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VOL + 2x mV
VOL + x mV
VTT - x mV
T2
T1
VTT - 2x mV
T1
T2
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
Figure 17 - Method for calculating transitions and endpoints
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20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
nal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
Figure 18 - Differential input waveform timing - tDS and tDH
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test. See Figure 19.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test. See Figure 19.
CK
CK
tIH
tIH
tIS
tIS
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
Figure 19 - Differential input waveform timing - tIS and tIH
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24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period
of tIS + 2 x tCK + tIH.
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respec-
tive clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup
and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is
present or not.
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec val-
ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these
parameters should be met whether clock jitter is present or not.
31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/
R)DQS/DQS) crossing.
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means:
For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications
are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set.
34. New units, ’tCK(avg)’ and ’nCK’, are introduced in DDR2-667 and DDR2-800. Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under
operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ’tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x
tCK(avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these
parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
DDR2-667
Min
DDR2-800
Parameter
Symbol
units
Notes
Max
125
100
250
200
175
225
250
250
350
450
125
Min
-100
-80
Max
100
80
Clock period jitter
tJIT(per)
tJIT(per,lck)
tJIT(cc)
-125
-100
-250
-200
-175
-225
-250
-250
-350
-450
-125
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
35
35
35
35
35
35
35
35
35
35
35
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
-200
-160
-150
-175
-200
-200
-300
-450
-100
200
160
150
175
200
200
300
450
100
Cycle to cycle clock period jitter during DLL locking period
Cumulative error across 2 cycles
tJIT(cc,lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-10per)
tERR(11-50per)
tJIT(duty)
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles, n = 6 ... 10, inclusive
Cumulative error across n cycles, n = 11 ... 50, inclusive
Duty cycle jitter
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Definitions :
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
N
/N
tCK(avg) =
where
tCK
∑
j
j = 1
N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
N
/(N x tCK(avg))
tCH(avg) =
where
tCH
∑
j
j = 1
N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
N
/(N x tCK(avg))
tCL(avg) =
where
tCL
∑
j
j = 1
N = 200
- tJIT(duty)
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the larg-
est deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}
where,
tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}
tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}
- tJIT(per), tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
- tJIT(cc), tJIT(cc,lck)
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT(cc) = Max of |tCK - tCKi|
i+1
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.
- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
i + n - 1
- n x tCK(avg)
tERR(nper) =
tCK
∑
j
j = 1
n = 2
for tERR(2per)
for tERR(3per)
for tERR(4per)
for tERR(5per)
for tERR(6-10per)
n = 3
n = 4
n = 5
where
6 ≤ n ≤ 10
11 ≤ n ≤ 50 for tERR(11-50per)
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36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the
absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.)
Parameter
Symbol
Min
Max
Units
Absolute clock Period
tCK(abs)
tCK(avg),min + tJIT(per),min
tCK(avg),max + tJIT(per),max
ps
tCH(avg),min x tCK(avg),min +
tJIT(duty),min
tCH(avg),max x tCK(avg),max +
tJIT(duty),max
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
tCH(abs)
tCL(abs)
ps
ps
tCL(avg),min x tCK(avg),min +
tJIT(duty),min
tCL(avg),max x tCK(avg),max +
tJIT(duty),max
Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps
37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used
in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation;
tHP = Min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;
tCL(abs) is the minimum of the actual instantaneous clock LOW time;
38. tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of
each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers
39. tQH = tHP - tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column.
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples:
1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum.
2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
40. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output derat-
ings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per),max = + 293 ps, then
tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = - 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(6-
10per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = - 1193 ps and
tLZ(DQ),max(derated) = 450 ps + 272 ps = + 722 ps.
41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are
relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) =
tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps =
+ 2843 ps.
42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are
relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) =
tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = +
1592 ps.
43. When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT(duty),max - tERR(6-10per),max } and { -
tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6- 10per),max = + 293 ps, tJIT(duty),min = -
106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} =
- 837 ps and tAOF,max(derated) = tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps.
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44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and
tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock
has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have;
tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK
tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK
or
tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK)
tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK)
where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls.
45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to
tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input
with respect to 0.5.
For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an
input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have;
tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg)
tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg)
tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg))
tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg))
where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls.
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the
equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are;
tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max }
tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }
Rev. 1.0 October 2007
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