K4S643232E-TL45T [SAMSUNG]
Synchronous DRAM, 2MX32, 4ns, CMOS, PDSO86;
| 型号： | K4S643232E-TL45T |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 2MX32, 4ns, CMOS, PDSO86 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总44页 (文件大小：1191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S643232E
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 1.0
October 2000
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 (Oct. 2000)
- 1 -
K4S643232E
CMOS SDRAM
Revision History
Revision 1.0 (October 20, 2000)
• Removed Note 5 in page 9. tRDL is set to 2CLK in any case regardless of using AP or frequency
Revision 0.4 (August 24, 2000)
• Updated DC spec
Revision 0.3 (August 1, 2000)
• Changed the wording of tRDL related note for Users’ clear understanding
Revision 0.2 (July 18, 2000) - Preliminary
• Removed K4S643232E-40/55/7C
• Changed tSH of K4S643232E-45 from 0.7ns to 1.0ns
Revision 0.0 (March 14, 2000) - Target Spec.
• Initial draft
Rev. 1.0 (Oct. 2000)
- 2 -
K4S643232E
CMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• 3.3V power supply
The K4S643232E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG¢s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
• Auto & self refresh
Part NO.
Max Freq.
222MHz
200MHz
166MHz
143MHz
Interface Package
• 15.6us refresh duty cycle
K4S643232E-TC/L45
K4S643232E-TC/L50
K4S643232E-TC/L60
K4S643232E-TC/L70
86
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Rev. 1.0 (Oct. 2000)
- 3 -
K4S643232E
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
N.C
VDD
DQM0
WE
CAS
RAS
CS
1
2
3
4
5
6
7
8
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
N.C
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
N.C
DQM3
VSS
N.C
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)
Rev. 1.0 (Oct. 2000)
- 4 -
K4S643232E
CMOS SDRAM
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CS
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
A0 ~ A10
BA0,1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM0 ~ 3
Data input/output mask
DQ0 ~ 31
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
NC
Data output power/ground
No Connection
This pin is recommended to be left No connection on the device.
Rev. 1.0 (Oct. 2000)
- 5 -
K4S643232E
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
VOH
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
10
V
ILI
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. The VDD condition of K4S643232E-45/50/60 is 3.135V ~ 3.6V
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
Max
4
Unit
pF
Clock
-
-
-
-
RAS, CAS, WE, CS, CKE, DQM
Address
4.5
4.5
6.5
pF
CADD
COUT
pF
DQ0 ~ DQ31
pF
Rev. 1.0 (Oct. 2000)
- 6 -
K4S643232E
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)
Speed
CAS
Latency
Parameter
Symbol
Test Condition
Unit Note
-45
-50
-60
-70
3
2
180
175
170
155
Operating Current
(One Bank Active)
Burst Length =1
ICC1
mA
mA
2
tRC ³ tRC(min), tCC ³ tCC(min), Io = 0mA
150
150
150
150
ICC2P
CKE £ VIL(max), tCC = 15ns
3
2
Precharge Standby Current in
power-down mode
ICC2PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2N
20
10
Precharge Standby Current
in non power-down mode
mA
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 15ns
CKE £ VIL(max), tCC = ¥
7
5
Active Standby Current
in power-down mode
ICC3PS
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3N
55
40
Active Standby Current
in non power-down mode
(One Bank Active)
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC3NS
3
2
3
2
200
150
195
160
190
150
190
160
180
150
185
160
170
150
165
160
Operating Current
(Burst Mode)
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
ICC4
ICC5
ICC6
mA
mA
2
3
Refresh Current
tRC ³ tRC(min)
CKE £ 0.2V
3
mA
uA
4
5
Self Refresh Current
450
Notes :
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232E-TC**
5. K4S643232E-TL**
Rev. 1.0 (Oct. 2000)
- 7 -
K4S643232E
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
30pF
30pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
Notes :
1. The VDD condition of K4S643232E-45/50/60 is 3.135V ~ 3.6V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-45
-50
-60
-70
CAS Latency
CLK cycle time
CL
3
2
3
5
2
3
6
2
3
7
2
CLK
ns
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
4.5
10
10
10
10
Row active to row active delay
RAS to CAS delay
2
CLK
CLK
CLK
CLK
us
1
1
1
1
4
4
9
2
2
5
3
3
8
2
2
5
3
3
7
2
2
5
3
3
7
2
2
5
Row precharge time
Row active time
Row cycle time
100
tRC(min)
13
7
11
7
10
7
10
7
CLK
1
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
tMRS(min)
2
1
1
1
2
2
1
CLK
CLK
CLK
CLK
CLK
2
2
2
3
Col. address to col. address delay
Mode Register Set cycle time
CAS Latency=3
CAS Latency=2
Number of valid
output data
ea
4
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Rev. 1.0 (Oct. 2000)
- 8 -
K4S643232E
CMOS SDRAM
Version
-50
Parameter
Symbol
Unit
-45
9
-60
12
18
18
42
-70
14
20
20
49
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
10
15
15
40
ns
ns
ns
ns
us
ns
18
Row precharge time
18
tRAS(min)
tRAS(max)
tRC(min)
40.5
Row active time
Row cycle time
100
58.5
55
60
70
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-45
-50
-60
-70
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
4.5
10
-
Max
Min
5
Max
Min
6
Max
Min
Max
CAS Latency=3
7
10
-
CLK cycle time
1000
1000
1000
1000
CAS Latency=2
CAS Latency=3
CAS Latency=2
10
-
10
-
4
6
-
4.5
5.5
5.5
CLK to valid
output delay
tSAC
ns
1, 2
-
-
6
-
6
-
6
Output data hold time
tOH
tCH
2
2
-
2
-
2
-
ns
ns
2
3
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
1.75
3
-
2
-
2.5
3
-
3
-
CLK high pulse
width
-
3
-
-
-
3
-
1.75
3
-
2
2.5
3
-
-
3
-
-
CLK low
pulse width
ns
ns
3
3
tCL
tSS
-
3
-
3
1.2
2.5
1
-
1.5
2.5
1
-
1.5
2.5
1
-
1.75
2.5
1
-
Input setup time
Input hold time
-
-
-
-
tSH
-
-
-
-
ns
ns
3
2
CLK to output in Low-Z
tSLZ
1
-
1
-
1
-
1
-
CAS latency=3
CAS latency=2
-
4
6
-
4.5
6
-
5.5
6
-
5.5
6
CLK to output
in Hi-Z
tSHZ
ns
-
-
-
-
-
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.0 (Oct. 2000)
- 9 -
K4S643232E
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
,
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
A9 ~ A0
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A7)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A7)
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
No operation command
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.0 (Oct. 2000)
- 10
K4S643232E
CMOS SDRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
BA0 ~ BA1
RFU
A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address
Function
W.B.L
TM
CAS Latency
BT
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
0
A7
0
Type
Mode Register Set
Reserved
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A3
0
Type
A2
A1 A0
BT = 0
BT = 1
0
0
0
0
1
1
1
1
1
Sequential
Interleave
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
2
2
0
1
1
0
4
4
1
0
Reserved
1
1
8
3
8
1
1
Reserved
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
Write Burst Length
Length
0
1
A9
0
1
0
Burst
1
1
1
Single Bit
Full Page Length : x32 (256)
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Rev. 1.0 (Oct. 2000)
- 11
K4S643232E
CMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Rev. 1.0 (Oct. 2000)
- 12
K4S643232E
CMOS SDRAM
DEVICE OPERATIONS
CLOCK (CLK)
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
POWER-UP
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the-
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + tSS" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
SDRAMs must be powered up and initialized in a pre-
defined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode reg-
ister.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as four independent banks of 524,288
words x 32 bits memory arrays. The BA0 ~ BA1 inputs are
latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
ADDRESS INPUTS (A0 ~ A10)
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10).
The 11 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
Rev. 1.0 (Oct. 2000)
- 13
K4S643232E
CMOS SDRAM
DEVICE OPERATIONS (Continued)
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min). Every SDRAM bank
activate command must satisfy tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode
register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A0 ~ A2, burst type uses
A3, CAS latency (read latency from column address) use A4 ~
A6, vendor specific options or test mode use A7 ~ A8, A10/AP
and BA0 ~ BA1. The write burst length is programmed using A9.
A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal
SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.
BURST READ
The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read com-
mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com-
mand is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out-
puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.
BANK ACTIVATE
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SDRAM has four
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before another bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
BURST WRITE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com-
pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.
Rev. 1.0 (Oct. 2000)
- 14
K4S643232E
CMOS SDRAM
DEVICE OPERATIONS (Continued)
AUTO REFRESH
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh com-
mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by tRFC(min). The minimum number of
clock cycles required can be calculated by driving tRFC with
clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. All banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for nor-
mal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once in
64ms.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1
of the bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of tRFC before the SDRAM reaches idle state to
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 4096
auto refresh cycles immediately after exiting in self refresh
mode.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after all banks have satisfied tRAS(min) require-
ment, performs precharge on all banks. At the end of tRP after
performing precharge to all the banks, both banks are in idle
state.
Rev. 1.0 (Oct. 2000)
- 15
K4S643232E
CMOS SDRAM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4
2) Clock Suspended During Read (BL=4)
CLK
CMD
CKE
WR
RD
Masked by CKE
Masked by CKE
Internal
CKE
Q1
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
D2
D2
D3
D3
Q0
Q2
Q1
Q3
Q2
Q3
Q0
Not Written
SuspendedDout
2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
WR
RD
CMD
DQM
Masked byDQM
D3
Masked by DQM
Hi-Z
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
Q0
Q2
Q1
Q3
Q2
Hi-Z
D3
Q3
DQM to Data-in Mask = 0
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) Note 2
CLK
CMD
RD
CKE
DQM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ(CL2)
DQ(CL3)
Q6
Q5
Q0
Q2
Q1
Q4
Q3
Q7
Q6
Q8
Q7
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
Rev. 1.0 (Oct. 2000)
- 16
K4S643232E
CMOS SDRAM
3. CAS Interrupt (I)
Note 1
1) Read interrupted by Read (BL=4)
CLK
CMD
ADD
RD RD
A
B
DQ(CL2)
DQ(CL3)
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
tCCD
Note 2
2) Write interrupted by Write (BL=2)
CLK
3) Write interrupted by Read (BL=2)
WR RD
WR WR
CMD
tCCD
Note 2
tCCD
Note 2
A
B
A
B
ADD
DQ
DA0 DB0 DB1
DQ(CL2)
DQ(CL3)
DA0
DA0
QB0 QB1
QB0 QB1
tCDL
Note 3
tCDL
Note 3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
Rev. 1.0 (Oct. 2000)
- 17
K4S643232E
CMOS SDRAM
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
RD WR
D0
D1
D2
D3
D2
RD
WR
DQM
DQ
Hi-Z
D0
D1
D3
RD
WR
iii) CMD
DQM
DQ
Hi-Z
D0
D1
D2
D1
D3
D2
RD
WR
iv) CMD
DQM
DQ
Hi-Z
Q0
D0
D3
Note 1
(b) CL=3, BL=4
CLK
i) CMD
RD WR
DQM
DQ
D0
D1
D2
D3
D2
ii) CMD
RD
WR
DQM
DQ
D0
D1
D3
D2
RD
RD
WR
iii) CMD
DQM
DQ
D0
D1
D3
WR
iii) CMD
DQM
DQ
Hi-Z
D0
D1
D2
D1
D3
D2
RD
WR
iv) CMD
DQM
DQ
Hi-Z
D0
D3
Q0
Note 1
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
Rev. 1.0 (Oct. 2000)
- 18
K4S643232E
CMOS SDRAM
5. Write Interrupted by Precharge & DQM
CLK
Note 3
WR
PRE
CMD
Note 2
DQM
DQ
D0
D1
D2
D3
Masked by DQM
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
*Note :
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
6. Precharge
2) Normal Read (BL=4)
CLK
1) Normal Write (BL=4)
CLK
Note 2
1
WR
D0
CMD
DQ
PRE
CMD
RD
PRE
Q2
D1
D2
D3
DQ(CL2)
Q0
Q1
Q0
Q3
tRDL
Note 1
2
DQ(CL3)
Q1
Q2
Q3
7. Auto Precharge
1) Normal Write (BL=4)
CLK
2) Normal Read (BL=4)
CLK
WR
D0
CMD
DQ
CMD
DQ(CL2)
DQ(CL3)
RD
D1
D2
D3
D0
D1
D0
D2
D1
D3
D2
Note 3,4
Auto Precharge Starts
D3
Note 3
Auto Precharge Starts
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Rev. 1.0 (Oct. 2000)
- 19
K4S643232E
CMOS SDRAM
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
CLK
2) Write Burst Stop (BL=8)
CLK
WR
STOP
CMD
DQM
WR
CMD
DQM
PRE
DQ
DQ
D0
D1
D2
D3
D0
D1
D2
D3
D4
D5
tRDL Note 1
tBDL Note 2
3) Read Interrupted by Precharge (BL=4)
CLK
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
PRE
Q0
STOP
Q0
CMD
DQ(CL2)
DQ(CL3)
RD
Note 3
1
1
Q1
Q0
Q1
Q0
2
2
Q1
Q1
9. MRS
1) Mode Register Set
CLK
Note 4
CMD
PRE
MRS
ACT
tRP
2CLK
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : All banks precharge if necessary.
MRS can be issued only at all banks precharge state.
Rev. 1.0 (Oct. 2000)
- 20
K4S643232E
CMOS SDRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
CLK
2) Power Down (=Precharge Power Down) Exit
CLK
CKE
CKE
tSS
tSS
Internal
Note 1
Internal
CLK
Note 2
CLK
CMD
CMD
ACT
NOP
RD
11. Auto Refresh & Self Refresh
Note 3
1) Auto Refresh & Self Refresh
CLK
¡ó
¡ó
Note 4
Note 5
CMD
CKE
PRE
AR
CMD
¡ó
¡ó
tRP
tRFC
Note 6
2) Self Refresh
CLK
¡ó
¡ó
Note 4
CMD
CKE
PRE
SR
CMD
¡ó
tRP
tRFC
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
Rev. 1.0 (Oct. 2000)
- 21
K4S643232E
CMOS SDRAM
12. About Burst Type Control
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
Sequential Counting
Basic
MODE
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Interleave Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random
MODE
Random column Access
tCCD = 1 CLK
13. About Burst Length Control
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
1
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
2
Basic
MODE
4
At MRS A2,1,0 = "010".
At MRS A2,1,0 = "011".
8
At MRS A2,1,0 = "111".
Wrap around mode(Infinite burst length) should be stopped by burst stop
Ras interrupt or CAS interrupt
Full Page
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, tRAS should not be violated.
Special
BRSW
MODE
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Random
Burst Stop
MODE
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
RAS Interrupt
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
(Interrupted by Precharge)
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
Rev. 1.0 (Oct. 2000)
- 22
K4S643232E
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
CS
RAS
CAS
WE
BA
ADDR
ACTION
Note
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
X
ILLEGAL
2
2
X
H
L
BA
BA
BA
X
CA, A10/AP ILLEGAL
IDLE
H
H
L
RA
Row (& Bank) Active ; Latch RA
L
A10/AP
NOP
4
5
5
L
H
L
X
Auto Refresh or Self Refresh
L
L
OP code
X
OP code
Mode Register Access
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP
X
NOP
X
ILLEGAL
2
Row
Active
H
L
BA
BA
BA
BA
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
L
H
H
L
H
L
RA
ILLEGAL
2
L
A10/AP
Precharge
L
X
X
H
L
X
X
X
X
ILLEGAL
X
H
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
X
X
H
L
BA
BA
BA
BA
X
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
Read
L
3
2
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term burst, Precharge timing for Reads
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
X
X
H
L
BA
BA
BA
BA
X
CA, A10/AP Term burst, New read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
3
3
2
3
Write
L
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term burst, precharge timing for Writes
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
X
Read with
Auto
Precharge
X
X
X
X
X
H
L
BA
BA
X
CA, A10/AP ILLEGAL
H
L
RA, RA10
ILLEGAL
2
2
L
X
X
X
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
X
Write with
Auto
Precharge
X
X
X
X
X
H
L
BA
BA
X
CA, A10/AP ILLEGAL
H
L
RA, RA10
ILLEGAL
L
X
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP --> Idle after tRP
NOP --> Idle after tRP
ILLEGAL
X
X
Pre-
charging
X
X
2
2
2
4
X
H
L
BA
BA
BA
CA
RA
A10/AP
ILLEGAL
H
H
ILLEGAL
L
NOP --> Idle after tRPL
Rev. 1.0 (Oct. 2000)
- 23
K4S643232E
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
CS
RAS
CAS
WE
BA
ADDR
ACTION
Note
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
X
H
H
L
X
X
H
L
X
X
X
ILLEGAL
X
NOP --> Row Active after tRCD
NOP --> Row Active after tRCD
ILLEGAL
X
X
Row
Activating
X
X
2
2
2
2
X
H
L
BA
BA
BA
X
CA
ILLEGAL
H
H
L
RA
ILLEGAL
L
A10/AP
ILLEGAL
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
X
H
H
L
X
H
L
X
NOP --> Idle after tRFC
NOP --> Idle after tRFC
ILLEGAL
X
Refreshing
X
H
L
X
ILLEGAL
L
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP --> Idle after 2 clocks
NOP --> Idle after 2 clocks
ILLEGAL
X
Mode
Register
Accessing
X
X
X
X
ILLEGAL
X
X
ILLEGAL
Abbreviations : RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Rev. 1.0 (Oct. 2000)
- 24
K4S643232E
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 2)
CKE
n
Current
State
CKE
(n-1)
CS
RAS
CAS
WE
ADDR
ACTION
Note
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
INVALID
X
Exit Self Refresh --> Idle after tRFC (ABI)
Exit Self Refresh --> Idle after tRFC (ABI)
ILLEGAL
6
6
L
X
Self
Refresh
L
L
X
L
L
X
X
X
X
X
H
L
X
ILLEGAL
L
L
X
X
X
X
H
H
L
X
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
X
NOP (Maintain Self Refresh)
INVALID
H
L
X
H
H
H
H
H
L
X
X
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
All
Banks
Precharge
Power
L
X
7
7
L
L
X
L
L
X
X
X
X
X
H
L
X
ILLEGAL
Down
L
L
X
X
X
X
H
H
L
X
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
X
NOP (Maintain Low Power Mode)
Refer to Table 1
H
H
H
H
H
H
H
H
L
H
L
X
X
Enter Power Down
Enter Power Down
ILLEGAL
L
X
8
8
L
L
X
All
Banks
Idle
L
L
X
H
H
L
X
ILLEGAL
L
L
H
L
RA
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
L
L
L
X
8
L
L
L
L
OP Code
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend
Any State
other than
Listed
9
9
H
L
above
L
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
Rev. 1.0 (Oct. 2000)
- 25
K4S643232E
CMOS SDRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
CS
tRAS
tRC
*Note 1
tSH
tRP
tRCD
tSS
tSH
tSS
RAS
CAS
tCCD
tSH
tSS
tSH
Ra
Ca
Cb
Cc
Rb
ADDR
tSS
*Note 2
*Note 2,3
*Note 2,3
*Note 2,3 *Note 4
*Note 2
BA0 ~ BA1
BS
BS
BS
BS
BS
BS
*Note 3
*Note 3
*Note 3 *Note 4
Ra
A10/AP
DQ
Rb
tRAC
tSH
tSAC
tSLZ
Qa
Db
Qc
tSS
tOH
tSH
WE
tSS
tSS
tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don't care
Rev. 1.0 (Oct. 2000)
- 26
K4S643232E
CMOS SDRAM
*Note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA0~BA1.
BA0 BA1
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP BA0 BA1
Operation
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Disable auto precharge, leave bank C active at end of burst.
Disable auto precharge, leave bank D active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
0
1
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
BA1
A10/AP BA0
Precharge
Bank A
0
0
1
1
x
0
0
0
0
1
0
0
1
1
x
Bank B
Bank C
Bank D
All Banks
Rev. 1.0 (Oct. 2000)
- 27
K4S643232E
CMOS SDRAM
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
High level is necessary
CKE
CS
tRP
tRC
RAS
CAS
Key
RAa
ADDR
BA0
BA1
RAa
A10/AP
High-Z
DQ
WE
DQM
High level is necessary
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
: Don't care
Rev. 1.0 (Oct. 2000)
- 28
K4S643232E
CMOS SDRAM
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
*Note 1
tRC
CS
tRCD
RAS
CAS
ADDR
BA0
*Note 2
Ra
Ca
Rb
Cb
BA1
Ra
Rb
A10/AP
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
CL=2
tRAC
tRDL
tRDL
*Note 4
tSAC
tSHZ
*Note 3
DQ
tOH
Qa0 Qa1 Qa2 Qa3
CL=3
Db0 Db1 Db2 Db3
tRAC
*Note 3
tSAC
*Note 4
tSHZ
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Rev. 1.0 (Oct. 2000)
- 29
K4S643232E
CMOS SDRAM
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
tRCD
RAS
CAS
*Note 2
Ra
Ca
Cb
Cc
Cd
ADDR
BA0
BA1
Ra
A10/AP
tRDL
Qa0 Qa1 Qb0 Qb1 Qb2
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
CL=2
DQ
CL=3
Dc0 Dc1 Dd0 Dd1
tCDL
WE
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
Rev. 1.0 (Oct. 2000)
- 30
K4S643232E
CMOS SDRAM
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
*Note 1
CS
RAS
*Note 2
CAS
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
ADDR
BA0
BA1
RAa
RBb
RCc
RDd
A10/AP
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
CL=2
DQ
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
CL=3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(C-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Row Active
(B-Bank)
Row Acive
(C-Bank)
Row Active
(D-Bank)
Precharge
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
: Don't care
*Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Rev. 1.0 (Oct. 2000)
- 31
K4S643232E
CMOS SDRAM
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 2
RAa
RBb CAa
CBb RCc
RDd CCc
CDd
ADDR
BA0
BA1
RCc
RDd
A10/AP
RAa
RBb
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
DQ
tCDL
tRDL
WE
*Note 1
DQM
Precharge
(All Banks)
Row Active
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
: Don't care
*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Rev. 1.0 (Oct. 2000)
- 32
K4S643232E
CMOS SDRAM
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
BA0
RAa
CAa
RDb
CDb RBc
CBc
BA1
RAa
RBb
RAc
A10/AP
*Note 1
tCDL
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
QAa0 QAa1 QAa2 QAa3
CL=2
DQ
QAa0 QAa1 QAa2 QAa3
CL=3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Precharge
(B-Bank)
: Don't care
*Note : 1. tCDL should be met to complete write.
Rev. 1.0 (Oct. 2000)
- 33
K4S643232E
CMOS SDRAM
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
RAa
CBb
RBb CAa
ADDR
BA0
BA1
RAa
RBb
A10/AP
DQ
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAa0 QAa1 QAa2 QAa3
(CL=2)
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
WE
DQM
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
Auto Precharge
Start Point
Row Active
(A-Bank)
Write with
Auto Precharge
(B-Bank)
(A-Bank)
(B-Bank)
Row Active
(B-Bank)
: Don¢t care
*Note :
1. tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
Rev. 1.0 (Oct. 2000)
- 34
K4S643232E
CMOS SDRAM
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
Ra
Rb
Ca
Cb
Ra
Ca
ADDR
BA0
BA1
A10/AP
Ra
Rb
Ra
Qa0
Qa1
Qa0
Qb0
Qa1
Qb1
Qb0
Qb2
Qb3
Da0
Da0
Da1
Da1
DQ CL=2
Qb1 Qb2
Qb3
CL=3
WE
DQM
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
Read with
Auto Pre
charge
Write with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
Precharge
(B-Bank)
Row Active
(A-Bank)
(A-Bank)
(A-Bank)*
Row Active
(B-Bank)
: Don't care
*Note:
* When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Rev. 1.0 (Oct. 2000)
- 35
K4S643232E
CMOS SDRAM
Read & Write Cycle with Auto Precharge III @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
Ra
Ca
Rb
Cb
ADDR
BA0
BA1
A10/AP
Ra
Rb
Qa0
Qa1
Qa0
Qa2
Qa3
Qa2
Qb0
Qb1
Qb0
Qb2
Qb3
Qb2
DQ CL=2
Qa1
Qa3
Qb1
Qb3
CL=3
WE
DQM
*
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(A-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
: Don't care
*Note :
* Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
Rev. 1.0 (Oct. 2000)
- 36
K4S643232E
CMOS SDRAM
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A10/AP
DQ
Ra
Qa0 Qa1
Qa2
Qa3
Qb0 Qb1
tSHZ
Dc0
Dc2
tSHZ
WE
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Write
DQM
Write
DQM
Read DQM
Write
Clock
Suspension
: Don't care
*Note : 1. DQM is needed to prevent bus contention.
Rev. 1.0 (Oct. 2000)
- 37
K4S643232E
CMOS SDRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
RAa
CAa
CAb
ADDR
BA0
BA1
RAa
A10/AP
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
Rev. 1.0 (Oct. 2000)
- 38
K4S643232E
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
RAa
CAa
CAb
ADDR
BA0
BA1
A10/AP
DQ
RAa
tBDL
tRDL
*Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
*Note :
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC
parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
Rev. 1.0 (Oct. 2000)
- 39
K4S643232E
CMOS SDRAM
Burst Read Single bit Write Cycle @Burst Length=2
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
*Note 1
HIGH
CS
RAS
CAS
*Note 2
RAa
CAa RBb CAb
RCc
CBc
CCd
ADDR
BA0
BA1
RAa
RBb
RAc
A10/AP
DAa0
QAb0 QAb1
DBc0
DBc0
QCd0 QCd1
CL=2
DQ
DAa0
QAb0 QAb1
QCd0 QCd1
CL=3
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Precharge
(C-Bank)
Write
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
: Don't care
*Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Rev. 1.0 (Oct. 2000)
- 40
K4S643232E
CMOS SDRAM
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
CLOCK
CKE
tSS
tSS
*Note 1
*Note 2
tSS
*Note 2
*Note 3
CS
RAS
CAS
Ra
Ca
ADDR
BA
Ra
A10/AP
DQ
tSHZ
Qa2
Qa0
Qa1
WE
DQM
Precharge
Power-down
Entry
Row Active
Read
Precharge
Active
Precharge
Active
Power-down
Exit
Power-down
Exit
Power-down
Entry
: Don ¡Ç t Care
*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Rev. 1.0 (Oct. 2000)
- 41
K4S643232E
CMOS SDRAM
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
tRFCmin
15 16
17
18
19
CLOCK
CKE
*Note 4
*Note 2
*Note 6
*Note 1
*Note 3
tSS
*Note 5
CS
RAS
CAS
*Note 7
ADDR
BA0~BA1
A10/AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note : TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
Rev. 1.0 (Oct. 2000)
- 42
K4S643232E
CMOS SDRAM
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
CLOCK
CKE
HIGH
HIGH
CS
*Note 2
tRFC
RAS
CAS
*Note 1
*Note 3
ADDR
DQ
Key
Ra
Hi-Z
Hi-Z
WE
ó
DQM
MRS
New
Auto Refresh
New Command
Command
: Don't care
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Rev. 1.0 (Oct. 2000)
- 43
K4S643232E
CMOS SDRAM
PACKAGE DIMENSIONS
86-TSOP2-400F
Unit : Millimeters
0~8°C
0.25
0.010
TYP
#86
#44
#43
#1
+0.075
-0.035
+0.003
-0.001
0.125
0.005
22.62
0.891
MAX
22.22
0.875
± 0.10
0.21 ± 0.05
± 0.10
1.00
0.039
1.20
0.047
MAX
± 0.004
± 0.002
± 0.004
0.008
0.10
MAX
0.004
0.05
0.010
MIN
0.50
0.0197
0.61
0.024
+0.10
-0.03
(
)
0.20
Rev. 1.0 (Oct. 2000)
- 44
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