K4S641632N-LP750 [SAMSUNG]
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT AND HALOGEN FREE, TSOP2-54;
| 型号： | K4S641632N-LP750 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, ROHS COMPLIANT AND HALOGEN FREE, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S641632N
Industrial Synchronous DRAM
64Mb N-die SDRAM Specification
54 TSOP-II
with Lead-Free and Halogen-Free
(RoHS compliant)
Industrial Temp. -40 to 85°C
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.12 July 2008
1 of 14
K4S641632N
Industrial Synchronous DRAM
Table of Contents
1.0 FEATURES .....................................................................................................................................4
2.0 GENERAL DESCRIPTION .............................................................................................................4
3.0 Ordering Information ....................................................................................................................4
4.0 Package Physical Dimension ......................................................................................................5
5.0 FUNCTIONAL BLOCK DIAGRAM .................................................................................................6
6.0 PIN CONFIGURATION ...................................................................................................................7
7.0 Input/Output Function Description .............................................................................................7
8.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................8
9.0 DC OPERATING CONDITIONS .....................................................................................................8
10.0 CAPACITANCE ............................................................................................................................8
11.0 DC CHARACTERISTICS (x16).....................................................................................................9
12.0 AC OPERATING TEST CONDITIONS .......................................................................................10
13.0 OPERATING AC PARAMETER .................................................................................................10
14.0 AC CHARACTERISTICS ...........................................................................................................11
15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS ................................................................11
16.0 IBIS SPECIFICATION ................................................................................................................12
17.0 SIMPLIFIED TRUTH TABLE ......................................................................................................14
Rev. 1.12 July 2008
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K4S641632N
Industrial Synchronous DRAM
Revision History
Revision
1.0
Month
December
December
March
Year
2007
2007
2008
2008
History
- Release SPEC revision 1.0
- Revised ICC6 current SPEC of lowpower
- Added Package pin out lead width
1.1
1.11
1.12
July
- Corrected typo of temperature condition on page 10
Rev. 1.12 July 2008
3 of 14
K4S641632N
Industrial Synchronous DRAM
1M x 16Bit x 4Banks SDRAM
1.0 FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Lead-Free and Halogen-Free Package
• RoHS compliant
• Support Industrial Temp (-40 to 85°C)
2.0 GENERAL DESCRIPTION
The K4S641632N is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/
O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-
cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S641632N-LI/P60
K4S641632N-LI/P75
166MHz(CL=3)
133MHz(CL=3)
54pin TSOP(II)
Lead-Free & Halogen-Free
4Mb x 16
LVTTL
Organization
Row Address
Column Address
4Mx16
A0~A11
A0-A7
Row & Column address configuration
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K4S641632N
Industrial Synchronous DRAM
4.0 Package Physical Dimension
Unit : mm
#54
#28
#1
#27
(1.50)
+0.075
0.125
- 0.035
22.22 ± 0.10
(10°)
0.10 MAX
[
(10°)
0.80TYP
0.075 MAX
[
(0.71)
[0.80 ± 0.08]
Detail A
Detail B
Detail B
0.25TYP
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
(0° ∼ 8°)
+0.10
- 0.05
+0.10
0.35
- 0.05
0.30
54Pin TSOP(II) Package Dimension
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K4S641632N
Industrial Synchronous DRAM
5.0 FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
1M x 16
1M x 16
DQi
1M x 16
CLK
ADD
1M x 16
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev. 1.12 July 2008
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K4S641632N
Industrial Synchronous DRAM
6.0 PIN CONFIGURATION
x16
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
1
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
2
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
LDQM
WE
N.C/RFU
UDQM
CLK
CKE
N.C
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A11
A9
A8
A7
A1
A6
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
A2
A5
A3
A4
VDD
VSS
7.0 Input/Output Function Description
Pin
Name
System clock
Description
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,
Column address : (x16 : CA0 ~ CA7)
A0 ~ A11
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
CAS
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
Data inputs/outputs are multiplexed on the same pins.
(x16 : DQ0 ~ 15)
DQ0 ~ N
Data input/output
VDD/VSS
VDDQ/VSSQ
Power supply/ground
Data output power/ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connection
/reserved for future use
N.C/RFU
This pin is recommended to be left No Connection on the device.
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K4S641632N
Industrial Synchronous DRAM
8.0 ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
Symbol
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
VIN, VOUT
VDD, VDDQ
TSTG
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9.0 DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40 to 85°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
3.6
Unit
V
Note
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDD+0.3
0.8
V
1
VIL
V
2
VOH
-
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(VDD = 3.3V, TA = 23°C, f = 1MHz)
10.0 CAPACITANCE
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
Note
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
pF
CADD
COUT
pF
(x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15)
pF
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K4S641632N
Industrial Synchronous DRAM
11.0 DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = -40 to 85°C for x16 only)
Version
Parameter
Symbol
Test Condition
Unit
Note
60
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
ICC1
80
65
mA
mA
1
(One bank active)
ICC2P
CKE ≤ VIL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
2
2
Precharge standby current in
power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
15
10
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
4
4
Active standby current in
power-down mode
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3N
30
25
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
120
120
110
110
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
mA
mA
uA
2
3
4
I
P
1
400
Self refresh current
CKE ≤ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641632N-LI
4. K4S641632N-LP
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.12 July 2008
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K4S641632N
Industrial Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = -40 to 85°C)
12.0 AC OPERATING TEST CONDITIONS
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
30pF
30pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
(AC operating conditions unless otherwise noted)
13.0 OPERATING AC PARAMETER
Version
Parameter
Symbol
Unit
Note
60
12
18
18
42
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
ns
1
1
1
1
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
100
us
Row cycle time
60
65
ns
1, 6
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
CLK
CLK
CLK
2,5,6
2 CLK + tRP
5
2
2
3
1
1
1
2
1
Col. address to col. address delay
CAS latency = 3
CAS latency = 2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
Rev. 1.12 July 2008
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K4S641632N
Industrial Synchronous DRAM
(AC operating conditions unless otherwise noted)
14.0 AC CHARACTERISTICS
60
75
Parameter
Symbol
Unit
ns
Note
1
Min
6
10
-
Max
Min
7.5
10
-
-
3
Max
CAS latency=3
CLK cycle time
tCC
tSAC
tOH
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5
6
-
5.4
6
-
-
CLK to valid
output delay
ns
1,2
2
-
2.5
3
Output data
hold time
ns
-
3
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
tCH
tCL
tSS
2.5
2.5
1.5
1
-
-
-
-
2.5
2.5
1.5
0.8
1
-
-
-
-
ns
ns
ns
ns
ns
3
3
3, 4
3, 4
2
tSH
tSLZ
1
-
-
CAS latency=3
CAS latency=2
-
-
5
6
-
-
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time
tSH applies for address holde time, clock enable hold time, commend hold time and data hold time
15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
Output rise time
trh
1.37
4.37
Volts/ns
Volts/ns
Volts/ns
Volts/ns
3
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
3
Measure in linear
region : 1.2V ~ 1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~ 1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
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K4S641632N
Industrial Synchronous DRAM
16.0 IBIS SPECIFICATION
200MHz/133MHz Pull-up
0
0.5
1
1.5
2
2.5
3
3.5
IOH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
200MHz/133MHz 200MHz/133MHz
Voltage
Min
I (mA)
-
Max
(V)
I (mA)
-1.68
3.45
3.30
3.00
2.70
2.50
1.95
1.80
1.65
1.50
1.40
1.00
0.20
-
-19.11
-51.87
-90.44
-107.31
-137.9
-158.34
-173.6
-188.79
-199.01
-241.15
-351.68
-0.35
-3.75
-6.65
-13.75
-17.75
-20.55
-23.55
-26.2
-36.25
-46.5
Voltage
IOH Min (200MHz / 133MHz)
IOH Max (200MHz / 133MHz)
200MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
250
200
150
100
50
200MHz/133MHz 200MHz/133MHz
Voltage
Min
I (mA)
43.92
-
Max
I (mA)
155.82
-
153.72
148.40
146.02
141.75
136.08
131.39
105.84
93.66
75.25
49.14
(V)
3.45
3.30
3.00
1.95
1.80
1.65
1.50
1.40
1.00
0.85
0.65
0.40
43.36
41.20
40.56
39.60
38.40
37.28
30.08
26.64
21.52
14.16
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (200MHz / 133MHz)
IOL Max (200MHz / 133MHz)
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K4S641632N
Industrial Synchronous DRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
20
15
10
5
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
VSS Clamp @ CLK, CKE, CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 1.12 July 2008
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K4S641632N
Industrial Synchronous DRAM
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
17.0 SIMPLIFIED TRUTH TABLE
A11,
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
A9 ~ A0
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
3
3
3
L
L
L
H
X
X
X
X
Entry
Exit
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
L
H
H
H
X
X
Bank active & row addr.
Read &
column address
X
X
V
V
Row address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
4,5
6
Column
address
L
H
L
H
Write &
column address
Column
address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
Burst stop
Precharge
X
Bank selection
All banks
V
X
L
H
X
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.12 July 2008
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