K4S283233E-SG750 [SAMSUNG]
Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, 11 X 13 MM, FBGA-90;
| 型号： | K4S283233E-SG750 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, 11 X 13 MM, FBGA-90 动态存储器 |
| 文件： | 总10页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FEATURES
GENERAL DESCRIPTION
The K4S283233E is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32
bits, fabricated with SAMSUNG¢s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth and
high performance memory system applications.
• 3.0V & 3.3V power supply
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• EMRS cycle with address key programs.
-. PASR(Partial Array Self Refresh)
-. Internal TCSR(Temperature Compensated Self Refresh)
• All inputs are sampled at the positive going edge of the system
clock
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
• Burst read single-bit write operation
• DQM for masking
K4S283233E-S(D)E/N/G/C/L/F60 166MHz(CL=3)
133MHz(CL=3)
K4S283233E-S(D)E/N/G/C/L/F75
105MHz(CL=2)
90FBGA
• Auto & self refresh
LVCMOS
Pb
• 64ms refresh period (4K cycle).
K4S283233E-S(D)E/N/G/C/L/F1H 105MHz(CL=2)
(Pb Free)
• Extended Temperature Operation (-25°C ~ 85°C).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 90Balls Monolithic FBGA(11mm x 13mm)
• Pb for -SXXX, Pb Free for -DXXX.
*1
K4S283233E-S(D)E/N/G/C/L/F1L
105MHz(CL=3)
- S(D)E/N/G : Normal/Low Power, Extended Temperature.
- S(D)C/L/F : Normal/Low Power, Commercial Temperature.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
1M x 32
1M x 32
1M x 32
1M x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
Package Dimension and Pin Configuration
*1
< Bottom View >
*2
< Top View >
E
1
90Ball(6x15) CSP
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
DQ26 DQ24
VSS
VSSQ
VDD
VDDQ
DQ23 DQ21
VSSQ DQ19
DQ28
VSSQ
VSSQ
VDDQ
VSS
VDDQ
DQ27 DQ25 DQ22 DQ20
DQ29 DQ30 DQ17 DQ18
VDDQ
VDDQ
VSSQ
VDD
DQ31
DQM3
A5
NC
A3
NC
A2
DQ16
DQM2
A0
G
H
J
G
H
J
A4
A6
A10
NC
A1
A7
A8
NC
A9
BA1
CS
A11
K
L
CLK
CKE
NC
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
K
L
DQM1
VDDQ
VSSQ
VSSQ
DQ11
NC
VSS
DQ9
WE
M
N
P
R
DQ8
DQ10
DQ7
DQ5
DQ3
VSSQ
DQ0
M
N
P
R
DQ12 DQ14
VDDQ
VSSQ
VSS
E
DQ13 DQ15
E/2
*2: Top View
Pin Name
Pin Function
System Clock
CLK
CS
Chip Select
CKE
Clock Enable
A
A0 ~ A11
BA0 ~ BA1
RAS
Address
A1
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Substrate(2Layer)
z
b
CAS
*1: Bottom View
WE
*2
< Top View >
DQM0 ~DQM3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
#A1 Ball Origin Indicator
[Unit:mm]
Symbol
Min
Typ
1.40
0.35
11.00
6.40
13.00
11.20
0.80
0.45
-
Max
A
1.35
1.45
A
0.30
0.40
1
E
-
-
E
-
-
1
D
-
-
-
D
-
1
e
-
0.40
-
-
b
z
0.50
0.10
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
VIN, VOUT
VDD, VDDQ
TSTG
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Supply voltage
Symbol
VDD
VDDQ
VIH
Min
2.7
2.7
2.2
-0.3
2.4
-
Typ
3.0
3.0
3.0
0
Max
Unit
V
Note
3.6
3.6
V
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDDQ+0.3
V
1
VIL
0.5
-
V
2
VOH
VOL
ILI
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.3V AC. The overshoot voltage duration is£ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V£ VIN £ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE (VDD = 3.0V & 3.3, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
CCLK
CIN
Min
Max
4.0
4.0
4.0
6.0
Unit
Note
Clock
-
-
-
-
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM0~ DQM3
Address(A0 ~ A11, BA0 ~ BA1)
DQ0 ~ DQ31
CADD
COUT
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
Unit Note
-60
-75
-1H
-1L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating Current
(One Bank Active)
ICC1
100
85
85
80
mA
mA
1
ICC2P CKE £ VIL (max), tCC = 10ns
0.5
0.5
Precharge Standby Current
in power-down mode
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC2N
16
8
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC2NS
Input signals are stable
ICC3P CKE £ VIL (max), tCC = 10ns
5
5
Active Standby Current
in power-down mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
26
22
mA
mA
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Operating Current
(Burst Mode)
Page burst
4Banks Activated
tCCD = 2CLKs
ICC4
110
180
85
80
80
mA
1
Refresh Current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
160
150
130
mA
uA
°C
2
4
5
3
-S(D)E/C
-S(D)N/L
1500
800
Internal TCSR
Max 40
Max 85/70
800
Self Refresh Current
4 Banks
500
460
440
-S(D)G/F
uA
6
2 Banks
1 Bank
650
550
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In Commercial Temp : Max 40°C/Max 70°C, In Extended Temp : Max 40°C/Max 85°C
4. K4S283233E-S(D)E/C**
5. K4S283233E-S(D)N/L**
6. K4S283233E-S(D)G/F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ /VSSQ)
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
AC input levels (Vih/Vil)
Value
Unit
V
2.4 / 0.4
Input timing measurement reference level
Input rise and fall time
0.5 x VDDQ
tr/tf = 1/1
0.5 x VDDQ
See Fig. 2
V
ns
V
Output timing measurement reference level
Output load condition
VDDQ
Vtt = 0.5 x VDDQ
1200W
50W
VOH (DC) =2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
30pF
Output
Output
Z0 = 50W
30pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
-1L
Note
- 60
12
- 75
-1H
19
19
19
50
Row active to row active delay
RAS to CAS delay
tRRD (min)
tRCD (min)
tRP(min)
15
19
19
45
19
24
24
60
ns
ns
1
1
1
1
18
Row precharge time
18
ns
tRAS(min)
tRAS (max)
tRC(min)
42
ns
Row active time
100
2
us
Row cycle time
60
64
69
84
ns
1
2,3
3
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL (min)
tCDL(min)
tBDL (min)
tCCD (min)
CLK
-
tRDL + tRP
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
4
CAS latency=3
CAS latency=2
CAS latency=1
Number of valid output data
ea
5
-
1
-
0
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum 2RDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and
precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- 60
- 75
-1H
-1L
Parameter
Symbol
Unit Note
Min
Max
Min
7.5
9.5
-
Max
Min
9.5
9.5
-
Max
Min
Max
CAS latency=3
6.0
9.5
12
25
CLK cycle time
tCC
1000
1000
1000
1000
ns
ns
ns
1
1,2
2
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
-
-
5.4
6
7
-
7
7
-
7
8
CLK to valid output
delay
tSAC
tOH
-
-
20
2.5
-
2.5
2.5
-
2.5
2.5
-
2.5
2.5
2.5
3
Output data hold time
-
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
2.0
1.0
1
2.5
2.5
2.0
1.0
1
3
ns
ns
ns
ns
ns
3
3
3
3
2
3
3
tSS
tSH
2.5
1.5
1
2.5
1.5
1
Input hold time
CLK to output in Low-Z
tSLZ
CAS latency=3
CAS latency=2
CAS latency=1
5.4
6
7
-
7
7
-
7
8
CLK to output in Hi-Z
tSHZ
ns
-
-
20
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
A11,
A9 ~ A 0
COMMAND
Mode Register Set
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Register
Refresh
H
X
H
L
L
L
L
L
X
OP CODE
1, 2
3
Auto Refresh
H
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
3
Bank Active & Row Addr.
X
X
V
V
Row Address
Column
Address
(A0~ A7)
Read &
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4, 5
4
L
H
L
H
Column Address
H
Column
Address
(A0~ A7)
Write &
L
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Column Address
H
4, 5
6
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No Operation Command
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Notes :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
*2
Address
BA0 ~ BA1
A11 ~ A10/AP
A8
A7
A6
A5
A4
A3
A2
A1
A0
A9
"0" Setting for
Normal MRS
*1
Function
W.B.L
Test Mode
CAS Latency
BT
Burst Length
RFU
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Type
Burst Length
A8
0
A7
0
Type
Mode Register Set
Reserved
A6
0
A5
0
A4
0
Latency
A3
0
A2
A1
0
A0
0
BT=0
BT=1
Reserved
1
Sequential
Interleave
Mode Select
0
0
0
0
1
1
1
1
1
2
4
8
1
2
4
8
0
1
0
0
1
1
0
1
1
0
Reserved
0
1
0
2
1
0
1
1
Reserved
0
1
1
3
BA1 BA0
Mode
1
1
Write Burst Length
Length
1
0
0
Reserved
Reserved
Reserved
Reserved
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Setting for
Normal
MRS
A9
0
1
0
1
0
1
0
0
Burst
1
1
0
1
0
1
Single Bit
1
1
1
1
1
* Full Page Length
64Mb : x16(256) / x32(256), 128Mb : x16(512) / x32(256), 256Mb : x16(512) / x32(512), 512Mb : x16(1024) / x32(512)
Register Programmed with Extended MRS
Address
BA1
BA0
A11 ~ A10/AP
A9
A8
RFU
A7
*1
A6
A5
A4
A3
A2
A1
A0
Function
Mode Select
PASR
Extended MRS for PASR(Partial Array Self Refresh)
*3,4
Mode Select
PASR
BA1
BA0
Mode
Normal MRS
A2
A1
0
A0
# of Banks
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
4 Banks(All Banks)
2 Banks(1/2 of All Banks)
1 Bank(1/4 of All Banks)
Reserved
Reserved
0
EMRS for Mobile SDRAM
1
Reserved
*1
1
0
Reserved
Reserved Address
A11~A10/AP
0
A9
0
A8
A7
A6
0
A5
0
A4
0
A3
0
Reserved
1
Reserved
0
0
0
1
Reserved
Notes : 1. RFU(Reserved for future use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. In case of 1 Bank Partial Refresh, one bank(BA1=BA0=0) is selected.
In case of 2 Banks Partial Refresh, two banks(BA1=0) are selected.
4. Mobile SDRAM supports PASR of 4 Banks(128Mb), 2 Banks(64Mb) and 1Bank(32Mb).
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode ; 4 Banks(128Mb), 2 Banks(64Mb), 1 Bank(32Mb).
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- 1 Bank
- 4 Banks
- 2 Banks
Partial Self Refresh Area
Temperature Compensated Self Refresh
1. In order to save power consumption, Mobile SDRAM has includes the Internal temperature sensor and control units to
control the self refresh cycle automatically according to the two temperature range : Max 40°C and Max 85°C(for Extended),
Max 70°C(for Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc 6)
Temperature Range
Unit
- G/F
4 Banks
2 Banks
1 Bank
Max 85/70
Max 40
°
C
800
500
650
460
550
440
uA
°C
B. Power Up Sequence
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue an extended mode register set command to define PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and EMRS command needs to be issued only when PASR is used.
The default state without EMRS command issued is all 4banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with PASR, set PASR mode in EMRS setting stage.
In order to adjust another mode in the state of PASR mode, additional EMRS set is required but power up sequence is
not needed again at this time, In that case, all banks have to be in idle state prior to adjusting EMRS set.
May. 2003
K4S283233E-S(D)E/N/G/C/L/F
Mobile-SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
0
A0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
0
A1
0
A0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
6
7
0
1
2
3
4
0
3
2
5
4
7
6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
May. 2003
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