K4S280432D-TN75 [SAMSUNG]

Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;


型号：	K4S280432D-TN75
厂家：	SAMSUNG
描述：	Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 时钟动态存储器光电二极管内存集成电路
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K4S280432D

CMOS SDRAM

128Mbit SDRAM

(Extended Temp Support)

8M x 4Bit x 4 Banks

Synchronous DRAM

LVTTL

Rev. 0.1

Sept. 2001

* Samsung Electronics reserves the right to change products or specification without notice.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

Revision History

Revision 0.0 (Mar., 2001)

Revision 0.1 (Sep., 2001)

•

Redefined IDD1 & IDD4 in DC Characteristics

Changed the Notes in Operating AC Parameter.

< Before >

5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

< After >

5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

8M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

The K4S280432C is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits,

fabricated with SAMSUNG¢s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance mem-

ory system applications.

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4 & 8 )

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

ORDERING INFORMATION

• Auto & self refresh

Part No.

Max Freq.

Interface Package

• 64ms refresh period (4K Cycle)

K4S280432D-TE/N7C

K4S280432D-TE/N75

K4S280432D-TE/N1H

K4S280432D-TE/N1L

133MHz(CL=2)

133MHz(CL=3)

100MHz(CL=2)

100MHz(CL=3)

LVTTL

TSOP(II)

*E/N : Extended Temperature (-25 to 85 °C)

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

8M x 4

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LRAS

LCBR

LWE

LCAS

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

N.C

VDDQ

VSS

N.C

VSSQ

N.C

DQ3

VDDQ

N.C

VSSQ

N.C

DQ2

VDDQ

N.C

VSS

N.C/RFU

DQM

CLK

CKE

N.C

A11

N.C

DQ0

VSSQ

N.C

VDDQ

N.C

DQ1

VSSQ

N.C

VDD

N.C

CAS

RAS

BA0

BA1

A10/AP

VSS

VDD

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Name

System clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11

A0 ~ A11

BA0 ~ BA1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM

Data input/output mask

DQ0 ~ 3

VDD/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

Data output power/ground

No connection

/reserved for future use

N.C/RFU

This pin is recommended to be left No Connection on the device.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (voltage referenced to VSS = 0V, TA = -25 to 85°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

Typ

Max

3.6

Unit

Note

3.3

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

3.0

VDD+0.3

0.8

VIL

VOH

IOH = -2mA

IOL = 2mA

VOL

0.4

ILI

-10

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ,

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

Clock

RAS, CAS, WE, CS, CKE, DQM

Address

CADD

COUT

DQ0 ~ DQ3

Notes :

1. -75 only specify a maximum value of 3.5pF

2. -75 only specify a maximum value of 3.8pF

3. -75 only specify a maximum value of 6.0pF

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA =-25 to 85°C)

Version

Parameter

Symbol

Test Condition

Burst length = 1

tRC ³ tRC(min)

IO = 0 mA

Unit Note

-7C

-75

-1H

-1L

Operating current

(One bank active)

ICC1

100

ICC2P

CKE £ VIL(max), tCC = 10ns

Precharge standby current

in power-down mode

ICC2PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC2N

Input signals are changed one time during 20ns

Precharge standby current

in non power-down mode

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC2NS

Input signals are stable

ICC3P

CKE £ VIL(max), tCC = 10ns

Active standby current in

power-down mode

ICC3PS CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC3N

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

ICC3NS

Input signals are stable

IO = 0 mA

Operating current

(Burst mode)

Page burst

4Banks Activated

tCCD = 2CLKs

ICC4

110

220

110

200

100

190

100

190

Refresh current

ICC5

ICC6

tRC ³ tRC(min)

CKE £ 0.2V

Self refresh current

800

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S280432D-TE**

4. K4S280432D-TN**

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA =-25 to 85°C)

Parameter

Input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

Vtt = 1.4V

3.3V

50W

1200W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50W

50pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

- 7C

- 75

- 1H

-1L

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

100

Row cycle time

2,5

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

tCCD(min)

CLK

2 CLK + tRP

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

- 7C

- 75

- 1H

- 1L

Parameter

Symbol

tCC

Unit Note

Min

7.5

Max

Min

7.5

Max

Min

Max

Min

Max

CAS latency=3

CLK cycle

time

1000

1,2

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

5.4

CLK to valid

output delay

tSAC

Output data

hold time

tOH

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

2.5

1.5

0.8

2.5

1.5

0.8

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CAS latency=3

CAS latency=2

5.4

CLK to output

in Hi-Z

tSHZ

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

Measure in linear

region : 1.2V ~ 1.8V

Output rise time

trh

1.37

4.37

Volts/ns

Measure in linear

region : 1.2V ~ 1.8V

Output fall time

Output rise time

Output fall time

tfh

trh

tfh

1.30

2.8

3.8

5.6

5.0

Volts/ns

Measure in linear

region : 1.2V ~ 1.8V

3.9

2.9

1,2

Measure in linear

region : 1.2V ~ 1.8V

2.0

Notes :

1. Rise time specification based on 0pF + 50 W to VSS, use these values to design to.

2. Fall time specification based on 0pF + 50 W to VDD, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to VSS.

Rev.0.1 Sept. 2001

K4S280432D

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

A11,

A9 ~ A0

Command

CKEn-1

CKEn

RAS

CAS

DQM BA0,1

A10/AP

Note

Refresh

Mode register set

Auto refresh

OP code

1,2

Entry

Self

refresh

Exit

Bank active & row addr.

Row address

Column

address

(A0~A9, A11)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4,5

Column

address

(A0~A9, A11)

Write &

column address

4,5

Burst stop

Precharge

Bank selection

All banks

Entry

Clock suspend or

active power down

Exit

Entry

Precharge power down mode

Exit

DQM

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev.0.1 Sept. 2001

K4S280432D-TN75 [SAMSUNG]

相关型号：

K4S280432D-TN7C

K4S280432D-TP1H

K4S280432D-TP1L

K4S280432D-TP7C

K4S280432E

K4S280432E-TC75

K4S280432E-TC750

K4S280432E-TC75T

K4S280432E-TC7C

K4S280432E-TC7C0

K4S280432E-TL75

K4S280432E-TL750