K4S1G0732D-UC75_技术文档

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

stacked 1Gb D-die SDRAM Specification

54 TSOP-II with Pb-Free

(RoHS compliant)

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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

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INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

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* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

Table of Contents

1.0 Features....................................................................................................................................... 4

2.0 General Description.................................................................................................................... 4

3.0 Ordering Information.................................................................................................................. 4

4.0 Package Physical Dimension ................................................................................................... 5

5.0 Functional Block Diagram.......................................................................................................... 6

6.0 Pin Configuration (Top view)..................................................................................................... 7

7.0 Pin Function Description ........................................................................................................... 7

8.0 Absolute Maximum Ratings........................................................................................................8

9.0 DC Operating Conditions........................................................................................................... 8

10.0 Capacitance............................................................................................................................... 8

11.0 DC Characteristics (x4) ............................................................................................................9

12.0 DC Characteristics (x8) ..........................................................................................................10

13.0 DC Characteristics (x16) ........................................................................................................11

14.0 AC Operating Test Conditions ...............................................................................................12

15.0 Operating AC Parameter ........................................................................................................12

16.0 AC Characteristics ..................................................................................................................13

17.0 DQ Buffer Output Drive Characteristics ...............................................................................13

18.0 IBIS Specification ................................................................................................................... 14

19.0 Simplified Truth Table ............................................................................................................16

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

Revision History

Revision

Month

Year

History

1.0

November

2005

- Revision 1.0

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM

1.0 Features

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM (x4,x8) for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

• 54pin TSOP II Pb-Free package

• RoHS compliant

2.0 General Description

The K4S1G0632D / K4S1G0732D is 1,073,741,824bits synchronous high data rate Dynamic RAM organized as 4 x 67,108,864/ 4 x

33,554,432 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle

control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable

burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory

system applications

3.0 Ordering Information

Part No.

Orgainization

st.256Mb x4

st.128Mb x8

Max Freq.

133MHz

Interface

Package

K4S1G0632D-UC75

K4S1G0732D-UC75

LVTTL

54pin TSOP(II)

Organization

Row Address

Column Address

st.256Mx4

st.128Mx8

A0~A12

A0-A9, A11

Row & Column address configuration

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

4.0 Package Physical Dimension

0~8°C

0.25 TYP

#54

#28

#27

#1

+0.075

0.125

-0.035

22.53 MAX

22.22

± 0.10

MAX

2.54

0.10

MAX

0.05

MIN

0.80

0.25~0.40

0.71

54Pin TSOP(II) Stack Package Dimension

5.0 Functional Block Diagram

CK,CK,CAS

RAS,WE,DM

CK,CK,CAS

RAS,WE,DM

128Mx4

64Mx8

CKE1,CS1

128Mx4

CKE0,CS0

DQ0 ~ DQ3

DQ0 ~ DQ7

A0-A12,

A0-A13,

BA0,BA1

st.256Mb x 4

st.128Mb x 8

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

6.0 Pin Configuration (Top view)

x8

x4

x8

VDD

DQ0

VDDQ

N.C

VDD

N.C

1

VSS

N.C

VSSQ

N.C

DQ3

VDDQ

N.C

VSSQ

N.C

DQ2

VDDQ

N.C

VSS

CKE1

DQM

CLK

CKE0

A12

A11

A9

VSS

DQ7

VSSQ

N.C

DQ6

VDDQ

N.C

DQ5

VSSQ

N.C

DQ4

VDDQ

N.C

VSS

CKE1

DQM

CLK

CKE0

A12

A11

A9

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

2

VDDQ

N.C

3

4

DQ1

VSSQ

N.C

DQ0

VSSQ

N.C

5

6

7

DQ2

VDDQ

N.C

8

VDDQ

N.C

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ3

VSSQ

N.C

DQ1

VSSQ

N.C

VDD

CS1

WE

CS1

WE

CAS

RAS

CS0

BA0

BA1

CAS

RAS

CS0

BA0

BA1

A10/AP A10/AP

A8

A0

A1

A0

A1

A7

A6

A2

A5

54Pin TSOP

(400mil x 875mil)

(0.8 mm Pin pitch)

A3

A4

VDD

VSS

7.0 Pin Function Description

Name

System clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CS0~1

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE0~1

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12,

Column address : (x4 : CA0 ~ CA9,CA11,CA12), (x8 : CA0 ~ CA9,CA11), (x16 : CA0 ~ CA9)

A0 ~ A12

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

BA0 ~ BA1

RAS

Bank select address

Row address strobe

Column address strobe

Write enable

CAS

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM

Data input/output mask

Data inputs/outputs are multiplexed on the same pins.

(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)

DQ0 ~ N

Data input/output

VDD/VSS

VDDQ/VSSQ

Power supply/ground

Data output power/ground

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

No connection

/reserved for future use

N.C/RFU

This pin is recommended to be left No Connection on the device.

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

8.0 Absolute Maximum Ratings

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

1

Unit

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

9.0 DC Operating Conditions

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

3.3

3.0

0

-

Max

3.6

VDD+0.3

0.8

Unit

V

Note

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

1

2

VIL

VOH

VOL

ILI

-

IOH = -2mA

IOL = 2mA

3

0.4

10

V

uA

-10

-

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Notes :

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

10.0 Capacitance

Symbol

CCLK

CIN

Min

5

Max

9

10

14

Unit

pF

Clock

RAS, CAS, WE, CS, CKE, DQM

Address

(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)

CADD

COUT

5

pF

8

pF

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

11.0 DC Characteristics (x4)

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

Parameter

Symbol

Test Condition

Unit

mA

Note

75

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

115

1

ICC2P CKE ≤ VIL(max), tCC = 10ns

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

4

Precharge standby current in

power-down mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

40

20

Input signals are changed one time during 20ns

Precharge standby current in

non power-down mode

mA

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

ICC2NS

ICC3P CKE ≤ VIL(max), tCC = 10ns

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

12

Active standby current in

power-down mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

60

50

mA

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

IO = 0 mA

Page burst

ICC3NS

Operating current

(Burst mode)

ICC4

120

1

Refresh current

ICC5

ICC6

tRC ≥ tRC(min)

230

12

6

mA

2

3

4

C

L

Self refresh current

CKE ≤ 0.2V

Notes : 1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S1G0632D-UC

4. K4S1G0632D-UL

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

12.0 DC Characteristics (x8)

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

Parameter

Symbol

Test Condition

Unit

mA

Note

75

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

120

1

ICC2P CKE ≤ VIL(max), tCC = 10ns

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

4

Precharge standby current in

power-down mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

40

20

Input signals are changed one time during 20ns

Precharge standby current in

non power-down mode

mA

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

ICC2NS

ICC3P CKE ≤ VIL(max), tCC = 10ns

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

12

Active standby current in

power-down mode

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

60

50

mA

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

IO = 0 mA

Page burst

ICC3NS

Operating current

(Burst mode)

ICC4

130

1

Refresh current

ICC5

ICC6

tRC ≥ tRC(min)

230

12

6

mA

2

3

4

C

L

Self refresh current

CKE ≤ 0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S1G0732D-UC

4. K4S1G0732D-UL

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

13.0 AC Operating Test Conditions

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

Unit

V

ns

V

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50Ω

50pF

870Ω

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

(AC operating conditions unless otherwise noted)

14.0 Operating AC Parameter

Version

Parameter

Symbol

Unit

Note

75

Row active to row active delay

RAS to CAS delay

Row precharge time

tRRD(min)

tRCD(min)

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

15

20

45

100

65

2

ns

us

ns

CLK

ns

CLK

1

Row active time

Row cycle time

1

2, 5

5

2

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

2 CLK + tRP

1

Col. address to col. address delay

tCCD(min)

CAS latency = 3

CAS latency = 2

1

2

1

CLK

3

Number of valid output data

ea

4

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

15.0 AC Characteristics

(AC operating conditions unless otherwise noted)

75

Parameter

Symbol

Unit

ns

Note

1

Min

7.5

10

Max

CAS latency=3

CLK cycle time

tCC

1000

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

5.4

6

CLK to valid

output delay

tSAC

ns

1, 2

2

3

Output data

hold time

tOH

ns

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

tCH

tCL

2.5

1.5

0.8

1

ns

3

2

tSS

tSH

tSLZ

CAS latency=3

CAS latency=2

5.4

6

CLK to output

in Hi-Z

tSHZ

ns

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

16.0 DQ Buffer Output Drive Characteristics

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

Measure in linear

region : 1.2V ~ 1.8V

Output rise time

trh

1.37

4.37

Volts/ns

3

Measure in linear

Output fall time

Output rise time

Output fall time

tfh

trh

tfh

1.30

2.8

3.8

5.6

5.0

Volts/ns

3

region : 1.2V ~ 1.8V

Measure in linear

region : 1.2V ~ 1.8V

3.9

2.9

1,2

Measure in linear

region : 1.2V ~ 1.8V

2.0

Notes :

1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to VSS.

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

17.0 IBIS Specification

IOH Characteristics (Pull-up)

66MHz and 100/133MHz Pull-up

0.5 1.5 2.5

0

1

2

3

3.5

0

-100

-200

-300

-400

-500

-600

100MHz

133MHz

Min

100MHz

133Mhz

Max

66MHz

Min

Voltage

(V)

3.45

3.3

3.0

2.6

2.4

2.0

1.8

1.65

1.5

1.4

1.0

0.0

I (mA)

-2.4

I (mA)

-27.3

-74.1

0.0

-21.1

-34.1

-58.7

-67.3

-73.0

-77.9

-80.8

-88.6

-93.0

-0.7

-7.5

-129.2

-153.3

-197.0

-226.2

-248.0

-269.7

-284.3

-344.5

-502.4

-13.3

-27.5

-35.5

-41.1

-47.9

-52.4

-72.5

-93.0

Voltage

I

OH Min (100/133MHz)

OH Min (66MHz)

OH Max (66 and 100/133MHz)

66MHz and 100MHz Pull-down

IOL Characteristics (Pull-down)

250

200

150

100

50

100MHz

133MHz

Min

100MHz

133MHz

Max

66MHz

Min

Voltage

(V)

I (mA)

0.0

I (mA)

0.0

I (mA)

0.0

0.4

27.5

70.2

17.7

26.9

33.3

37.6

46.6

48.0

49.5

50.7

51.5

54.2

54.9

0.65

0.85

1.0

41.8

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

51.6

58.0

1.4

70.7

1.5

72.9

1.65

1.8

75.4

77.0

1.95

3.0

77.6

80.3

0

3.45

81.4

0

0.5

1

1.5

2

2.5

3

3.5

Voltage

IOL Min (100MHz)

IOL Min (66MHz)

IOL Max (100MHz)

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

Minimum VDD clamp current

(Referenced to VDD)

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V)

0.0

0.2

0.4

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

I (mA)

0.0

20

15

10

5

0.0

0.23

1.34

3.02

5.06

7.35

9.83

12.48

15.30

18.31

0

1

2

3

Voltage

I (mA)

Minimum VSS clamp current

-2 -1

VSS Clamp @ CLK, CKE, CS, DQM & DQ

-3

0

VSS (V)

-2.6

-2.4

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.9

-0.8

-0.7

-0.6

-0.4

-0.2

0.0

I (mA)

-57.23

-45.77

-38.26

-31.22

-24.58

-18.37

-12.56

-7.57

-3.37

-1.75

-0.58

-0.05

0.0

0

-10

-20

-30

-40

-50

-60

0.0

Voltage

I (mA)

Rev. 1.0 November. 2005

SDRAM stacked 1Gb D-die (x4, x8)

SDRAM

18.0 Simplified Truth Table

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

A0 ~ A9

Note

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP

A11, A12

Register

Refresh

Mode register set

Auto refresh

H

X

H

L

X

OP code

X

1,2

3

H

Entry

Exit

Self

refresh

L

H

L

H

X

L

H

X

H

X

H

L

H

X

Bank active & row addr.

Read &

column address

V

Row address

L

H

L

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4

4,5

4

4,5

6

Column

L

H

L

H

address

Write &

column address

Column

address

H

X

L

H

L

H

L

X

V

H

Burst stop

Precharge

X

Bank selection

All banks

V

X

L

H

X

H

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

X

Clock suspend or

active power down

X

Entry

H

Precharge power down mode

H

L

Exit

L

H

X

V

X

DQM

X

7

H

L

X

H

X

H

No operation command

Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.0 November. 2005


型号：	K4S1G0732D-UC75
厂家：	SAMSUNG
描述：	Cache DRAM Module, 128MX8, 5.4ns, CMOS, PDSO54 时钟动态存储器光电二极管内存集成电路
文件：	总14页 (文件大小：359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4S1G0732D-UC75 [SAMSUNG]

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