K4R441869B-N(M)CK7 [SAMSUNG]
256K x 16/18 bit x 32s banks Direct RDRAMTM; 256K X 16/18位x 32S银行直接RDRAMTM
| 型号： | K4R441869B-N(M)CK7 |
| 厂家： | 
SAMSUNG |
| 描述： | 256K x 16/18 bit x 32s banks Direct RDRAMTM |
| 文件： | 总20页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
K4R271669B/K4R441869B
Direct RDRAM
128/144Mbit RDRAM(B-die)
256K x 16/18 bit x 32s banks
Direct RDRAMTM
Version 1.11
October 2000
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Change History
Direct RDRAM
Version 1.11 ( October 2000) - Preliminary
* Based on the Rambus 1.11ver. 128/144Mbit(32s banks) RDRAM Datasheet.
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
SAMSUNG 050
SAMSUNG 050
K4Rxxxx69B-Nxxx
K4Rxxxx69B-Mxxx
The 128/144-Mbit Direct Rambus DRAMs (RDRAMâ ) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
M
a. Normal Package
b. Mirrored Package
Figure 1: Direct RDRAM CSP Package
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
The 128/144-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Speed
Organization
Part Number
I/O
Freq.
MHz
t
(Row
RAC
Access
Time) ns
Bin
Features
a
b
c
256Kx16x32s
-CK8
-CK7
-CG6
-CK8
-CK7
-CG6
800
711
600
800
711
600
45
45
K4R271669B-N (M)C K8
K4R271669B-N(M)CK7
K4R271669B-N(M)CG6
K4R441869B-N(M)CK8
K4R441869B-N(M)CK7
K4R441869B-N(M)CG6
¨ Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
53.3
45
a
256Kx18x32s
45
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
53.3
a.“32s” - 32 banks which use a “split” bank architecture.
b.“N” - normal package, “M” - mirrored package.
c.“C” - RDRAM core uses normal power self refresh.
¨ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
¨ Advanced power management:
- Direct RDRAM operates from a 2.5 volt supply
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
¨ Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
¨ Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Page 1
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Pinouts and Definitions
Center-Bonded Devices
and bottom table is for the mirrored package. The mechan-
ical dimensions of this package are shown in a later section.
Refer to Section "Center-Bonded uBGA Package" on page
18.
These tables shows the pin assignments of the center-bonded
RDRAM package. The top table is for the normal package,
b. Top marking example of normal package
Table 1-1: a. Center-Bonded Device (top view for normal package)
GND
VDD
VDD
GND
12
11
10
9
SAMSUNG 050
K4Rxxxx69B-Nxxx
DQA7
GND
CMD
DQA4
VDD
CFM
GND
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB4
VDD
DQB7
GND
SIO1
DQA5
DQA2
DQB1
DQB5
8
7
6
For normal package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and the A1
SCK
DQA6
GND
DQA1
VDD
VREF
GND
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
SIO0
5
position is marked by the marker “ “.
·
VCMOS
DQA8*
VCMOS
DQB8*
4
DQA3
DQA0
CTMN
DQB3
3
Top View
2
GND
VDD
VDD
GND
1
ROW
A
B
C
D
E
F
G
H
J
COL
Chip
Table 1-2: a. Center-Bonded Device (top view for mirrored package)
GND
VDD
VDD
GND
12
11
10
9
* DQA8/DQB8 are just used for 144Mb RDRAM.
These two pins are NC(No Connection) in 128Mb
RDRAM.
DQA8*
VCMOS
SCK
DQA3
GND
DQA0
VDD
CTMN
GND
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB3
GND
DQB8*
VCMOS
SIO0
b. Top marking example of mirrored package
DQA6
DQA1
VREF
DQB2
DQB6
8
7
SAMSUNG 050
6
K4Rxxxx69B-Mxxx
CMD
GND
DQA5
VDD
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB5
VDD
SIO1
GND
5
4
DQA7
DQA4
DQB0
DQB4
DQB7
M
3
2
GND
VDD
VDD
GND
1
For mirrored package, pin #1(ROW 1, COL A) is
located at the A1 postion on the top side and the A1
position is marked by the alphabet “M“.
A
B
C
D
E
F
G
H
J
ROW
COL
Page 2
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Table 2: Pin Description
Description
# of
Pins
Signal
I/O
Type
a
a
SIO1,SIO0
I/O
CMOS
2
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
CMD
SCK
I
I
CMOS
CMOS
1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
a
Serial clock input. Clock source used for reading from and writing to the
control registers
V
V
V
10
1
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
DD
DDa
CMOS
2
GND
13
1
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
GNDa
b
DQA8..DQA0
I/O
RSL
9
Data byte A. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQA8 is not used (no connection) by
RDRAMs with a x16 organization.
b
CFM
I
I
RSL
1
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
b
CFMN
RSL
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
V
1
1
Logic threshold reference voltage for RSL signals
REF
b
CTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
b
CTM
I
RSL
1
3
5
9
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
b
RQ7..RQ5 or
ROW2..ROW0
I
RSL
Row access control. Three pins containing control and address informa-
tion for row accesses.
b
RQ4..RQ0 or
COL4..COL0
I
RSL
Column access control. Five pins containing control and address informa-
tion for column accesses.
b
DQB8..
DQB0
I/O
RSL
Data byte B. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQB8 is not used (no connection) by
RDRAMs with a x16 organization.
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
RQ7..RQ5 or
ROW2..ROW0
3
RQ4..RQ0 or
DQB8..DQB0
9
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
COL4..COL0
5
DQA8..DQA0
9
2
2
RCLK
RCLK
1:8 Demux
1:8 Demux
TCLK
RCLK
6
Control Registers
Packet Decode
Packet Decode
COLC
ROWR
11
ROWA
9
COLX
5
COLM
5
5
5
5
5
5
6
8
8
ROP DR BR
AV
R
REFR
DEVID
XOP DX BX COP DC BC
C
MB MA
Power Modes
M
S
Match
DM
Mux
Match
Match
Write
Buffer
Row Decode
XOP Decode
PRER
ACT
PREX
Mux
Column Decode & Mask
PREC RD, WR
Mux
DRAM Core
Sense Amp
32x72
512x64x144
32x72
32x72
72
Internal DQB Data Path
Internal DQA Data Path
72
72
Bank 0
Bank 1
Bank 2
72
9
9
9
9
Bank 13
Bank 14
Bank 15
9
9
Bank 16
Bank 17
Bank 18
9
9
9
9
Bank 29
Bank 30
Bank 31
Figure 2: 128/144 Mbit(256K x16/18 x32s) Direct RDRAM Block Diagram
Page 4
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
General Description
Figure 2 is a block diagram of the 128/144Mbit Direct
RDRAM. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 1.6GB/s.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM on the Channel.
ACT Command: An ACT (activate) command from an
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
RD Command: The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks: The 16Mbyte core of the RDRAM is divided into
thirty two 0.5Mbyte banks, each organized as 512 rows, with
each row containing 64 dualocts, and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps: The RDRAM contains 34 sense amps. Each
sense amp consists of 512 bytes of fast storage (256 for DQA
and 256 for DQB) and can hold one-half of one row of one
bank of the RDRAM. The sense amp may hold any of the
512 half-rows of an associated bank. However, each sense
amp is shared between two adjacent banks of the RDRAM
(except for sense amps 0, 15, 16, and 31). This introduces the
restriction that adjacent banks may not be simultaneously
accessed.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that a
precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
RQ Pins: These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
Page 5
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to specify
a nine bit row address, and the ROWR packet uses the
remaining bits for an eleven bit opcode field. Note the use of
the “RsvX” notation to reserve bits for future address field
extension.
Packet Format
Figure 3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table 3 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.
Table 3: Field Description for ROWA Packet and ROWR Packet
Description
Field
DR4T,DR4F
DR3..DR0
BR4..BR0
AV
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
Device address for ROWA or ROWR packet.
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R8..R0
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
ROP10..ROP0
Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table 4 describes the fields
which comprise these packets.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from at least t
RTR
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
earlier. An COLX packet may be used to specify an indepen-
dent precharge command. It contains a five bit device
address, a five bit bank address, and a five bit opcode. The
COLX packet may also be used to specify some house-
keeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
The 23 bit COLC packet has a five bit device address, a five
bit bank address, a six bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet
Description
Field
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
Device address for COLC packet.
DC4..DC0
BC4..BC0
C5..C0
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
Selects between COLM packet (M=1) and COLX packet (M=0).
COP3..COP0
M
MA7..MA0
MB7..MB0
DX4..DX0
BX4..BX0
XOP4..XOP0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.
Device address for COLX packet.
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
Opcode field for COLX packet. Specifies precharge, I control, and power management functions.
OL
Page 6
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
T
T
T
T
T
T
T
T
11
0
1
2
3
8
9
10
CTM/CFM
CTM/CFM
DR2 BR0 BR3 RsvR R8
DR1 BR1 BR4 RsvR R7
DR0 BR2 RsvB AV=1 R6
R5
R4
R3
R2
R1
R0
DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2
DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1
DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
ROW2 DR4T
ROW1
ROW0 DR3
ROW2 DR4T
ROW1
ROW0 DR3
DR4F
DR4F
ROWA Packet
ROWR Packet
T
T
T
2
T
3
T
T
T
T
T
T
T
T
T
T
T T T T T T
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
0
1
CTM/CFM
CTM/CFM
ROW2
..ROW0
DC4 S=1
DC3
RsvC C4
ACT a0
WR b1
PRER c0
COL4
COL3
COL2
COL1
COL0
t
PACKET
C5
C3
COL4
..COL0
MSK (b1) PREX d0
COP1
COP0
COP2
RsvB BC2 C2
BC4 BC1 C1
DC2
DC1
DC0
DQA8..0
DQB8..0
COP3 BC3 BC0 C0
COLC Packet
T
T
T
T
T
T
T
T
15
8
9
10
11
12
13
14
CTM/CFM
CTM/CFM
a
b
S=1 MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
S=1 DX4 XOP4 RsvB BX1
M=0 DX3 XOP3 BX4 BX0
DX2 XOP2 BX3
COL4
COL3
COL2
COL1
COL4
COL3
COL2
COL1
COL0
MB6 MB3 MB0
DX1 XOP1 BX2
COL0
MB5 MB2
DX0 XOP0
a
b
The COLM is associated with a
previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.
The COLX is aligned
with the present COLC,
indicated by the Start
bit (S=1) position.
COLM Packet
COLX Packet
Figure 3: Packet Formats
Page 7
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
broadcast operation is indicated when both bits are set.
Field Encoding Summary
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.
Table 5 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a
Table 5: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T
DR4F
Device Selection
Device Match signal (DM)
1
0
1
0
1
1
0
0
All devices (broadcast)
One device selected
One device selected
No packet present
DM is set to 1
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0
DM is set to 0
Table 6 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.
row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in “Power State Manage-
ment” on page 50. The TCEN and TCAL commands are
used to adjust the output driver slew rate and they are
described in more detail in “Current and Temperature
Control” on page 56.
An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-acti-
vate) command is similar to the ACT command, except the
Table 6: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field
Command Description
a
DM
AV
Name
10
9
8
7
6
5
4
3
2:0
0
1
1
1
-
-
-
-
-
-
-
-
-
---
-
No operation.
b
1
0
0
Row address
ACT
Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTN .
Precharge bank BR4..BR0 of this device.
c
1
0
1
0
0
0
0
1
0
1
x
0
x
0
x
x
000 PRER
000 REFA
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.
Increment REFR if BR4..BR0 = 11111 (see Figure 51).
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
0
0
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
1
1
x
x
0
0
0
0
1
0
1
x
x
0
0
0
x
x
x
x
0
1
x
x
0
000 REFP
000 PDNR
000 NAPR
Precharge bank BR4..BR0 of this device after REFA (see Figure 51).
Move this device into the powerdown (PDN) power state (see Figure 48).
Move this device into the nap (NAP) power state (see Figure 48).
000 NAPRC Move this device into the nap (NAP) power state conditionally
b
000 ATTN
000 RLXR
001 TCAL
010 TCEN
Move this device into the attention (ATTN) power state (see Figure 46).
Move this device into the standby (STBY) power state (see Figure 47).
Temperature calibrate this device (see Figure 54).
Temperature calibrate/enable this device (see Figure 54).
000 NOROP No operation.
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
Page 8
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Table 7 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 18 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transi-
tion. See “Power State Management” on page 50.
Table 7: COLC Packet Field Encodings
S
DC4.. DC0
(select device)
COP3..0 Name
Command Description
a
0
1
1
1
1
1
1
1
1
1
1
----
-----
-
-
No operation.
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-----
Retire write buffer of this device.
b
x000
x001
x010
x011
x100
x101
x110
x111
1xxx
NOCOP Retire write buffer of this device.
WR
Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer.
RSRV
RD
Reserved, no operation.
Read column C5..C0 of bank BC4..BC0 of this device.
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15).
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
Reserved, no operation.
PREC
WRA
RSRV
RDA
RLXC
Same as RD, but precharge bank BC4..BC0 afterward.
Move this device into the standby (STBY) power state (see Figure 47).
a. “/=” means not equal, “==” means equal.
b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).
Table 8 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see “Current and
Temperature Control” on page 56), and for the RLXX power
mode command (see “Power State Management” on page
50).
Table 8: COLM Packet and COLX Packet Field Encodings
DX4 .. DX0
(selects device)
M
XOP4..0
Name
Command Description
1
0
0
0
0
0
0
0
----
-
MSK
MB/MA bytemasks used by WR/WRA.
No operation.
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-
-
00000
NOXOP
PREX
CAL
No operation.
a
1xxx0
Precharge bank BX4..BX0 of this device (see Figure 15).
x10x0
x11x0
xxx10
xxxx1
Calibrate (drive) I current for this device (see Figure 53).
OL
CAL/SAM
RLXX
RSRV
Calibrate (drive) and Sample ( update) I current for this device (see Figure 53).
OL
Move this device into the standby (STBY) power state (see Figure 47).
Reserved, no operation.
a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Electrical Conditions
Table 9: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
T
Junction temperature under bias
Supply voltage
-
100
2.50 + 0.13
2.0
°C
V
J
V
V
V
2.50 - 0.13
DD, DDA
V
Supply voltage droop (DC) during NAP interval (t
Supply voltage ripple (AC) during NAP interval (t
)
NLIMIT
-
%
%
DD,N, DDA,N
v
v
)
NLIMIT
-2.0
2.0
DD,N, DDA,N
a
V
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
V
V
DD
1.80 + 0.2
V
V
CMOS
DD
1.80 - 0.1
V
V
V
Reference voltage
1.40 - 0.2
1.40 + 0.2
V
V
V
-
REF
DIL
DIH
DA
RSL data input - low voltage
V
- 0.5
V
- 0.2
REF
REF
b
RSL data input - high voltage
V
+ 0.2
V
+ 0.5
REF
REF
R
RSL data asymmetry: R = (V
- V ) / (V
- V )
DIL
0.67
1.00
DA
DIH
REF
REF
V
V
V
V
V
RSL clock input - common mode V = (V +V /2
CIL)
1.3
0.35
1.8
V
V
V
V
V
CM
CM
CIH
RSL clock input swing: V = V
- V
(CTM,CTMN pins).
(CFM,CFMN pins).
1.00
1.00
CIS,CTM
CIS,CFM
IL,CMOS
IH,CMOS
CIS
CIH
CIH
CIL
CIL
RSL clock input swing: V = V
CIS
- V
0.225
c
CMOS input low voltage
CMOS input high voltage
- 0.3
V
/2 - 0.25
d
CMOS
V
/2 + 0.25
V
+0.3
CMOS
CMOS
a. V
b. V
must remain on as long as V is applied and cannot be turned off.
DD
CMOS
is typically equal to V
(1.8V±0.1V) under DC conditions in a system.
TERM
DIH
c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.
d. Voltage overshoot is limited toV +0.7V for a duration of less than 5ns
CMOS
Page 10
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Electrical Characteristics
Table 10: Electrical Characteristics
Symbol
Parameter and Conditions
Junction-to-Case thermal resistance
current @ V
Min
Max
Unit
Q
-
-10
-10
30.0
-
0.5
10
°C/Watt
mA
mA
mA
mA
W
JC
REF
OH
I
I
I
V
REF
REF,MAX
RSL output high current @ (0£V
£V
)
10
OUT
DD
a
RSL I current @ V = 0.9V, V
, T
J,MAX
90.0
2.0
-
ALL
OL
OL
DD,MIN
DI
RSL I current resolution step
OL
OL
OUT
OL
r
I
I
Dynamic output impedance @ V = 0.9V
OL
150
26.6
-10.0
-
b,c
RSL I current @ V = 1.0V
30.6
10.0
0.3
-
mA
mA
V
OL
OL
CMOS input leakage current @ (0£V
£V
)
I,CMOS
I,CMOS
CMOS
V
V
CMOS output voltage @ I
= 1.0mA
OL,CMOS
OH,CMOS
OL,CMOS
CMOS output high voltage @ I
= -0.25mA
V
-0.3
V
OH,CMOS
CMOS
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and
CCB are initialized to a value of 64. This value applies to all DQA and DQB pins.
c. This measurement is made in automatic current control mode in a 25W test system with V
= 1.714V and V = 1.357V and with the ASYMA
REF
TERM
and ASYMB register fields set to 0.
Page 11
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Timing Conditions
Table 11: Timing Conditions
Min
Symbol
Parameter
Max
Unit
Figure(s)
t
CTM and CFM cycle times (-800)
CTM and CFM cycle times (-711)
CTM and CFM cycle times (-600)
2.50
2.80
3.33
0.2
3.83
3.83
3.83
0.5
ns
Figure 55
CYCLE
t
, t
CTM and CFM input rise and fall times. Use the minimum value
of these parameters during testing.
ns
Figure 55
Figure 55
CR CF
t
t
, t
CTM and CFM high and low times
40%
60%
t
t
CH CL
CYCLE
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
0.0
0.9
1.0
1.0
Figure 43
Figure 55
TR
CYCLE
t
t
Domain crossing window
-0.1
0.2
0.1
t
Figure 61
Figure 56
DCW
CYCLE
, t
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use
the minimum value of these parameters during testing.
0.65
ns
DR DF
b
t , t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
=2.50ns
=2.81ns
=3.33ns
0.200
0.240
0.275
-
-
-
ns
Figure 56
S
H
CYCLE
CYCLE
CYCLE
c,d
b,d
t
t
t
t
SIO0, SIO1 input rise and fall times
CMD, SCK input rise and fall times
-
-
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 58
Figure 58
Figure 58
Figure 58
Figure 58
Figure 58
Figure 58
Figure 58
Figure 58
Figure 49
Figure 59
Figure 49
Figure 49
Figure 48
Figure 53
Figure 53
Figure 49
Figure 48
Figure 47
Figure 46
DR1, DF1
t
2.0
DR2, DF2
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions
SCK high and low times
1000
10
4.25
1.25
1
-
CYCLE1
-
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
, t
-
CH1 CL1
e
CMD setup time to SCK rising or falling edge
-
S1
e
CMD hold time to SCK rising or falling edge
-
H1
SIO0 setup time to SCK falling edge
40
40
0
-
S2
SIO0 hold time to SCK falling edge
-
H2
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
-
S3
5.5
-1
-
H3
-
t
t
t
t
t
t
t
t
S4
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
f
ROW2..0, COL4..0 hold time for quiet window
5
-
H4
Quiet on ROW/COL bits during NAP/PDN entry
4
-
NPQ
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
12
8
-
READTOCC
CCSAMTOREAD
CE
-
2
-
CTM/CFM stable after NAP/PDN entry
100
7
-
-
CD
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
FRM
CYCLE
10.0
ms
NLIMIT
Page 12
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Table 11: Timing Conditions
Min
Symbol
Parameter
Max
Unit
Figure(s)
t
t
Refresh interval
32
ms
Figure 51
Figure 52
REF
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM must be refreshed at least once.
200
ms
BURST
t
t
t
t
t
t
Current control interval
34 t
100ms
ms/t
CYCLE
Figure 53
Figure 54
Figure 54
Figure 54
Figure 54
CCTRL
TEMP
CYCLE
Temperature control interval
100
ms
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
150
2
-
t
t
t
TCEN
CYCLE
CYCLE
2
-
TCAL
140
TCQUIET
PAUSE
CYCLE
RDRAM delay (no RSL operations allowed)
200.0
ms
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t =3.33ns.
CYCLE
c. t
and t
for other t
values can be interpolated between or extrapolated from the timings at the 3 specified t
values.
S,MIN
H,MIN
CYCLE
CYCLE
d. This parameter also applies to a -800 part when operated with t
=2.81ns.
CYCLE
e. With V
=0.5V
-0.4V and V
=0.5V
+0.4V
IL,CMOS
CMOS
IH,CMOS
CMOS
f. Effective hold becomes t ’=t +[PDNXA•64•t
+t
]-[PDNX•256•t
]
SCYCLE
H4 H4
SCYCLE PDNXB,MAX
if [PDNX•256•t
] < [PDNXA•64•t
+t
]. See Figure 49.
SCYCLE
SCYCLE PDNXB,MAX
Page 13
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Timing Characteristics
Table 12: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
a
a
t
CTM-to-DQA/DQB output time @ t
CTM-to-DQA/DQB output time @ t
CTM-to-DQA/DQB output time @ t
DQA/DQB output rise and fall times
=2.50ns
=2.81ns
=3.33ns
-0.260
+0.260
ns
Figure 57
Q
CYCLE
CYCLE
CYCLE
a,b
a,b
-0.300
+0.300
a,c
a,c
0.350
+0.350
t
t
t
t
t
t
t
t
t
t
t
t
t
, t
0.2
-
0.45
10
-
ns
ns
ns
ns
ns
ns
ns
ms
Figure 57
Figure 60
Figure 60
Figure 60
Figure 60
Figure 49
Figure 49
Figure 49
Figure 49
Figure 47
Figure 47
Figure 48
Figure 48
QR QF
SCK(neg)-to-SIO0 delay @ C
SCK(pos)-to-SIO0 delay @ C
= 20pF (SD read data valid).
= 20pF (SD read data hold).
Q1
LOAD,MAX
LOAD,MAX
2
-
HR
, t
SIO
rise/fall @ C = 20pF
LOAD,MAX
5
QR1 QF1
OUT
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C
= 20pF
LOAD,MAX
-
10
50
40
4
PROP1
NAPXA
NAPXB
PDNXA
PDNXB
AS
NAP exit delay - phase A
-
NAP exit delay - phase B
-
PDN exit delay - phase A
-
PDN exit delay - phase B
-
9000
1
t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
ATTN-to-STBY power state delay
STBY-to-ATTN power state delay
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
-
-
0
SA
-
8
ASN
-
8
ASP
a. t
and t
for other t
values can be interpolated between or extrapolated from the timings at the 3 specified t
values.
Q,MIN
Q,MAX
CYCLE
CYCLE
b. This parameter also applies to a -800 part when operated with t
=2.81ns.
CYCLE
c. This parameter also applies to a -800 or -711 part when operated with t
=3.33ns.
CYCLE
Page 14
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Timing Parameters
Table 13: Timing Parameter Summary
Min
-45
Min Min
-45 -53.3 Max Units
Parameter
Description
Figure(s)
-800 -711 -600
t
t
Row Cycle time of RDRAM banks -the interval between ROWA packets with 28
ACT commands to the same bank.
28
28
-
t
t
Figure 16
Figure 17
RC
CYCLE
CYCLE
b
RAS-asserted time of RDRAM bank - the interval between ROWA packet
20
20
20
64ms
Figure 16
Figure 17
RAS
a
with ACT command and next ROWR packet with PRER command to the
same bank.
t
Row Precharge time of RDRAM banks - the interval between ROWR packet
8
8
8
-
t
Figure 16
Figure 17
RP
CYCLE
a
with PRER command and next ROWA packet with ACT command to the
same bank.
t
t
t
Precharge-to-precharge time of RDRAM device - the interval between succes-
8
8
9
8
8
7
8
8
7
-
-
-
t
t
t
Figure 13
Figure 14
PP
CYCLE
CYCLE
CYCLE
a
sive ROWR packets with PRER commands to any banks of the same device.
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
RR
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen
Figure 16
Figure 17
RCD
by the RDRAM core (t
) is equal to t
= 1 + t
because of differ-
RCD-C
RCD-C
RCD
ences in the row and column paths through the RDRAM interface.
t
CAS Access delay - the interval from RD command to Q read data. The equa-
8
8
8
12
t
Figure 5
CAC
CYCLE
tion for t
is given in the TPARM register in Figure 40.
Figure 40
CAC
t
t
CAS Write Delay (interval from WR command to D write data.
6
4
6
4
6
4
6
-
t
t
Figure 5
CWD
CC
CYCLE
CYCLE
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands).
Figure 16
Figure 17
t
t
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
8
4
8
4
8
4
-
t
t
Figure 3
PACKET
RTR
CYCLE
CYCLE
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
Figure 18
t
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
4
4
4
4
t
Figure 15
Figure 40
OFFP
CYCLE
the equivalent ROWR packet with PRER. The equation for t
the TPARM register in Figure 40.
is given in
OFFP
t
t
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
4
4
4
-
-
t
t
Figure 16
Figure 17
RDP
RTP
CYCLE
CYCLE
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
a. Or equivalent PREC or PREX command. See Figure 15.
b. This is a constraint imposed by the core, and is therefore in units of ms rather than t
.
CYCLE
Page 15
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Absolute Maximum Ratings
Table 14: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
V
V
Voltage applied to any RSL or CMOS pin with respect to Gnd
Voltage on VDD and VDDA with respect to Gnd
Storage temperature
- 0.3
- 0.5
- 50
V
V
+0.3
V
V
I,ABS
DD
DD
, V
+1.0
DD,ABS
STORE
DDA,ABS
T
100
°C
I
- Supply Current Profile
DD
Table 15: Supply Current Profile
Min
a
Max
-45
-800
Max
-45
-711
Max
-53.3
-600
Unit
I
value
RDRAM Power State and Steady-State Transaction Rates
DD
I
I
I
Device in PDN, self-refresh enabled and INIT.LSR=0.
-
-
-
5000
4
5000
4
5000
4
mA
mA
mA
DD,PDN
DD,NAP
DD,STBY
Device in NAP.
Device in STBY. This is the average for a device in STBY with (1) no
packets on the Channel, and (2) with packets sent to other devices.
105
100
90
I
I
Device in STBY and refreshing rows at the t
period.
-
-
105
165
100
155
90
mA
mA
DD,REFRESH
DD,ATTN
REF,MAX
Device in ATTN. This is the average for a device in ATTN with (1) no
packets on the Channel, and (2) with packets sent to other devices.
140
I
I
Device in ATTN. ACT command every 8•t
, PRE command
CYCLE
-
-
575/
625
525/
580
455/
500
mA
mA
DD,ATTN-W
DD,ATTN-R
b
every 8•t
, WR command every 4•t
, and data is 1100..1100
CYCLE
CYCLE
Device in ATTN. ACT command every 8•t
, PRE command
490/
520
450/
480
400/
420
CYCLE
c
every 8•t
, RD command every 4•t
, and data is 1111..1111
CYCLE
CYCLE
a. CMOS interface consumes power in all power states.
b. x16/x18 RDRAM data width.
c. This does not include the I sink current. The RDRAM dissipates I •V in each output driver when a logic one is driven.
OL
OL OL
Table 16: Supply Current at Initialization
Symbol
Parameter
Allowed Range of t
V
Min
Max
Unit
CYCLE
DD
a
I
I
I
I
from power -on to SETR
from SETR to CLRR
3.33ns to 3.83ns
2.50ns to 3.32ns
V
V
-
-
150
mA
DD,PWRUP,D
DD
DD,MIN
DD,MIN
b
200
b
3.33ns to 3.83ns
2.50ns to 3.32ns
250
mA
DD,SETR,D
DD
b
332
Page 16
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Parameter and Conditions - RSL pins
RSL effective input inductance
Symbol
Min
Max
4.0
0.2
0.6
1.8
2.4
2.4
2.6
0.1
0.06
Unit
nH
nH
nH
nH
pF
Figure
L
L
Figure 62
Figure 62
I
Mutual inductance between any DQA or DQB RSL signals.
Mutual inductance between any ROW or COL RSL signals.
12
DL
Difference in L value between any RSL pins of a single device.
I
-
Figure 62
Figure 62
I
a
C
RSL effective input capacitance
800
711
600
2.0
2.0
2.0
-
I
C
Mutual capacitance between any RSL signals.
pF
pF
Figure 62
Figure 62
12
DC
Difference in C value between average of {CTM, CTMN, CFM,
I
-
I
CFMN} and any RSL pins of a single device.
R
RSL effective input resistance
4
15
W
Figure 62
I
a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.
Table 18: CMOS Pin Parasitics
Symbol
Parameter and Conditions - CMOS pins
CMOS effective input inductance
CMOS effective input capacitance (SCK,CMD)
Min
Max
Unit
Figure
L
C
C
8.0
2.1
7.0
nH
pF
pF
Figure 62
I ,CMOS
a
1.7
-
I ,CMOS
a
CMOS effective input capacitance (SIO1, SIO0)
I ,CMOS,SIO
a. This value is a combination of the device IO circuitry and package capacitances.
Page 17
Version 1.11 Oct. 2000
™
K4R271669B/K4R441869B
Direct RDRAM
Center-Bonded uBGA Package
(62 Balls)
Figure 4 shows the form and dimensions of the recom-
mended package for the center-bonded CSP device class
D
Bottom
A
B
C
D
E
F
G
H
J
Bottom
Top
1
2
3
4
5
6
A
7
8
9
e2
10
11
12
e1
d
Bottom
E1
E
Figure 4: Center-Bonded uBGA Package
Table 19 lists the numerical values corresponding to dimen-
sions shown in Figure 4.
Table 19: Center-Bonded uBGA Package Dimensions
Symbol
Parameter
Min(128Mb/144Mb)
Max(128Mb/144Mb)
Unit
e1
e2
A
Ball pitch (x-axis)
Ball pitch (y-axis)
Package body length
Package body width
Package total thickness
Ball height
1.00
0.8
1.00
0.8
mm
mm
mm
mm
mm
mm
mm
11.90
10.10
-
12.10
10.30
D
a
E
1.00
E1
d
0.20
0.30
0.30
0.40
Ball diameter
a. The E,MAX parameter for SO-RIMM applications is 0.94mm.
Page 18
Version 1.11 Oct. 2000
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