K4M51323LC-DL750 [SAMSUNG]
Synchronous DRAM, 16MX32, 5.4ns, CMOS, PBGA90, LEAD FREE, FBGA-90;
| 型号： | K4M51323LC-DL750 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 16MX32, 5.4ns, CMOS, PBGA90, LEAD FREE, FBGA-90 时钟 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
GENERAL DESCRIPTION
• VDD/VDDQ = 2.5V/2.5V
The K4M51323LC is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA ( -SXXX -Pb, -DXXX -Pb Free).
ORDERING INFORMATION
Part No.
Max Freq.
Interface
Package
K4M51323LC-S(D)N/G/L/F75
133MHz(CL=3), 111MHz(CL=2)
133MHz(CL=3), 83MHz(CL=2)
90 FBGA Pb
(Pb Free)
LVCMOS
K4M51323LC-S(D)N/G/L/F7L*1
- S(D)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- S(D)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization
Bank
Row
A0 - A12
Column Address
16Mx32
BA0,BA1
A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
1
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
4M x 32
4M x 32
4M x 32
4M x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
2
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
Package Dimension and Pin Configuration
< Bottom View*1
>
< Top View*2
>
E1
90Ball(6x15) FBGA
9
8
7
6
5
4
3
2
1
1
2
3
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
DQ26 DQ24
DQ28
V
SS
V
DD
DQ23 DQ21
DQ19
V
DDQ
V
SSQ
V
DDQ
VSSQ
V
SSQ
SSQ
DQ27 DQ25 DQ22 DQ20
DQ29 DQ30 DQ17 DQ18
V
DDQ
DDQ
V
V
V
DDQ
SS
DQ31
DQM3
A5
NC
A3
NC
A2
DQ16
DQM2
A0
V
SSQ
DD
V
V
G
H
J
G
H
J
A4
A7
A6
A10
NC
A1
A11
A8
A12
A9
BA1
CS
CLK
DQM1
CKE
NC
BA0
CAS
RAS
DQM0
K
L
K
L
NC
WE
V
DDQ
DQ8
DQ10
V
SS
V
DD
DQ7
DQ5
DQ3
VSSQ
M
N
P
R
M
N
P
R
V
SSQ
SSQ
DQ9
DQ6
DQ1
VDDQ
DDQ
V
DQ12 DQ14
V
DQ11
V
DDQ
V
SSQ
SS
V
DDQ
DD
V
SSQ
DQ4
DQ2
DQ13 DQ15
V
V
DQ0
E
Pin Name
Pin Function
System Clock
Chip Select
Clock Enable
Address
CLK
CS
A
CKE
A1
A
0
~ A12
~ BA
z
b
BA
0
1
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
RAS
CAS
WE
< Top View*2
>
#A1 Ball Origin Indicator
DQM
0
~ DQM
3
Data Input/Output Mask
Data Input/Output
DQ
0
~ 31
V
DD/VSS
Power Supply/Ground
V
DDQ/VSSQ
Data Output Power/Ground
[Unit::mm]
Symbol
Min
Typ
-
Max
1.00
-
A
A1
E
-
0.25
-
10.9
11.0
6.40
13.0
11.2
0.80
0.50
-
11.1
-
E1
D
-
12.9
13.1
-
D1
e
-
-
0.45
-
-
b
0.55
0.10
z
3
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.0
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
V
IN, VOUT
V
DD, VDDQ
V
T
STG
°C
W
Power dissipation
P
D
Short circuit current
I
OS
50
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, T = -25 to 85°C for Extended, -25 to 70°C for Commercial)
A
Parameter
Symbol
Min
2.3
Typ
Max
2.7
Unit
V
Note
V
DD
DDQ
IH
2.5
1
Supply voltage
V
2.3
2.5
2.7
V
1
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
NOTES :
V
0.8 x VDDQ
-0.3
-
0
-
V
DDQ + 0.3
0.3
V
2
V
IL
V
3
V
OH
V
DDQ -0.2
-
V
I
OH = -0.1mA
V
OL
LI
-
-
0.2
V
I
OL = 0.1mA
4
I
-10
-
10
uA
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 2.5V, T = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
A
Pin
Symbol
Min
1.5
1.5
1.5
1.5
2.0
Max
3.5
3.0
3.0
3.0
4.5
Unit
Note
Clock
C
CLK
pF
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE
CIN
DQM
CIN
Address
C
ADD
OUT
DQ0 ~ DQ31
C
4
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
Unit
mA
mA
Note
-75
-7L
Burst length = 1
Operating Current
(One Bank Active)
I
CC1
110
110
1
t
I
RC ≥ tRC(min)
= 0 mA
O
I
CC2P CKE ≤ VIL(max), tCC = 10ns
1.0
1.0
Precharge Standby Current
in power-down mode
I
CC2PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
I
CC2N
15
5
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
I
CC2NS
I
CC3P CKE ≤ VIL(max), tCC = 10ns
8
8
Active Standby Current
in power-down mode
I
CC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
I
CC3N
30
20
mA
mA
Active Standby Current
in non power-down mode
(One Bank Active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
I
CC3NS
IO = 0 mA
Operating Current
(Burst Mode)
Page burst
4Banks Activated
I
I
CC
4
5
150
180
105
180
mA
1
2
3
t
CCD = 2CLKs
Refresh Current
CC
t
RC ≥ tRC(min)
mA
uA
°C
-N/L
800
45 *4
85/70
Internal TCSR
Full Array
Self Refresh Current
I
CC6
CKE ≤ 0.2V
500
800
-G/F
uA
1/2 of Full Array
1/4 of Full Array
450
425
700
625
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C
4. It has +/-5 °C tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
5
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
AC OPERATING TEST CONDITIONS(VDD = 2.5V ± 0.2V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Value
0.9 x VDDQ / 0.2
Unit
V
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
0.5 x VDDQ
tr/tf = 1/1
V
ns
V
Output timing measurement reference level
Output load condition
0.5 x VDDQ
See Figure 2
VDDQ
500Ω
Vtt=0.5 x VDDQ
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
VOL (DC) = 0.2V, IOL = 0.1mA
30pF
Output
50Ω
500Ω
Output
Z0=50Ω
30pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
6
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-75
15
18
18
45
-7L
15
Row active to row active delay
RAS to CAS delay
t
t
RRD(min)
RCD(min)
ns
ns
1
1
1
1
22.5
22.5
45
Row precharge time
t
RP(min)
RAS(min)
RAS(max)
RC(min)
RDL(min)
DAL(min)
CDL(min)
BDL(min)
CCD(min)
ns
t
ns
Row active time
t
100
us
Row cycle time
t
63
67.5
ns
1,6
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
t
2
CLK
-
t
tRDL + tRP
3
t
1
1
1
2
1
CLK
CLK
CLK
2
t
2
Col. address to col. address delay
t
4
Number of valid output data
Number of valid output data
Number of valid output data
CAS latency=3
CAS latency=2
CAS latency=1
ea
5
-
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
6. Maximum burst refresh cycle : 8
7
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
- 75
-7L
Parameter
Symbol
Unit
Note
Min
7.5
9.0
-
Max
Min
7.5
12
Max
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
t
t
t
CC
CC
CC
CLK cycle time
1000
1000
ns
1
25
t
t
t
SAC
SAC
SAC
5.4
7
5.4
8
CLK to valid output delay
Output data hold time
ns
ns
1,2
2
-
20
t
OH
OH
OH
2.5
2.5
-
2.5
2.5
2.5
2.5
2.5
2.0
1.0
1
t
t
CLK high pulse width
CLK low pulse width
Input setup time
t
CH
CL
SS
SH
SLZ
2.5
2.5
2.0
1.0
1
ns
ns
ns
ns
ns
3
3
3
3
2
t
t
Input hold time
t
CLK to output in Low-Z
t
CAS latency=3
CAS latency=2
CAS latency=1
5.4
7
5.4
8
CLK to output in Hi-Z
t
SHZ
ns
-
20
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
8
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
A12, A11
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
A9 ~ A0
Register
Refresh
Mode Register Set
Auto Refresh
H
H
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE
X
1, 2
3
H
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
X
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
L
Column
4
L
H
L
H
Address
(A0~A8)
H
4, 5
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
L
Column
Address
(A0~A8)
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4, 5
Burst Stop
Precharge
X
6
Bank Selection
All Banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
Exit
X
H
L
Entry
H
Precharge Power Down
Mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
H
X
H
No Operation Command
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
9
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
A9*2
BA0 ~ BA1
Address
A12 ~ A10/AP
A8
A7
A6
A5
A4
A3
A2
A1
A0
"0" Setting for
Normal MRS
RFU*1
Function
W.B.L
Test Mode
CAS Latency
BT
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Type
Burst Length
A8 A7
Type
Mode Register Set
Reserved
A6 A5 A4
Latency
Reserved
1
A3
0
A2
A1
0
A0
0
BT=0
BT=1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
1
2
4
8
1
2
4
8
1
0
1
Reserved
2
Mode Select
1
0
Reserved
3
BA1 BA0
Mode
1
1
Write Burst Length
Length
Reserved
Reserved
Reserved
Reserved
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Setting
for Nor-
mal MRS
A9
0
0
1
0
0
Burst
1
0
Full Page*3
Reserved
1
Single Bit
1
1
Register Programmed with Extended MRS
Address
BA1
BA0
A12 ~ A10/AP
A9
RFU*1
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU*1
Function
Mode Select
DS
PASR
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Mode
Driver Strength
PASR
BA1
BA0
A6 A5 Driver Strength
A2
0
A1
0
A0
Size of Refreshed Array
Full Array
0
0
1
1
0
1
0
1
Normal MRS
Reserved
0
0
1
1
0
1
0
1
Full
1/2
0
1
0
1
0
1
0
1
0
0
1/2 of Full Array
1/4 of Full Array
Reserved
EMRS for Mobile SDRAM
Reserved
Reserved
Reserved
0
1
0
1
Reserved Address
1
0
Reserved
A12~A10/AP
0
A9
0
A8
0
A7
0
A4
0
A3
0
1
0
Reserved
1
1
Reserved
1
1
Reserved
NOTES:
1. RFU(Reserved for future use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. Full Page Length : x32 : 64Mb(256) , 128Mb (256), 256Mb (512), 512Mb (512)
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March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- 1/4 Array
- Full Array
- 1/2 Array
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; 45 °C and 85 °C(for Extended), 70 °C(for Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/-5 °C tolerance.
Self Refresh Current (Icc6)
Temperature Range
-G/F
1/2 of Full Array
700
Unit
-N/L
Full Array
800
1/4 of Full Array
85/70 °C
45 °C *3
625
425
800
uA
500
450
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
11
March 2006
K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
0
A0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
0
A1
0
A0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
6
7
0
1
2
3
4
0
3
2
5
4
7
6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
12
March 2006
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