K4H560838E-ULA2_技术文档

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

256Mb E-die DDR SDRAM Specification

66 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.1

October, 2004

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

256Mb E-die Revision History

Revision 1.0 (February, 2004)

-First release

Revision 1.1 (October, 2004)

-Corrected typo.

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Key Features

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• DM for write masking only (x4, x8)

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 66pin TSOP II Pb-Free package

• RoHS compliant

Ordering Information

Part No.

Org.

Max Freq.

Interface

Package

K4H560438E-UC/LB3

K4H560438E-UC/LAA

K4H560438E-UC/LA2

K4H560438E-UC/LB0

K4H560838E-UC/LB3

K4H560838E-UC/LAA

K4H560838E-UC/LA2

K4H560838E-UC/LB0

B3(DDR333@CL=2.5)

AA(DDR266@CL=2)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

AA(DDR266@CL=2)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

64M x 4

SSTL2

66pin TSOP II

32M x 8

SSTL2

66pin TSOP II

Operating Frequencies

B3(DDR333@CL=2.5) AA(DDR266@CL=2.0) A2(DDR266@CL=2.0) B0(DDR266@CL=2.5)

Speed @CL2

Speed @CL2.5

133MHz

166MHz

133MHz

100MHz

133MHz

*CL : CAS Latency

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Pin Description

32Mb x 8

64Mb x 4

V

SS

V

SS

1

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

V

DD

V

DD

NC

DQ

7

2

DQ

0

NC

DDQ

NC

VSSQ

3

VDDQ

V

NC

DQ

NC

DQ

4

NC

3

6

5

DQ

1

DQ

0

VDDQ

6

VSSQ

NC

DQ

7

NC

DDQ

NC

5

8

DQ

2

DDQ

NC

VSSQ

9

V

NC

DQ

NC

DQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

66Pin TSOPII

(400mil x 875mil)

(0.65mm Pin Pitch)

2

4

DQ

3

DQ

1

VDDQ

VSSQ

NC

DDQ

NC

DDQ

NC

Bank Address

BA0~BA1

VSSQ

V

DQS

NC

DQS

NC

Auto Precharge

A10

VREF

VDD

VSS

NC

DM

CK

DM

CK

WE

CAS

RAS

CS

WE

CAS

RAS

CS

CK

CKE

NC

CKE

NC

24

25

26

27

28

29

30

31

32

33

A

V

12

11

9

A

V

12

11

9

NC

BA

0

BA

0

BA

1

BA

1

8

AP/A¹⁰

AP/A10

7

A

0

1

2

3

A

0

1

2

3

6

5

4

SS

VDD

256Mb TSOPII Package Pinout

Organization

64Mx4

Row Address

A0~A12

Column Address

A0-A9, A11

A0-A9

32Mx8

A0~A12

DM is internally loaded to match DQ and DQS identically.

Row & Column address configuration

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Package Physical Dimension

Units : Millimeters

#66

#34

(10×)

#1

#33

+0.075

-0.035

0.125

(1.50)

22.22±0.10

(10×)

0.10 MAX

0.25TYP

(0.71)

0.65TYP

0.65±0.08

0.30±0.08

[

]

0.075 MAX

NOTE

1. (

0×~8×

) IS REFERENCE

2. [

] IS ASS’Y OUT QUALITY

66pin TSOPII / Package dimension

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Block Diagram (16Mbit x 4 / 8Mbit x 8 I/O x 4 Banks)

(L)WE

(L)DM

x4/8

CK, CK

Data Input Register

Serial to parallel

Bank Select

x8/16

8Mx8/ 4Mx16

x8/16

x4/8

DQi

CK, CK

ADD

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

LCKE

LRAS LCBR

LWE

LCAS

CK, CK

DM

Timing Register

CK, CK

CKE

CS

RAS

CAS

WE

DM

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

Clock : CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to

both edges of CK. Internal clock signals are derived from CK/CK.

CK, CK

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN

(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,

which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-

ing power-down and self refresh modes, providing low standby power. CKE will recognize an

LVCMOS LOW level prior to VREF being stable on power-up.

CKE

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code.

CS

Input

RAS, CAS, WE

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS

loading.

DM

Input

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-

CHARGE command is being applied.

BA0, BA1

Address Inputs : Provide the row address for ACTIVE commands, and the column address and

AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-

ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-

mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also

provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which

mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).

A [0 : 12]

Input

DQ

I/O

Data Input/Output : Data bus

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DQS

NC

-

No Connect : No internal electrical connection is present.

DQ Power Supply : +2.5V ± 0.2V.

DQ Ground.

VDDQ

VSSQ

VDD

Supply

Input

Power Supply : +2.5V ± 0.2V (device specific).

Ground.

VSS

VREF

SSTL_2 reference voltage.

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

A0 ~ A9,

COMMAND

CKEn-1 CKEn CS RAS CAS

WE BA0,1 A10/AP

Note

A11,A12

Register

Extended MRS

Mode Register Set

Auto Refresh

H

X

H

L

OP CODE

1, 2

3

H

L

H

X

Entry

Refresh

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

Exit

L

H

X

3

Bank Active & Row Addr.

Read &

Column Address

V

Row Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

4, 6

7

Column

Address

L

H

L

H

Write &

Column Address

Column

Address

H

X

L

H

L

H

L

V

H

Burst Stop

Precharge

X

Bank Selection

All Banks

V

X

L

H

X

5

H

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

Active Power Down

X

Entry

H

Precharge Power Down Mode

H

L

Exit

L

H

X

DM(UDM/LDM for x16 only)

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

Note :1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks Double Data Rate SDRAM

General Description

The K4H560438E / K4H560838E is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x

8,388,608 words by 4/ 8/ bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe

allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating fre-

quencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance mem-

ory system applications.

Absolute Maximum Rating

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V_SS

V_IN, V_OUT

-0.5 ~ 3.6

V

Voltage on V_DD& V_DDQsupply relative to V_SS

Storage temperature

V_DD, V_DDQ

T_STG

P_D

-1.0 ~ 3.6

-55 ~ +150

1.5

V

°C

W

Power dissipation

Short circuit current

I_OS

50

mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Conditions

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Symbol

VDD

Min

2.3

Max

2.7

Unit

Note

Supply voltage(for device with a nominal VDD of 2.5V)

I/O Supply voltage

I/O Reference voltage

I/O Termination voltage(system)

VDDQ

VREF

V_TT

2.3

0.49*VDDQ

VREF-0.04

2.7

0.51*VDDQ

VREF+0.04

V

1

2

V

Input logic high voltage

Input logic low voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input leakage current

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VI(Ratio)

II

VREF+0.15

-0.3

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.4

V

-0.3

0.36

0.71

-2

3

4

-

2

5

uA

mA

Output leakage current

Output High Current(Normal strengh driver) ;V_OUT= V_TT+ 0.84V

IOZ

-5

IOH

-16.8

Output High Current(Normal strengh driver) ;V_OUT= V_TT- 0.84V

Output High Current(Half strengh driver) ;V_OUT= V_TT+ 0.45V

Output High Current(Half strengh driver) ;V_OUT= V_TT- 0.45V

IOL

IOH

IOL

16.8

-9

mA

9

Note :

1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.

Peak-to peak noise on VREF may not exceed +/-2% of the dc value.

2. V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the

maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the

maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

DDR SDRAM Spec Items & Test Conditions

Conditions

Symbol

IDD0

Operating current - One bank Active-Precharge;

tRC=tRCmin; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333;

DQ,DM and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating current - One bank operation ; One bank open, BL=4, Reads

IDD1

- Refer to the following page for detailed test condition

Percharge power-down standby current; All banks idle; power - down mode;

IDD2P

CKE = <VIL(max); tCK=10ns for DDR200,7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM.

Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200,

7.5ns for DDR266, 6ns for DDR333; Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ,DQS and DM

IDD2F

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min); tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; Address and other control inputs

stable at >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM

IDD2Q

IDD3P

Active power - down standby current ; one bank active; power-down mode;

CKE=< VIL (max); tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333;

DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock

cycle

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control

inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at

7.5ns for DDR266(B0), 6ns for DDR333; 50% of data changing on every transfer; lout = 0 m A

IDD3N

IDD4R

IDD4W

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle; CL=2 at tCK= 10ns for DDR200, CL=2

at tCK=7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333; DQ, DM and DQS inputs

changing twice per clock cycle, 50% of input data changing at every burst

Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at tCK=10ns; 10*tCK for DDR266 at tCK=7.5ns;

IDD5

IDD6

12*tCK for DDR333 at tCK=6ns; distributed refresh

Self refresh current; CKE =< 0.2V; External clock on; tCK = 10ns for DDR200, tCK=7.5ns for DDR266, 6ns for

DDR333.

Orerating current - Four bank operation ; Four bank interleaving with BL=4

IDD7A

-Refer to the following page for detailed test condition

Input/Output Capacitance

(V_DD=2.5, V_DDQ=2.5V, T_A= 25°C, f=1MHz)

Delta

0.5

Parameter

Symbol

Min

Max

Unit

Note

Input capacitance

CIN1

2

3

pF

4

(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)

Input capacitance( CK, CK )

CIN2

COUT

CIN3

2

4

3

5

0.25

pF

4

Data & DQS input/output capacitance

Input capacitance(DM for x4/8)

1,2,3,4

0.5

Note :

1.These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.

This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameteer is sampled. VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +0.25V+0.2V, f=100MHz, tA=25°C, Vout(dc) =

VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading

(to facilitate trace matching at the board level).

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >

IDD1 : Operating current: One bank operation

1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

2. Timing patterns

- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- AA (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK

Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK

Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

IDD7A : Operating current: Four bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- AA(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

DDR SDRAM I spec table

(V_DD=2.7V, T = 10°C)

DD

64Mx4 (K4H560438E)

AA(DDR266@CL=2.0)

Symbol

Unit

Notes

A2(DDR266@CL=2.0)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

IDD0

IDD1

90

110

3

25

20

90

110

3

20

18

80

100

3

20

18

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

35

55

30

45

30

45

140

160

170

3

1.5

260

120

135

160

3

1.5

260

120

135

160

3

1.5

240

Normal

Low power

IDD7A

IDD6

Optional

32Mx8 (K4H560838E)

AA(DDR266@CL=2.0)

Symbol

Unit

Notes

A2(DDR266@CL=2.0)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

IDD0

IDD1

90

115

3

25

20

90

115

3

20

18

80

105

3

20

18

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

35

55

30

45

30

45

160

170

3

1.5

280

140

135

160

3

1.5

280

140

135

160

3

1.5

250

Normal

Low power

IDD7A

IDD6

Optional

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

AC Operating Conditions

Parameter/Condition

Symbol

VIH(AC)

VIL(AC)

VID(AC)

Min

VREF + 0.31

Max-10

Unit

V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and /CK inputs

VREF - 0.31

VDDQ+0.6

0.7

1

2

Input Crossing Point Voltage, CK and /CK inputs

VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2

Notes :

1. VID is the magnitude of the difference between the input level on CK and the input level on /CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

AC Overshoot/Undershoot specification for Address and Control Pins

Specification

Parameter

DDR333

TBD

DDR200/266

Maximum peak amplitude allowed for overshoot

Maximum peak amplitude allowed for undershoot

1.5 V

TBD

The area between the overshoot signal and VDD must be less than or equal to

The area between the undershoot signal and GND must be less than or equal to

TBD

4.5 V-ns

VDD

Overshoot

5

4

3

Maximum Amplitude = 1.5V

2

Area = 4.5V-ns

1

0

-1

-2

Maximum Amplitude = 1.5V

GND

-3

-4

-5

0

0.6875

0.5 1.0

1.5

2.5

3.5

4.5

5.5

6.3125

6.0 6.5

undershoot

7.0

2.0

3.0

4.0

5.0

Tims(ns)

AC overshoot/Undershoot Definition

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Overshoot/Undershoot specification for Data, Strobe, and Mask Pins

Specification

Parameter

DDR333

DDR200/266

1.2 V

Maximum peak amplitude allowed for overshoot

Maximum peak amplitude allowed for undershoot

The area between the overshoot signal and VDD must be less than or equal to

The area between the undershoot signal and GND must be less than or equal to

TBD

1.2 V

2.4 V-ns

VDDQ

Overshoot

5

Maximum Amplitude = 1.2V

4

3

2

Area = 2.4V-ns

1

0

-1

-2

Maximum Amplitude = 1.2V

GND

-3

-4

-5

0

0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0

Tims(ns)

undershoot

DQ/DM/DQS AC overshoot/Undershoot Definition

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

AC Timming Parameters & Specifications

B3

B0

AA

A2

(DDR333@CL=2.5)

(DDR266@CL=2.5)

(DDR266@CL=2.0) (DDR266@CL=2.0)

Parameter

Symbol

Unit Note

Min

60

Max

Min

60

Max

Min

65

Max

Min

65

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

72

75

42

70K

45

120K

45

120K

45

120K

ns

RAS to CAS delay

18

15

20

ns

Row precharge time

18

15

20

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

12

15

ns

15

ns

Last data in to Read command

Col. address to Col. address delay

tWTR

tCCD

1

tCK

ns

1

CL=2.0

CL=2.5

7.5

6

12

7.5

0.45

-0.75

-

12

7.5

0.45

-0.75

-

12

10

12

Clock cycle time

tCK

12

7.5

0.45

-0.75

-

ns

Clock high level width

tCH

tCL

0.45

-0.6

-0.7

-

0.55

+0.6

+0.7

0.45

1.1

0.55

+0.75

0.5

0.55

+0.75

0.5

0.55

+0.75

0.5

tCK

ns

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

ns

12

3

0.9

0.4

0.75

0

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.9

0.25

0.2

0.35

0.9

0.25

0.2

0.35

0.9

0.25

0.2

0.35

0.9

tCK

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

tDSH

tDQSH

tDQSL

tDSC

DQS-in low level width

DQS-in cycle time

1.1

Address and Control Input setup time(fast)

tIS

i,5.7

i,

0.75

0.8

0.9

1.0

0.9

1.0

0.9

1.0

ns

Address and Control Input hold time(fast)

Address and Control Input setup time(slow)

Address and Control Input hold time(slow)

tIH

tIS

tIH

i,

0.8

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

tHZ

tLZ

-0.7

0.67

+0.7

1.5

-0.75

0.67

+0.75

1.5

-0.75

0.67

+0.75

1.5

-0.75

0.67

+0.75

1.5

ns

1

Output Slew Rate Matching Ratio(rise to fall) tSLMR

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

B3

AA

A2

B0

(DDR333@CL=2.5)) (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5))

Parameter

Symbol

Unit Note

Min

12

Max

Min

15

Max

Min

15

Max

Min

15

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

ns

0.45

0.5

ns

j, k

tDH

0.45

0.5

Control & Address input pulse width

DQ & DM input pulse width

Power down exit time

tIPW

tDIPW

tPDEX

2.2

1.75

6

2.2

1.75

7.5

2.2

1.75

7.5

2.2

1.75

7.5

ns

8

ns

Exit self refresh to non-Read command tXSNR

75

ns

Exit self refresh to read command

Refresh interval time

tXSRD

tREFI

200

tCK

us

7.8

-

7.8

-

7.8

-

7.8

-

4

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

ns

11

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

-

ns 10, 11

Data hold skew factor

tQHS

0.55

0.6

0.75

0.6

0.75

0.6

0.75

0.6

ns

11

2

DQS write postamble time

tWPST

0.4

18

0.4

20

0.4

20

0.4

20

tCK

Active to Read with Auto precharge

command

tRAP

Autoprecharge write recovery +

Precharge time

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

tDAL

tCK

13

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure

proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

DDR333

DDR266

DDR200

PARAMETER

SYMBOL

DCSLEW

MIN

MAX

MIN

MAX

MIN

MAX

Units

V/ns

Notes

a, m

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

TBD

0.5

4.0

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

tIS

tIH

Units

Notes

0.5 V/ns

0

ps

i

0.4 V/ns

+50

+100

0

ps

0.3 V/ns

0

ps

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

tDS

tDH

Units

Notes

0.5 V/ns

0

ps

k

0.4 V/ns

+75

+150

+75

+150

ps

0.3 V/ns

ps

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

tDS

tDH

Units

Notes

+/- 0.0 V/ns

0

ps

j

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

ps

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

(V/ns)

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

Table 6 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS DDR266

DDR200

PARAMETER

Output Slew Rate Matching Ratio (Pullup to Pulldown)

MIN

TBD

MAX

TBD

MIN

0.67

MAX

1.5

Notes

e,m

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Component Notes

1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a

specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).

2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys

tem performance (bus turnaround) will degrade accordingly.

3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ

ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

5. For command/address input slew rate ≥ 1.0 V/ns

6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

7. For CK & CK slew rate ≥ 1.0 V/ns

8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

9. Slew Rate is measured between VOH(ac) and VOL(ac).

10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the

period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into

the clock traces.

11. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst

case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

channel to n-channel variation of the output drivers.

12. tDQSQ

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.

13. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and

tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)

tDAL = 5 clocks

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50Ω

VSSQ

Figure 1 : Pullup slew rate test load

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

DDR SDRAM

50Ω

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotony.

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

IBIS :I/V Characteristics for Input and Output Buffers

DDR SDRAM Output Driver V-I Characteristics

DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.

Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input

into simulation tools. The driver characteristcs evaluation conditions are:

Typical

Minimum

Maximum

25×C

70×C

0×C

Vdd/Vddq = 2.5V, typical process

Vdd/Vddq = 2.3V, slow-slow process

Vdd/Vddq = 2.7V, fast-fast process

Output Driver Characteristic Curves Notes:

1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines

the of the V-I curve of Figure 3 and 4.

2. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figure 3 and 4.

3. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity +/- 10%, for device drain to

source voltages from 0.1 to1.0. This specification is a design objective only. It is not guaranteed.

160

Maximum

140

120

Typical High

100

80

Typical Low

Minimum

60

40

20

0

0.0

0.5

1.0

1.5

2.0

2.5

Vout(V)

Pullup Characteristics for Full Strength Output Driver

0.0

1.0

2.0

0

-20

Minumum

Typical Low

-40

-60

-80

-100

-120

-140

-160

-180

-200

-220

Typical High

Maximum

Vout(V)

Pulldown Characteristics for Full Strength Output Driver

Figure 3. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Pulldown Current (mA)

pullup Current (mA)

Voltage

(V)

Typical

Low

Typical

High

Typical

Low

Typical

High

Minimum

Maximum

Minimum

Maximum

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

6.0

6.8

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

4.6

9.2

9.6

18.2

26.0

33.9

41.8

49.4

56.8

63.2

69.9

76.3

82.5

88.3

93.8

99.1

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

-6.1

-7.6

-14.5

-21.2

-27.7

-34.1

-40.5

-46.9

-53.1

-59.4

-65.5

-71.6

-77.6

-83.6

-89.7

-95.5

-101.3

-107.1

-112.4

-118.7

-124.0

-129.3

-134.6

-139.9

-145.2

-150.5

-155.3

-160.1

-4.6

-9.2

-10.0

-20.0

-29.8

-38.8

-46.8

-54.4

-61.8

-69.5

-77.3

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

-12.2

-18.1

-24.0

-29.8

-34.3

-38.1

-41.1

-41.8

-46.0

-47.8

-49.2

-50.0

-50.5

-50.7

-51.0

-51.1

-51.3

-51.5

-51.6

-51.8

-52.0

-52.2

-52.3

-52.5

-52.7

-52.8

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

-13.8

-18.4

-23.0

-27.7

-32.2

-36.0

-38.2

-38.7

-39.0

-39.2

-39.4

-39.6

-39.9

-40.1

-40.2

-40.3

-40.4

-40.5

-40.6

-40.7

-40.8

-40.9

-41.0

-41.1

-41.2

-85.2

-93.0

-100.6

-108.1

-115.5

-123.0

-130.4

-136.7

-144.2

-150.5

-156.9

-163.2

-169.6

-176.0

-181.3

-187.6

-192.9

-198.2

Table 8. Full Strength Driver Characteristics

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

90

80

70

60

50

40

30

20

10

0

Maximum

Typical High

Typical Low

Minimum

0.0

1.0

2.0

Vout(V)

Pullup Characteristics for Weak Output Driver

0.0

1.0

2.0

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

Minumum

Typical Low

Typical High

Maximum

Vout(V)

Pulldown Characteristics for Weak Output Driver

Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

Rev. 1.1 October, 2004

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

DDR SDRAM

Pulldown Current (mA)

pullup Current (mA)

Voltage

(V)

Typical

Low

Typical

High

Typical

Low

Typical

High

Minimum

Maximum

Minimum

Maximum

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.4

6.9

3.8

7.6

2.6

5.2

7.8

5.0

9.9

-3.5

-6.9

-4.3

-8.2

-2.6

-5.2

-7.8

-5.0

-9.9

10.3

13.6

16.9

19.6

22.3

24.7

26.9

29.0

30.6

31.8

32.8

33.5

34.0

34.3

34.5

34.8

35.1

35.4

35.6

35.8

36.1

36.3

36.5

36.7

36.8

11.4

15.1

18.7

22.1

25.0

28.2

31.3

34.1

36.9

39.5

42.0

44.4

46.6

48.6

50.5

52.2

53.9

55.0

56.1

57.1

57.7

58.2

58.7

59.2

59.6

14.6

19.2

23.6

28.0

32.2

35.8

39.5

43.2

46.7

50.0

53.1

56.1

58.7

61.4

63.5

65.6

67.7

69.8

71.6

73.3

74.9

76.4

77.7

78.8

79.7

-10.3

-13.6

-16.9

-19.4

-21.5

-23.3

-24.8

-26.0

-27.1

-27.8

-28.3

-28.6

-28.7

-28.9

-29.0

-29.2

-29.3

-29.5

-29.6

-29.7

-29.8

-29.9

-12.0

-15.7

-19.3

-22.9

-26.5

-30.1

-33.6

-37.1

-40.3

-43.1

-45.8

-48.4

-50.7

-52.9

-55.0

-56.8

-58.7

-60.0

-61.2

-62.4

-63.1

-63.8

-64.4

-65.1

-65.8

-14.6

-19.2

-23.6

-28.0

-32.2

-35.8

-39.5

-43.2

-46.7

-50.0

-53.1

-56.1

-58.7

-61.4

-63.5

-65.6

-67.7

-69.8

-71.6

-73.3

-74.9

-76.4

-77.7

-78.8

-79.7

10.4

13.0

15.7

18.2

20.8

22.4

24.1

25.4

26.2

26.6

26.8

27.0

27.2

27.4

27.7

27.8

28.0

28.1

28.2

28.3

28.4

28.5

28.6

-10.4

-13.0

-15.7

-18.2

-20.4

-21.6

-21.9

-22.1

-22.2

-22.3

-22.4

-22.6

-22.7

-22.8

-22.9

-23.0

-23.1

-23.2

-23.3

Table 9. Weak Driver Characteristics

Rev. 1.1 October, 2004


型号：	K4H560838E-ULA2
厂家：	SAMSUNG
描述：	256Mb E-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) 256Mb的电子芯片DDR SDRAM规格66 TSOP- II与无铅（符合RoHS）电子动态存储器双倍数据速率
文件：	总23页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4H560838E-ULA2 [SAMSUNG]

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