K4H511638D-KLB3 [SAMSUNG]
DDR DRAM, 32MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, MS-024FC, TSOP2-66;
| 型号： | K4H511638D-KLB3 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 32MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, MS-024FC, TSOP2-66 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512Mb(x16, DDP)
DDR SDRAM
DDP 512Mbit DDR SDRAM
8M x 16bit x 4 Banks
DDR SDRAM Specification
Revision 1.0
July. 2002
This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM
products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,
work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones,
telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are,
however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev 1.0 July. 2002
- 1 -
512Mb(x16, DDP)
DDR SDRAM
Revision History
Revision 1.0 (July. 2002)
Rev 1.0 July. 2002
- 2 -
512Mb(x16, DDP)
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Operating Frequencies
- B3(DDR333)
133MHz
- A2(DDR266A)
133MHz
- B0(DDR266B)
100MHz
- A0(DDR200)
Speed @CL2
100MHz
-
Speed @CL2.5
166MHz
133MHz
133MHz
*CL : Cas Latency
Functional Block Diagram
CK,CK,CAS
RAS,WE, CS, CKE
32Mx8
32Mx8
I/O8 ~ I/O15,UDQS
A0-A12,BA0,BA1
I/O0 ~ I/O7,LDQS
Rev 1.0 July. 2002
- 3 -
512Mb(x16, DDP)
DDR SDRAM
Package Pinout
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
VDD
DQ0
2
DQ15
VSSQ
3
VDDQ
DQ1
4
DQ14
DQ13
5
DQ2
6
VDDQ
DQ12
VSSQ
7
DQ3
DQ4
8
DQ11
VSSQ
9
VDDQ
DQ5
DQ10
DQ9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
DQ6
VSSQ
DQ7
NC
VDDQ
DQ8
NC
Bank Address
BA0-BA1
VSSQ
UDQS
VDDQ
LDQS
NC
Row Address
A0-A12
NC
VREF
VDD
NC
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
Column Address
A0-A9
LDM
W E
CAS
RAS
CS
Auto Precharge
A10
24
25
26
27
28
29
30
31
32
33
NC
MS-024FC
BA0
BA1
AP/A 10
A0
A8
A7
A6
A1
A5
A2
A4
A3
VSS
VDD
Rev 1.0 July. 2002
- 4 -
512Mb(x16, DDP)
DDR SDRAM
Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
CS
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
RAS, CAS , WE
LDM,(U)DM
Input
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
BA0, BA1
A [n : 0]
Input
Input
Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
DQ
I/O
I/O
Data Input/Output : Data bus
LDQS,(U)DQS
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
NC
-
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V.
DQ Ground.
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
Input
Power Supply : +2.5V ± 0.2V (device specific).
Ground.
VSS
VREF
SSTL_2 reference voltage.
Rev 1.0 July. 2002
- 5 -
512Mb(x16, DDP)
Command Truth Table
COMMAND
DDR SDRAM
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
A11, A12
A9 ~ A 0
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
L
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4
Column
L
H
L
H
Address
H
L
Write &
Column Address
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA 1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA 1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA 0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tR P after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev 1.0 July. 2002
- 6 -
512Mb(x16, DDP)
DDR SDRAM
8M x 16Bit x 4 Banks Double Data Rate SDRAM
GENERAL DESCRIPTION
The K4H561638D is 536,870,912 bits of double data rate synchronous DRAM organized as 4 x 8,392,608 words by 16 bits, fabricated
with SAMSUNG¢s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to
333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
3
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS =0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
VREF
2.3
2.7
V
V
I/O Reference voltage
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL (DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
-0.3
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
-0.3
V
0.3
V
3
5
1.15
-2
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
IOL
-16.8
16.8
-9
mA
mA
mA
mA
;V
= V + 0.84V
TT
OUT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
9
OUT
TT
Rev 1.0 July. 2002
- 7 -
512Mb(x16, DDP)
DDR SDRAM
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise
coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of V REF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V IX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
K4H511638D-KC(L)B3
(DDR333)
K4H511638D-KC(L)A2/CB0
(DDR266A/B)
K4H511638D-KC(L)A0
(DDR200)
Symbol
Unit
Notes
IDD0
IDD1
180
240
6
160
220
6
150
200
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
50
40
36
40
36
32
70
60
50
110
340
340
360
6
90
80
280
280
330
6
240
230
300
6
IDD6
Normal
Low power
IDD7A
3
3
3
Optional
650
560
470
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Overshoot/Undershoot specification
Specification
Parameter
Address &
Control pins
Data pins
Maximum peak amplitude allowed for overshoot
1.6 V
1.6 V
1.2V
1.2V
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
4.5 V-ns
4.5 V-ns
2.5 V-ns
2.5 V-ns
Rev 1.0 July. 2002
- 8 -
512Mb(x16, DDP)
DDR SDRAM
AC Timming Parameters & Specifications
KCB3
(DDR333)
-KCA2
(DDR266A)
-KCB0
(DDR266B)
-KCA0
(DDR200)
Parameter
Symbol
Unit Note
Min Max
Min
65
Max
Min
65
Max
Min
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
60
72
70
80
48
20
20
15
15
1
ns
ns
Refresh row cycle time
Row active time
75
75
42
70K
45
120K
45
120K
120K
ns
RAS to CAS delay
18
20
20
ns
Row precharge time
18
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
12
15
15
ns
15
15
15
ns
Last data in to Read command
Col. address to Col. address delay
tWTR
tCCD
1
1
1
tCK
tCK
ns
1
1
1
1
CL=2.0
CL=2.5
7.5
6
12
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
10
12
5
5
Clock cycle time
tCK
12
7.5
0.45
0.45
-0.75
-0.75
-
ns
Clock high level width
tCH
tCL
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.55
0.55
+0.75
+0.75
0.5
0.55
0.55
+0.75
+0.75
0.5
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
0.6
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
ns
5
2
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
-0.7
-0.7
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
1.1
1.1
1.1
1.1
-0.8
-0.8
0.5
0.5
1.0
0.67
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
1.1
1.1
1.1
1.1
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
6
6
6
6
tIH
ns
tIS
ns
tIH
ns
tHZ
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
+0.8
+0.8
ns
tLZ
ns
tSL(I)
tSL(IO)
tSL(O)
V/ns
V/ns
V/ns
6
7
4.5
1.5
4.5
1.5
4.5
1.5
4.5
1.5
10
Output Slew Rate Matching Ratio(rise to fall) tSLMR
Rev 1.0 July. 2002
- 9 -
512Mb(x16, DDP)
DDR SDRAM
-KCB3
(DDR333)
-KCA2
(DDR266A)
-KCB0
(DDR266B)
-KCA0
(DDR200)
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
12
15
15
16
ns
ns
ns
0.45
0.5
0.5
0.6
7,8,9
7,8,9
tDH
0.45
0.5
0.5
0.6
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
tIPW
tDIPW
tPDEX
2.2
1.75
6
2.2
1.75
7.5
75
2.2
1.75
7.5
2.5
2
ns
ns
10
80
200
7.8
ns
Exit self refresh to non-Read command tXSNR
75
75
ns
4
Exit self refresh to read command
Refresh interval time
tXSRD
tREFI
200
7.8
200
7.8
200
7.8
tCK
us
1
5
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
-
-
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
Data hold skew factor
tQHS
0.55
0.6
0.75
0.6
0.75
0.6
0.8
0.6
ns
DQS write postamble time
tWPST
0.4
20
0.4
20
0.4
20
0.4
20
tCK
3
Active to Read with Auto precharge
command
tRAP
tDAL
Autoprecharge write recovery +
Precharge time
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
tCK
11
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(ps)
0
(V/ns)
0.5
0.4
+75
+150
+75
+150
0.3
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev 1.0 July. 2002
- 10 -
512Mb(x16, DDP)
DDR SDRAM
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
+50
DtDH
(ps)
± 280
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS /tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
DtIH/tIS
DtDSS/tDSH
DtAC/tDQSCK
DtLZ(min)
DtHZ(max)
(Single ended)
(ps)
(ps)
(ps)
(ps)
(ps)
1.0V/ns
0.75V/ns
0.5V/ns
0
0
0
0
0
+50
+100
+50
+100
+50
+100
-50
-100
+50
+100
Rev 1.0 July. 2002
- 11 -
512Mb(x16, DDP)
DDR SDRAM
AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(VIH/VIL)
Value
Unit
V
Note
0.5 * VDDQ
1.5
V
1.0
VREF+0.31/VREF-0.31
VREF
V/ns
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
4.0
6.0
pF
Input capacitance( CK, CK )
Data & DQS input/output capacitance
Input capacitance(DM)
CIN2
COUT
CIN3
4.0
4.0
4.0
6.0
6.0
6.0
pF
pF
pF
Rev 1.0 July. 2002
- 12 -
相关型号：
K4H511638D-UC/LA2
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
SAMSUNG
K4H511638D-UC/LB0
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
SAMSUNG
©2020 ICPDF网 联系我们和版权申明