K4E170812D-F [SAMSUNG]
DRAM;
| 型号： | K4E170812D-F |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM 动态存储器 |
| 文件： | 总21页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
2M x 8Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to real-
ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal
computer.
FEATURES
• Part Identification
• Extended Data Out Mode operation
(Fast page mode with Extended Data Out)
• CAS-before-RAS refresh capability
- K4E170811D-B(F) (5V, 4K Ref.)
• RAS-only and Hidden refresh capability
- K4E160811D-B(F) (5V, 2K Ref.)
• Self-refresh capability (L-ver only)
- K4E170812D-B(F) (3.3V, 4K Ref.)
- K4E160812D-B(F) (3.3V, 2K Ref.)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
Unit : mW
5V
3.3V
Speed
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
4K
2K
396
360
4K
2K
-50
-60
324
288
495
440
605
550
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
Refresh
cycle
Refresh period
VCC
RAS
CAS
W
Vcc
Vss
NO.
Control
Clocks
Normal
L-ver
VBB Generator
K4E170811D
5V
4K
2K
64ms
K4E170812D 3.3V
K4E160811D 5V
Data in
Buffer
128ms
Row Decoder
Refresh Timer
Refresh Control
Refresh Counter
32ms
K4E160812D 3.3V
DQ0
to
DQ7
Memory Array
2,097,152 x8
Cells
• Performance Range
A0-A11
(A0 - A10)*1
A0 - A8
Row Address Buffer
Col. Address Buffer
Speed
-50
Remark
tRAC
50ns
60ns
tCAC
tRC
tHPC
Data out
Buffer
13ns
84ns
20ns 5V/3.3V
Column Decoder
OE
(A0 - A9)*1
-60
15ns 104ns 25ns 5V/3.3V
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E17(6)0811(2)D-F
• K4E17(6)0811(2)D-B
VCC
DQ0
DQ1
DQ2
DQ3
W
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VCC
DQ0
DQ1
DQ2
DQ3
1
2
3
4
5
6
7
8
9
28 VSS
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
W
RAS
RAS
*A11(N.C)
A10
*A11(N.C)
A10
9
A0
A1
A2
A3
10
11
12
13
14
A0 10
A1 11
A2 12
A3 13
A5
A4
VSS
16 A4
15 VSS
VCC
VCC
14
*A11 is N.C for K4E160811(2)D(5V/3.3V, 2K Ref. product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 7
VSS
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
CAS
W
OE
Data Output Enable
Power(+5V)
VCC
N.C
Power(+3.3V)
No Connection (2K Ref. product)
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Units
3.3V
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
5V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN,VOUT
VCC
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
V
V
Tstg
°C
W
Power Dissipation
PD
Short Circuit Output Current
IOS Address
50
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
3.3V
5V
Typ
5.0
0
Parameter
Symbol
Units
Min
3.0
0
Typ
Max
3.6
0
Min
4.5
0
Max
5.5
0
Supply Voltage
VCC
VSS
VIH
VIL
3.3
V
V
V
V
Ground
0
-
*1
*1
Input High Voltage
Input Low Voltage
2.0
2.4
-
VCC+0.3
0.8
VCC+1.0
0.8
*2
*2
-
-
-0.3
-1.0
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
3.3V
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Input Leakage Current (Any input 0£VIN£VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
5V
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
K4E170812D
K4E160812D
K4E170811D
K4E160811D
-50
-60
90
80
110
100
90
80
110
100
mA
mA
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Don¢t care
Normal
L
1
1
1
1
2
1
2
1
mA
mA
Don¢t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
Don¢t care
Don¢t care
-50
-60
80
70
90
80
80
70
90
80
mA
mA
Normal
L
0.5
200
0.5
200
1
250
1
250
mA
uA
Don¢t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
250
200
250
200
300
250
300
250
uA
uA
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don¢t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Hyper page mode cycle time, tHPC.
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Symbol
Min
Max
Units
pF
CIN1
CIN2
CDQ
-
-
-
5
7
7
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ7]
pF
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
-50
-60
Parameter
Symbol
Units
Notes
Min
84
Max
Min
104
140
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
116
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay from CAS
OE to output in Low-Z
13
50
15
50
6,14
3
3
3
Transition time (rise and fall)
RAS precharge time
2
2
2
30
50
13
38
8
40
60
15
45
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
20
15
5
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
8
10
30
0
25
0
0
0
8
8
0
0
10
10
13
8
10
10
15
10
tRWL
tCWL
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
AC CHARACTERISTICS (Continued)
-50
-60
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Data set-up time
0
0
ns
9
9
tDS
Data hold time
8
10
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
tDH
Refresh period (2K, Normal)
Refresh period (4K, Normal)
Refresh period (L-ver)
32
64
32
64
tREF
tREF
128
128
tREF
Write command set-up time
0
0
7
7
7
7
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
CAS to W delay time
30
67
42
47
5
34
79
49
54
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
10
5
10
5
28
35
3
20
47
8
25
56
10
60
35
13
13
tHPC
tHPRWC
tCP
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper Page cycle)
RAS pulse width (Hyper Page cycle)
RAS hold time from CAS precharge
OE access time
50
30
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
OE to data delay
13
3
15
3
Output buffer turn off delay time from OE
OE command hold time
13
15
6
13
10
10
10
10
5
15
10
10
10
10
5
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
11
11
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
15
15
6,14
6
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
15
5
15
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
5
5
100
90
-50
100
110
-50
15,16,17
15,16,17
15,16,17
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
( Note 11 )
TEST MODE CYCLE
-50
-60
Parameter
Symbol
Units
Note
Min
89
Max
Min
109
145
Max
Random read or write cycle time
ns
tRC
Read-modify-write cycle time
Access time from RAS
121
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAC
tCAC
tAA
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
30
35
55
13
18
43
30
35
72
47
52
25
53
55
10K
10K
65
15
20
50
35
39
84
54
59
30
61
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS pulse width
RAS hold time
CAS hold time
Column address to RAS lead time
CAS to W delay time
7
7
7
tCWD
tRWD
tAWD
tCPWD
tHPC
tHPRWC
tRASP
tCPA
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
Hyper Page cycle time
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper Page cycle)
Access time from CAS precharge
OE access time
13
13
200K
33
200K
40
3
18
20
tOEA
tOED
tOEH
OE to data delay
18
18
20
20
OE command hold time
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
2.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
5.
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-
tion of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle and the
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition
of the data out is indeterminate.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
10.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
11.
12.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
tASC³ 6ns, Assume tT = 2.0ns
13.
14. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
15.
16.
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-
cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.
17. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tRCH
tRRH
VIH -
VIL -
W
tWEZ
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCAC
tCLZ
DQ0 ~ DQ3(7)
VOH -
VOL -
tREZ
DATA-OUT
tRAC
OPEN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
tDS
DQ0 ~ DQ3(7)
VIH -
VIL -
tDH
DATA-IN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
DQ0 ~ DQ3(7)
VIH -
VIL -
tDH
DATA-IN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
tCSH
VIL -
tRAD
tRAH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tDS
tDH
DQ0 ~ DQ3(7)
tOEZ
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tRHCP
tCAS
tCSH
tHPC
tHPC
tCAS
tHPC
tCRP
tRCD
tCP
tCP
tCP
tCAS
tCAS
VIH -
CAS
VIL -
tRAD
tASR
tRAH tASC
tCAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
ROW
ADDR
A
tRAL
tRRH
tRCH
tRCS
VIH -
VIL -
W
tCPA
tCAC
tCAC
tAA
tCPA
tCAC
tAA
tCHO
tOEP
tAA
tCPA
tAA
tOCH
tOEA
VIH -
VIL -
tOEA
OE
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
DQ0 ~ DQ3(7)
VOH -
tRAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VOL -
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
VIL -
tRHCP
RAS
¡ó
tHPC
tHPC
tRSH
tCRP
tASR
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
¡ó
CAS
tRAD
tRAH
tCSH
tASC
tCAH
tASC
tCAH
tASC
tCAH
¡ó
¡ó
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
A
tRAL
tWCH
tWCS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ó
tWP
VIH -
VIL -
W
tCWL
tCWL
tCWL
tRWL
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ3(7)
VIH -
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
RAS
VIL -
tCSH
tRSH
tHPRWC
tCRP
tRCD
tCRP
VIH -
tCAS
tCAS
tRAL
CAS
VIL -
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
VIL -
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
DQ0 ~ DQ3(7)
tRAC
tCLZ
VI/OH -
VI/OL -
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
WRITE
READ(tAA)
RAS
tRHCP
tHPC
tHPC
tHPC
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAH
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tASC
tASC
tASC
VIH -
VIL -
COLUMN
ADDRESS
COL.
ADDR
COL.
ADDR
COLUMN
ADDRESS
ROW
ADDR
tRAL
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
DQ0 ~ DQ3(7)
tCLZ
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
VI/OL -
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
RAS
VIL -
tRAS
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
CAS
VIL -
tCHR
tWRP
tWRH
VIH -
W
VIL -
DQ0 ~ DQ3(7)
VOH -
VOL -
tCEZ
OPEN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tRAL
tCAH
COLUMN
tASR
tRAH
tASC
tRCS
VIH -
VIL -
ROW
ADDRESS
A
W
ADDRESS
tWRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCEZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
DQ0 ~ DQ3(7)
VOH -
tOEZ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tRAL
tCAH
tASR
tRAH
tASC
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDH
DATA-IN
DQ0 ~ DQ3(7)
VIH -
VIL -
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tRPC
tCHS
tCP
tCSR
VIH -
CAS
VIL -
DQ0 ~ DQ3(7)
VOH -
tCEZ
OPEN
VOL -
VIH -
VIL -
W
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tOFF
DQ0 ~ DQ3(7)
VOH -
VOL -
OPEN
Don¢t care
Undefined
K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
PACKAGE DIMENSION
28 SOJ 300mil
Units : Inches (millimeters)
#28
0.006 (0.15)
0.012 (0.30)
#1
0.027 (0.69)
MIN
0.741 (18.82)
MAX
0.720 (18.30)
0.730 (18.54)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
28 TSOP(II) 300mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.741 (18.81)
MAX
0.721 (18.31)
0.729 (18.51)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
0.018 (0.45)
0.030 (0.75)
MIN
0.012 (0.30)
0.020 (0.50)
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