K4C89083AF-GCFB [SAMSUNG]
288Mb x18 Network-DRAM2 Specification; 288MB X18网络DRAM2规格
| 型号： | K4C89083AF-GCFB |
| 厂家： | 
SAMSUNG |
| 描述： | 288Mb x18 Network-DRAM2 Specification |
| 文件： | 总55页 (文件大小：1469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4C89183AF
288Mb x18 Network-DRAM2 Specification
Version 0.7
- 1 -
REV. 0.7 Jan. 2005
K4C89183AF
Revision History
Version 0.0 (Oct. 2002)
- First Release
Version 0.01 (Nov. 2002)
- Changed die revision from D-die to F-die
- Corrected typo
- Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
From
To
Min
1.5
Max
2.5
Min
1.5
Max
3.0
Addr/CMD/CLK
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
From
To
F6
0.9
0.9
0.9
-
FB
0.9
0.9
0.9
-
F5
1.0
1.0
1.0
-
G7
F6
0.75
0.75
0.75
-
FB
0.8
0.8
0.8
-
F5
1.0
1.0
1.0
-
CL4
CL5
CL6
CL7
0.75
0.75
0.75
0.75
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
- Corrected min. Vref to VDDQ/2x95% in page 7
Version 0.2 (Aug. 2003)
- Added package physical dimension
- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)
- Changed DC test condition
From
To
Changed point
Changed condition
newly inserted
IDD1S,IDD2N,IDD2P,IDD5,IDD6 IDD1S,IDD2N,IDD2P,IDD5B,IDD6
-
IDD4W, IDD4R
- Changed low frequency spec like below
From
To
FB
6.0
6.0
6.0
Unit : ns
F6
7.5
7.5
7.5
FB
7.5
7.5
7.5
F5
F6
F5
6.0
6.0
6.0
tCK max@CL=4
tCK max@CL=5
tCK max@CL=6
7.5
7.5
7.5
6.0
6.0
6.0
- Changed AC test load picture
Version 0.3 (Nov. 2003)
- Changed Packge type from die-exposed to full molded
- Changed Package code in Partnumber
- 2 -
REV. 0.7 Jan. 2005
K4C89183AF
Version 0.31 (Mar., 2004)
- Corrected typo. in page 7 (Changed operating Temperature to 85’C, case temperature)
Version 0.4 (Jun., 2004)
- Changed from "target" to "Preliminary"
- Changed min. tCK@CL5 to 3.5ns in "-F6"
From
F6
To
F6
CL = 4
CL = 5
CL = 6
4.0 ns
3.33 ns
3.0ns
4.0 ns
3.5 ns
3.0ns
t
CK Clock Cycle Time (min)
Version 0.5 (Aug., 2004)
- Deleted self-refresh function and BL2 from spec
Version 0.51 (Aug., 2004)
- Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing)
Version 0.6 (Nov., 2004)
- Deleted "preliminary"
- Changed current value in page 9
Version 0.7 (Jan., 2005)
- Deleted the tDQSQA in page 11
- Deleted the tSSK in page 11
- 3 -
REV. 0.7 Jan. 2005
K4C89183AF
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as
4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper-
ate fast core cycle compared with regular DDR SDRAM.
K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
K4C89183AF
Parameter
F6
FB
F5
CL = 4
CL = 5
CL = 6
4.0 ns
3.5 ns
3.0ns
20.0 ns
4.5 ns
3.75 ns
3.33 ns
22.5 ns
5.0 ns
4.5 ns
4.0 ns
25 ns
t
CK Clock Cycle Time (min)
tRC Random Read/Write Cycle Time (min)
tRAC Random Access Time (min)
20.0 ns
320mA
70mA
22.5 ns
300mA
65mA
25 ns
280mA
60mA
IDD1S Operating Current (single bank) (max)
IDD2P Power Down Current (max)
•
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
•
- Data : 666 Mbps/pin maximum
•
•
•
•
•
•
•
•
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional Data Strobe
Distributed Auto-Refresh cycle in 3.9us
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 4
•
•
Organization : 4,194,304 words x 4 banks x 18 bits
Power Supply Voltage VDD : 2.5V ± 0.125V
•
VDDQ : 1.4V ∼ 1.9V
•
•
•
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
- 4 -
REV. 0.7 Jan. 2005
K4C89183AF
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
Pin Names
Pin
Name
Address Input
Bank Address
x18
A0 ~ A14
BA0, BA1
DQ0 ~ DQ17
CS
1
2
3
4
5
6
Index
Data Input/Output
Chip Select
Vss
DQ17
DQ0
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
DQ8
A14
A13
NC
A
B
C
D
E
F
FN
Function Control
Power Down Control
Clock Input
DQ16
Vss
Q
VDDQ
PD
CLK, CLK
DS/QS
VDD
DQ15 VDD
Q
VssQ
Write/Read data strobe
Power (+2.5V)
Ground
DQ14 DQ13
DQ4
VSS
DQ12
DQ11
DQ10
DQ9
VREF
CLK
A12
Vss
Q
VDDQ
VDDQ
Power (+1.8V)
(for I/O buffer)
VDD
Q
VssQ
VSSQ
Ground
(for I/O buffer)
G
H
J
Vss
Q
VDDQ
VREF
NC
Reference Voltage
No Connection
DS
Vss
CLK
PD
A9
QS
VDD
FN
K
L
CS
BA1
A0
M
N
P
R
A11
BA0
A10
A1
A8
A7
A5
A6
A2
VSS
A4
A3
VDD
- 5 -
REV. 0.7 Jan. 2005
K4C89183AF
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
To Each Block
BANK #3
BANK #2
BANK #1
BANK #0
CONTROL
SIGNAL
CS
FN
COMMAND
DECODER
GENERATOR
MEMORY
CELL
ARRAY
MODE
REGISTER
ADDRESS
BUFFER
A0 ~ A14
BA0, BA1
UPPER ADDRESS
LATCH
COLUMN DECODER
LOWER ADDRESS
LATCH
REFRESH
COUNTER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
WRITE ADDRESS
BURST
COUNTER
LATCH
ADDRESS
COMPARATOR
DS
QS
DQ BUFFER
DQ0 ~ DQ17
Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17.
- 6 -
REV. 0.7 Jan. 2005
K4C89183AF
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Power Supply Voltage
Power Supply Voltage (for I/O buffer)
Input Voltage
-0.3 ~ 3.3
V
VDDQ
VIN
-0.3 ~ VDD + 0.3
-0.3 ~ VDD + 0.3
-0.3 ~ VDDQ + 0.3
-0.3 ~ VDDQ + 0.3
0 ~ 85
V
V
VOUT
VREF
TOPR
TSTG
TSOLDER
PD
DQ pin Voltage
V
Input Reference Voltage
Operating Temperature
Storage Temperature
V
OC
OC
OC
W
mA
Case Temp.
-55 ~ 150
260
Soldering Temperature(10s)
Power Dissipation
2
IOUT
Short Circuit Output Current
± 50
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-
cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1) (Tcase = 0 ~ 85 OC)
Symbol
Parameter
Min
Typ
Max
Units Notes
VDD
Power Supply Voltage
2.375
2.5
2.625
V
VDDQ
VREF
Power Supply Voltage (for I/O Buffer)
Input Reference Voltage
Input DC high Voltage
1.7
VDDQ/2x95%
VREF+0.125
-0.1
1.8
1.9
V
VDDQ/2
VDDQ/2x105%
VDDQ+0.2
V
V
V
V
V
V
V
V
V
V
2
VIH (DC)
VIL(DC)
-
-
-
-
-
-
-
-
-
5
Input DC Low Voltage
VREF-0.125
VDDQ+0.1
5
VICK (DC) Differential Clock DC Input Voltage
-0.1
10
V
ID (DC)
VIH (AC)
IL (AC)
ID (AC)
VX (AC)
Input Differential Voltage. CLK and CLK Inputs (DC)
Input AC High Voltage
0.4
VDDQ+0.2
7,10
3,6
4,6
7,10
8,10
9,10
VREF+0.2
-0.1
VDDQ+0.2
V
Input AC Low Voltage
VREF-0.2
V
Input Differential Voltage. CLK and CLK Inputs (AC)
Differential AC Input Cross Point Voltage
0.55
VDDQ+0.2
VDDQ/2-0.125
VDDQ/2-0.125
VDDQ/2+0.125
VDDQ/2+0.125
V
ISO (AC) Differential Clock AC Middle Level
- 7 -
REV. 0.7 Jan. 2005
K4C89183AF
1. All voltages are referenced to Vss, VssQ.
Notes:
2. VREF is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC).
3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns
5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.
6. VIH(AC) and VIL(AC) are levels to change to the new logic state.
7. VID is magnitude of the difference between CLK input level and CLK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. VISO means [VICK(CLK) + VICK(CLK)]/2
10. Refer to the figure below.
CLK
VX
VX
VX
VX
VX
VID(AC)
CLK
VICK
VICK
VICK
VICK
VSS
VID(AC)
0 V Differential
VISO
VISO(min)
VISO(max)
VSS
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V.
o
Pin Capacitance (V = 2.5V, V
= 1.8V, f = 1 MHz, Ta = 25 C)
DD
DDQ
Symbol
Parameter
Min
1.5
1.5
2.5
-
Max
3.0
3.0
3.5
1.5
Delts
0.25
0.25
0.5
Units
pF
CIN
CINC
CI/O
CNC
Input Pin Capacitance
Clock Pin (CLK, CLK) Capacitance
DQ, DS, QS Capacitance
NC Pin Capacitance
pF
pF
-
pF
Note : These parameters are periodically sampled and not 100% tested.
- 8 -
REV. 0.7 Jan. 2005
K4C89183AF
DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)
Max
Parameter
Symbol
Units Notes
F6
FB
F5
Operating Current
One bank Read or Write operation;
CK = min, IRC = min, IOUT = 0mA;
t
Burst Length = 4, CAS Latency = 6, Free running QS mode;
IDD1S
320
300
280
1, 2
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
Address inputs change up to 2 times during minimum IRC
Read data change twice per clock cycle
,
Standby Current
All Banks : inactive state;
t
CK=min, CS = VIH, PD = VIH;
IDD2N
100
95
65
90
60
1
1
0V ≤ VIN ≤ VIL(AC)(max.), VIH(AC)(min.) ≤ VIH ≤ VDDQ;
Other input signals change one time during 4*tCK,
DQ and DS inputs change twice per clock cycle
Standby (Power Down) Current
All Banks : inactive state;
t
CK=min, PD = VIL (Power Down);
CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC)(max), VIH(AC)(min) ≤ VIN ≤ VDDQ
IDD2P
70
;
Other input signals change one time during 4*tCK
DQ and DS inputs are floating(VDDQ/2)
,
mA
Write Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
CK = min, IRC = min;
t
IDD4W
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
650
650
600
600
550
550
1
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
Read Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
t
CK = min, IRC = min, IOUT = 0mA;
IDD4R
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
1,2
1,3
Address inputs change once per clock cycle,
Read data change twice per clock cycle
Burst Auto-Refresh Current
Refresh command at every IREFC interval;
t
CK = min, IREFC= min;
IDD5B
CAS Latency = 6, Free running QS mode;
250
235
210
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC) (min.) ≤ VIN ≤ VDDQ;
Address change up to 2 times during minimum IREFC
,
DQ and DS inputs change twice per clock cycle
- 9 -
REV. 0.7 Jan. 2005
K4C89183AF
DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)
Parameter
Symbol
Min
Max
Unit
Notes
Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V)
ILI
-5
5
5
5
-
uA
Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ)
VREF Current
ILO
-5
uA
IREF
-5
uA
VOH = 1.420V
Normal Output
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
-5.6
5.6
-9.8
9.8
-2.8
2.8
-4
4
4
4
4
4
Driver
VOL = 0.280V
VOH = 1.420V
VOL = 0.280V
VOH = 1.420V
VOL = 0.280V
OH = VDDQ - 0.4
VOL = 0.4V
-
-
Output DC Current
(VDDQ = 1.7 ~ 1.9V)
Strong Output
Driver
mA
-
-
Weak Output
Driver
-
V
-
3
3
3
3
Normal Output
Driver
-4
-
VOH = VDDQ - 0.4
VOL = 0.4V
-8
-
Output DC Current
(VDDQ = 1.4 ~ 1.6V)
Strong Output
Driver
mA
-8
-
Not defined
-
-
Weak Output
Driver
Not defined
-
-
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
CK, tRC and IRC
t
.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification
4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
- 10 -
REV. 0.7 Jan. 2005
K4C89183AF
AC Characteristics and Operating Conditions (Notes : 1, 2)
F6
FB
F5
Symbol
Parameter
Units Notes
Min
20.0
4.0
Max
-
Min
22.5
4.5
Max
-
Min
25
Max
-
t
Random Cycle Time
3
3
3
3
3
RC
CK
CL = 4
6.0
6.0
6.0
20.0
6.0
6.0
6.0
22.5
5.0
6.0
6.0
6.0
25
t
C
C
L = 5
L = 6
Clock Cycle Time
3.33
3.0
3.75
3.33
-
4.5
4.0
t
t
t
t
t
t
t
Random Access Time
-
-
RAC
CH
0.45*tCK
0.45*tCK
0.45*tCK
Clock High Time
-
-
-
-
3
3
0.45*tCK
-0.45
-
0.45*tCK
-0.45
-
0.45*tCK
-0.5
-
Clock Low Time
-
-
CL
QS Access Time from CLK
Data Output Skew from QS
Data Access Time from CLK
Data Output Hold Time from CLK
0.45
0.2
0.5
0.5
0.45
0.25
0.5
0.5
0.5
0.3
0.6
0.6
3, 8
4
CKQS
QSQ
AC
-0.5
-0.5
-0.6
-0.6
3, 8
3, 8
-0.5
-0.5
OH
min(tCH
,
min(tCH
,
min(tCH,
t
CLK half period ( minium of Actual tCH, tCL)
-
-
-
3
HP
tCL)
tCL)
tCL
)
t
t
t
t
-t
t
t
-t
t
t
-t
QS(Read) Pulse Width
-
-
-
4, 8
4, 8
QSP
HP QHS
HP QHS
HP QHS
-t
-t
-t
Data Output Valid Time from QS
-
-
-
QSQV
HP QHS
HP QHS
HP QHS
0.055x
+0.17
CK
0.055x
0.055x
+0.17
CK
t
DQ, QS Hold skew factor
-
-
-
QHS
t
t
+0.17
t
CK
t
t
t
t
t
0.8*tCK
0.4*tCK
1.2*tCK
0.8*tCK
0.4*tCK
1.2*tCK
0.8*tCK
0.4*tCK
1.2*tCK
DS(Write) Low to High Setup Time
DS(Write) Preamble Pulse Width
DS First Input Setup Time
3
DQSS
ns
-
-
-
-
-
-
-
-
-
4
3
3
DSPRE
DSPRES
DSPREH
DSP
0
0
0
0.3*tCK
0.3*tCK
0.3*tCK
DS First Low Input Hold Time
DS High or Low Input Pulse Width
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
4
C
C
L = 4
L = 5
0.75
0.75
-
-
-
-
-
-
-
-
-
-
0.8
0.8
-
-
-
-
1.0
1.0
-
-
-
-
-
-
-
3, 4
3, 4
3, 4
3, 4
4
DS Input Falling Edge to Clock Setup
Time
t
t
t
DSS
CL = 6
L = 7
0.75
0.8
1.0
C
-
-
-
0.45*tCK
0.45*tCK
0.45*tCK
DS(Write) Postamble Pulse Width
DS(Write) Postamble Hold Time
DSPST
DSPSTH
CL = 4
L = 5
CL = 6
L = 7
0.75
0.75
0.75
-
0.8
0.8
0.8
-
-
-
-
-
-
1.0
1.0
1.0
-
3, 4
3, 4
3, 4
3, 4
4
C
C
-
-
-
-
-
t
t
t
t
Data Input Setup Time from DS
Data Input Hold Time from DS
0.3
0.35
0.4
DS
DH
IS
0.3
0.6
0.6
-
-
-
0.35
0.6
-
-
-
0.4
0.7
0.7
4
3
3
Command / Address Input Setup Time
Command / Address Input Hold Time
0.6
IH
- 11 -
REV. 0.7 Jan. 2005
K4C89183AF
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
F6
FB
F5
Symbol
Parameter
Units Notes
Min
-0.5
-
Max
Min
-0.5
-
Max
Min
-0.6
-
Max
t
Data-out Low Impedance Time from CLK
Data-out High Impedance Time from CLK
Last Output to PD High Hold Time
Power Down Exit Time
-
0.5
-
-
0.5
-
-
0.6
-
3, 6, 8
3, 7, 8
LZ
t
HZ
t
0
0
0
QPDH
t
0.6
-
0.6
-
0.7
-
3
3
PDEX
t
Input Transition Time
0.1
1
0.1
1
0.1
1
T
t
-0.5*tCK
-0.5*tCK
-0.5*tCK
PD Low Input Window for Self-Refresh Entry
Auto-Refresh Average Interval
Pause Time after Power-up
5
5
5
FPDL
t
0.4
3.9
0.4
3.9
0.4
3.9
5
REFI
us
t
200
5
-
-
-
-
-
200
5
-
-
-
-
-
200
5
-
-
-
-
-
PAUSE
CL = 4
C
C
C
L = 5
L = 6
L = 7
Random Read/Write Cycle Time
(Applicable to Same Bank)
6
6
6
I
I
I
RC
7
7
7
-
-
-
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
1
1
1
1
1
1
RCD
RAS
CL = 4
4
5
6
-
-
-
-
-
4
5
6
-
-
-
-
-
4
5
6
-
-
-
-
-
C
C
L = 5
L = 6
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
CL = 7
Random Bank Access Delay
(Applicable to Other Bank)
I
I
I
2
3
1
-
-
-
2
3
1
-
-
-
2
3
1
-
-
-
RBD
RWD
WRD
LAL following RDA to WRA Delay
(Applicable to Other Bank)
BL = 4
CL = 4
LAL following WRA to RDA Delay
(Applicable to Other Bank)
Cycle
7
7
7
-
-
-
7
7
7
-
-
-
7
7
7
-
-
-
C
C
C
L = 5
L = 6
L = 7
I
Mode Register Set Cycle Time
RSC
I
I
PD Low to Inactive State of Input Buffer
PD High to Active State of Input Buffer
-
2
-
2
-
2
PD
1
-
-
-
-
1
-
-
-
-
1
-
-
-
-
PDA
CL = 4
19
23
25
19
23
25
19
23
25
C
C
L = 5
L = 6
Power down mode valid from REF com-
mand
I
PDV
CL = 7
CL = 4
19
23
25
-
-
-
19
23
25
-
-
-
19
23
25
-
-
-
C
C
C
L = 5
L = 6
L = 7
I
I
Auto-Refresh Cycle Time
REFC
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
LOCK
- 12 -
REV. 0.7 Jan. 2005
K4C89183AF
AC Test Conditions
Symbol
Parameter
Input high voltage (minimum)
Value
Units
V
Notes
VIH(min)
VIL (max)
VREF
VREF + 0.2
VREF - 0.2
Input low voltage (maximum)
Input reference voltage
V
VddQ/2
VREF
V
VTT
Termination voltage
V
VSWING
VR
Input signal peak to peak swing
Differential clock input reference level
Input differential voltage
0.7
V
VX(AC)
V
VID(AC)
1.0
2.5
V
SLEW
VOTR
Input signal minimum slew rate
Output timing measurement reference voltage
V/ns
V
VddQ/2
9
VddQ
VTT
VIH min(AC)
25 Ω
VSWING
VREF
Output
VIL max(AC)
Measurement Point
Vss
∆T
∆T
AC Test Load
Slew=(VIHmin(AC) - VILmax(AC))/∆T
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to tCK contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.
4. These parameters are measured from signal transition point of DS crossing VREF level.
5. The tREFI (MAX.) applies to equally distributed refresh method.
The tREFI (MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength at VDDQ = 1.7V ~ 1.9V.
Output timing is measured by using Strong driver strength at VDDQ = 1.4V ~ 1.6V
- 13 -
REV. 0.7 Jan. 2005
K4C89183AF
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply VDD before or at the same time as VDDQ
.
3. Apply VDDQ before or at the same time as VREF
.
4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
2.5V(TYP)
V
DD
1.8V(TYP)
0.9V(TYP)
V
DDQ
V
REF
CLK
CLK
t
PDEX
I
l
l
l
l
REFC
PDA
RSC
RSC
REFC
200 µs(min)
PD
200 clock cycle(min)
Command
Address
DQ
DESL
RDA MRS DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF DESL
op-code
EMRS
MRS
DS
Hi-Z
QS
Low
(Uni-QS mode)
QS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
- 14 -
REV. 0.7 Jan. 2005
K4C89183AF
Basic Timing Diagrams
Input Timing
tCK
Command and Address
tCH
tCL
tCK
CK
CK
tIS
tIH
tIS
tIS
tIS
tIH
1st
2nd
2nd
LA
CS
FN
tIPW
tIH
tIH
tIS
1st
tIPW
tIH
tIS
tIH
A0-A14
BA0.BA1
UA, BA
Data
DS
tDS
tDH
tDS
tDH
DQn (Input)
DQm (Input)
tDS
tDH
tDS
tDH
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH(AC)
CLK
VIL(AC)
CLK
VIL
tT
tT
tCK
VIH
VIL
CLK
CLK
VID(AC)
VX
VX
VX
- 15 -
REV. 0.7 Jan. 2005
K4C89183AF
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
LDS/UDS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 4
LQS/UQS
(Output)
Low
Low
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 5
LQS/UQS
(Output)
Low
Low
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 6
LQS/UQS
(Output)
Low
Low
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
Note : DQ0 to DQ17 are aligned with LQS.
DQ18 to DQ35 are aligned with UQS.
- 16 -
REV. 0.7 Jan. 2005
K4C89183AF
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
LDS/UDS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 4
LQS/UQS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 5
LQS/UQS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 6
LQS/UQS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
Note : DQ0 to DQ17 are aligned with LQS.
DQ18 to DQ35 are aligned with UQS.
LQS/UQS is always asserted in Free Running QS mode.
- 17 -
REV. 0.7 Jan. 2005
K4C89183AF
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
tDSPSTH
tDSS
tDSP tDSPST
tDQSS
tDSPRES
tDSPREH
tDSP
tDSP
CAS latency = 4
LDS/UDS
(Input)
tDSS
tDS
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
Q2
tDH
tDH
Q3
DQ
Q0
Q1
(Input)
tDSS
tDQSS
tDSPRES
tDSPREH
tDSPSTH
tDSS
tDSP
tDSP
tDSP tDSPST
CAS latency = 5
LDS/UDS
(Input)
Preamble
Postamble
tDSPRE
tDS
tDS
tDS
tDH
Q0
tDH
Q2
tDH
Q3
DQ
Q1
(Input)
tDSS
tDQSS
tDSPRES
tDSPSTH
tDSS
tDSP
tDSP
tDSP tDSPST
tDSPREH
CAS latency = 6
LDS/UDS
(Input)
Preamble
Postamble
tDSPRE
tDS
tDS
tDS
tDH
Q0
tDH
Q2
tDH
Q3
DQ
Q1
(Input)
LQS/UQS
(Uni-QS)
Low
LQS/UQS
(Free Runninig)
Note : DQ0 to DQ17 are sampled at both edges of LDS.
DQ18 to DQ35 are sampled at both edges of UDS.
- 18 -
REV. 0.7 Jan. 2005
K4C89183AF
t
, t
, Ixxxx Timing
REFI PAUSE
CLK
CLK
tIS
tIH
tREFI, PAUSE, XXXX
t
I
tIS
tIH
Input
Command
Command
(Control &
Addresses)
Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.
- 19 -
REV. 0.7 Jan. 2005
K4C89183AF
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
•The First Command
Symbol
Function
CS
H
FN
X
BA1-BA0
A14-A9
X
A8
X
A7
X
A6-A0
X
DESL Device Deselect
X
RDA
Read with Auto-close
Write with Auto-close
L
H
BA
BA
UA
UA
UA
UA
UA
UA
WRA
L
L
UA
UA
•The Second Command (The next clock of RDA or WRA command)
Symbol
LAL
Function
Lower Address Latch
CS
H
FN
X
BA1-BA0 A14-A13 A12-A11 A10-A9 A8
A7 A6-A0
X
X
V
V
X
L
X
X
L
X
X
L
X
X
L
X
X
V
LA
X
REF
Auto-Refresh
L
X
MRS
Mode Register Set
L
X
V
Notes :1. L=Logic Low,H=Logic High,X=eitherL or H,V=Valid(SpecifiedValue),BA=Bank Address,UA=Upper Address,
LA = Lower Address.
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the
command table below.
Read Command Table
Command (Symbol)
CS
L
FN
H
BA1-BA0
A14-A9
UA
A8
UA
X
A7
UA
X
A6-A0
UA
Notes
RDA (1st)
LAL (2nd)
BA
X
H
X
X
LA
Write Command Table
BA1-
BA0
A10~
Command (Symbol)
CS
FN
A14
A13
UA
A12
A11
A8
A7 A6-A0
A9
UA
X
WRA (1st)
LAL (2nd)
L
L
BA
X
UA
UA
X
UA
X
UA
X
UA
X
UA
LA
H
X
VW0 VW1
Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Function
Reserved
VW0
VW1
L
H
L
L
L
Write All Words
Write First Two Words
Write First One Word
BL = 4
H
H
H
- 20 -
REV. 0.7 Jan. 2005
K4C89183AF
Function Truth Table (Continued)
Mode Register Set Command Truth Table
Command (Symbol)
RDA (1st)
CS
L
FN
H
BA1-BA0
A14-A9
A8
X
A7
X
A6-A0
Notes
X
V
X
L
X
V
MRS (2nd)
L
X
L
V
6
Note : 6. Refer to "Mode Register Table".
Auto-Refresh Command Table
PD
Command
(Symbol)
Current
State
Function
CS
n
FN BA1-BA0 A14-A9
A8
A7
A6-A0 Notes
n-1
H
Active
Auto-Refresh
WRA(1st)
REF(2nd)
Standby
Active
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
H
X
Power Down Table
PD
Command
(Symbol)
Current
State
BA1-
BA0
Function
CS FN
A14-A9 A8
A7 A6-A0 Notes
n-1
n
L
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
-
Standby
H
L
L
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
9
Power Down
Power Down
L
PDEX
H
Notes : 7. PD has to be brought to Low within tFPDL from REF command.
8. PD should be brought to Low after DQ’s state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
- 21 -
REV. 0.7 Jan. 2005
K4C89183AF
Function Truth Table (Continued)
PD
Current State
CS
FN
Address
Command
Action
Notes
n-1
H
H
H
H
H
L
n
H
H
H
L
H
L
X
H
L
X
DESL
RDA
WRA
PDEN
-
NOP
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
L
BA, UA
Idle
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
10
L
X
X
H
H
L
X
H
L
X
-
Refer to Power Down state
Begin read
H
H
H
H
L
LA
LAL
Op-Code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
H
L
X
L
X
X
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
L
LA
LAL
Begin Write
Auto-Refresh
Illegal
X
REF
PDEN
H
L
X
L
X
REF (Self) Self-Refresh entry
X
H
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
H
L
X
DESL
RDA
WRA
PDEN
-
Continue burst read to end
BA, UA
Illegal
11
11
L
BA, UA
Illegal
Read
Write
H
L
X
X
X
X
H
L
X
Illegal
L
X
Illegal
X
H
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
H
L
X
DESL
RDA
WRA
PDEN
-
Data write & continue burst write to end
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
11
11
L
BA, UA
H
L
X
X
X
X
X
X
X
X
L
X
H
X
H
-
H
DESL
NOP-> Idle after I
REFC
H
H
H
H
L
H
H
L
L
L
H
L
BA, UA
RDA
WRA
PDEN
-
Illegal
Illegal
BA, UA
Auto-Refreshing
H
L
X
X
X
X
X
X
X
X
Self-Refresh entry
Illegal
12
L
X
H
X
H
-
Refer to Self-Refreshing state
H
DESL
Nop-> Idle after I
RSC
H
H
H
H
L
H
H
L
L
L
H
L
BA, UA
RDA
Illegal
Illegal
Illegal
Illegal
Invalid
Invalid
BA, UA
WRA
Mode Register Accessing
H
L
X
X
X
X
X
X
X
X
X
X
X
X
PDEN
L
-
X
X
L
X
X
X
H
-
H
L
-
-
Maintain Power Down Mode
Power Down
L
H
RDEX
Exit Power Down Mode->Idle after t
PDEX
L
H
L
X
X
-
Illegal
Notes : 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).
12. Illegal if t is not Stisfied.
FPDL
- 22 -
REV. 0.7 Jan. 2005
K4C89183AF
Mode Register Table
Regular Mode Register (Notes : 1)
Address
BA1*1
BA0*1
A7*3
A14-A8
A6-A4
A3
A2-A0
Register
0
0
0
TM
CL
BT
BL
A7
0
Test Mode (TE)
Regular (Default)
Test Mode Entry
A3
0
Burst Type (BT)
Sequential
1
1
Interleave
A6
A5
A4
CAS Latency (CL)
A2
A1
A0
Burst Length (BL)
Reserved *2
Reserved *2
Reserved *2
0
0
X
0
0
0
Reserved *2
4
0
0
1
1
0
1
0
0
1
Reserved *2
0
0
1
1
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
Reserved *2
X
X
Reserved *2
Extended Mode Register (Notes : 4)
BA1*4
BA0*4
A0*5
Address
A14-A7
A6~A5
A4-A3
A2~A1
DIC(DQ)
Register
0
1
0
SS
DIC(QS)
DS
A6
A5
Strobe Select
Reserved*2
Reserved*2
QS
DQ
A1
0
Output Driver Impedance Control
(DIC)
0
0
A4
0
A3
A2
0
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
0
1
0
0
1
1
1
0
1
Unidirectional DS/QS
1
1
0
Unidirectional DS/Free Running QS
1
1
1
Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0.
2. "Reserved" places in Regular Mode Register should not be set.
A0
0
DLL Switch (DS)
DLL Enable
3. A7 in Regular Mode Register must be set to "0"(Low state).
Because Test Mode is specific mode for supplier.
1
DLL Disable
4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
- 23 -
REV. 0.7 Jan. 2005
K4C89183AF
State Diagram
Power
Down
PDEX
(PD = H)
PDEN
(PD = L)
Standby
(Idle)
PD = H
Auto-
Refresh
Mode
Register
WRA
RDA
REF
MRS
Active
(Restore)
Active
LAL
LAL
Write
(Buffer)
Read
Command Input
Automatic Return
The second command at Active
state must be issued 1clock after
RDA or WRA command input
- 24 -
REV. 0.7 Jan. 2005
K4C89183AF
Timing Diagrams
Single Bank Read Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
RDA
LAL
RDA
LAL
RDA
LAL
RDA
UA
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
CL=4
CL=4
CL=4
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
CL=4
CL=4
CL=4
Hi-Z
DQ
(Output)
Q0
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
- 25 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Read Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
LA
DESL
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
UA
LA
UA
#0
LA
UA
#0
Bank Add.
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
CL=5
CL=5
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
- 26 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Read Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
DESL
lRC=7cycles
DESL
Command
Address
RDA
LAL
RDA
LAL
RDA
LAL
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
UA
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
CL=6
CL=6
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2
- 27 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
WRA
LAL
WRA
LAL
WRA
LAL
WRA
UA
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
WL=3
WL=3
WL=3
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
WL=3
WL=3
WL=3
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
- 28 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
DESL
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
WL=4
WL=4
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
WL=4
WL=4
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
- 29 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
lRC=7cycles
WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
Command
Address
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
WL=5
WL=5
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
WL=5
WL=5
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
- 30 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Read-Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
RDA
UA
LAL
LA
WRA
UA
LAL
LA
RDA
UA
LAL
LA
WRA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
CL=4
WL=3
CL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=4
WL=3
CL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
- 31 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Read-Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
DESL
RDA
UA
LAL
LA
DESL
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
CL=5
WL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=5
WL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
- 32 -
REV. 0.7 Jan. 2005
K4C89183AF
Single Bank Read-Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
lRC=7cycles
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
DESL
RDA
UA
LAL
LA
Command
Address
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
CL=6
WL=5
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=6
WL=5
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
- 33 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Read Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
LAL
LA
RDA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")=5cycles
lRC(Bank"b")=5cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
CL=4
CL=4
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=4
CL=4
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Note : lRC to the same bank must be satisfied
- 34 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Read Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
LAL
LA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=6cycles
lRC(Bank"6")=6cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Note : lRC to the same bank must be satisfied
- 35 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Read Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=7cycles
lRC(Bank"b")=7cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2
Note : lRC to the same bank must be satisfied
- 36 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
LAL
LA
WRA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")=5cycles
lRC(Bank"b")=5cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
WL=3
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=3
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Note : lRC to the same bank must be satisfied
- 37 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
LAL
LA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=6cycles
lRC(Bank"b")=6cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1
Note :IRC to the same bank must be satisfied.
- 38 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=7cycles
lRC(Bank"a")=7cycles
Unidirectional DS/QS mode
DS
(input)
Low
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
Note :IRC to the same bank must be satisfied.
- 39 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Read-Write Timing (BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
LAL
LA
DESL
lRWD=3cycles
WRA
UA
LAL
RDA
LAL
LA
DESL
WRA
UA
LAL
RDA
LAL
LA
Command
lWRD=1cycle
lWRD=1cycle
lRWD=3cycles
lWRD=1cycle
Address
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/QS mode
CL =4
DS
(Input)
Low
QS
(Output)
CL=4
Da0 Da1 Da2 Da3
WL=3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =5
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=5
Da0 Da1 Da2 Da3
WL=4
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =6
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=6
WL=5
DQ
Da0 Da1
Qb0 Qb1 Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Da2 Da3
(Output)
Note :IRC to the same bank must be satisfied.
- 40 -
REV. 0.7 Jan. 2005
K4C89183AF
Multiple Bank Read-Write Timing (BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
LAL
LA
DESL
lRWD=3cycles
WRA
UA
LAL
RDA
LAL
LA
DESL
WRA
UA
LAL
RDA
LAL
LA
Command
lWRD=1cycle
lWRD=1cycle
lRWD=3cycles
lWRD=1cycle
Address
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/Free Running QS mode
CL =4
DS
(Input)
QS
(Output)
CL=4
Da0 Da1 Da2 Da3
WL=3
WL=4
WL=5
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =5
DS
(Input)
QS
(Output)
CL=5
Da0 Da1 Da2 Da3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =6
DS
(Input)
QS
(Output)
CL=6
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1
(Output)
Note :IRC to the same bank must be satisfied.
- 41 -
REV. 0.7 Jan. 2005
K4C89183AF
Write with Variable Write Length (VW) Control(CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL=2, SEQUENTIAL MODE
WRA
LAL
DESL
WRA
UA
LAL
DESL
Command
Address
LA=#3
VW=All
LA=#1
VW=1
UA
VW0 = Low
VW1 = don’t care
VW0 = High
VW1 = don’t care
Bank
"a"
Bank
"a"
Bank Add.
DS
(Input)
DQ
(Input)
D0 D1
D0
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL=4, SEQUENTIAL MODE
WRA
LAL
DESL
WRA
UA
LAL
DESL
WRA
UA
LAL
DESL
Command
LA=#3
VW=All
LA=#1
VW=1
LA=#2
VW=2
UA
Address
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
Bank
"a"
Bank Add.
DS
(Input)
DQ
(Input)
D0 D1 D2 D3
Lower Address #3 #0 #1 #2
D0
D0 D1
#2 #3 (#0) (#1)
#1 (#2) (#3) (#0)
Last three data are masked.
Last two data are masked.
Note : DS input must be continued till end of burst count even if some of laster data is masked.
- 42 -
REV. 0.7 Jan. 2005
K4C89183AF
Power Down Timing (CL=4, BL=4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
BL=2, SEQUENTIAL MODE
RDA
or
RDA
LAL
DESL
DESL
Command
Address
WRA
IPDA
UA
LA
UA
IPD=2 cycle
tIS
tIH
PD
tQPDH
tPDEX
IRC(min), tREFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
CL=4
Hi-Z
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=4
Hi-Z
DC
(Output)
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Power Down Exit
Note :
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
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K4C89183AF
Power Down Timing (CL=4, BL=4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
IPDA
RDA
or
WRA
UA
LAL
LA
DESL
DESL
Command
Address
WRA
UA
IPD=2 cycle
tIS
tIH
PD
tPDEX
IPD=2 cycle
WL=3
IRC(min), tREFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
WL=3
DC
(Output)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=3
DC
(Output)
D0 D1 D2 D3
Note :
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
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K4C89183AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
WRA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
WL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DC
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DC
(input)
D0 D1 D2 D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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K4C89183AF
Extended Mode Register Set Timing (CL=4, BL=4)
From Write operation to Extended Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
WRA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
WL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DQC
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DQ
(input)
D0 D1 D2 D3
Note :
When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
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K4C89183AF
Auto-Refresh Timing (CL=4, BL=4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
n-1
n
n+1
n+2
CLK
CLK
lRC=5cycles
lREFC=19cycles
DESL
RDA
or
LAL or
MRS or
REF
RDA
LAL
LA
DESL
WRA
REF
Command
WRA
Bank,
UA
Bank, Address
lRCD=1cycle
Low
lRAS=4cycles
lRCD=1cycle
QS
(output)
Low
CL=4
Hi-Z
Hi-Z
DQ
(output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
CLK
CLK
lRC=5cycles
lREFC=19cycles
RDA
or
LAL or
MRS or
REF
RDA
LAL
LA
DESL
WRA
REF
DESL
Command
WRA
Bank,
UA
Bank, Address
lRCD=1cycles
lRAS=4cycles
lRCD=1cycles
QS
(output)
CL=4
Hi-Z
Hi-Z
DQ
(output)
Q0 Q1 Q2 Q3
Note :
In case of CL=4, IREFC must be meet 19 clock cycles.
When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command
specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
t1+t2+t3+t4+t5+t6+t7+t8
8
Total time of 8 Refresh cycle
8
tREFI
=
=
t
REFI is specified to avoid partly concentrated current of Refresh operation that is acivated
larger are than Read/Write operation.
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K4C89183AF
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM.
Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all
address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output
data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK
signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).
BA0
0
BA1
0
Bank #0
Bank #1
Bank #2
Bank #3
1
0
0
1
1
1
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address
Lower Address
K4C89183AF
A0 to A14
A0 to A6
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K4C89183AF
Functional Description (Continued)
Data Input/Output : DQ0 ~ DQ17
The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal.
The output data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal.
Data Strobe : DS or QS
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS/QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low"
level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS/Free running QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe
type is easy to use for pin to pin connect application.
Power Supply : V , V
, V , V
SS SSQ
DD
VDD and VSS are supply pins for memory core and peripheral circuits.
DDQ and VSSQ are power supply pins for the output buffer.
DDQ
V
Reference Voltage : V
REF
VREF is reference voltage for all input signals.
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K4C89183AF
Command Functions and Operations
K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation
mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after IRC
.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be
asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-
ically to the idle state after IRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to
the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In
a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of
the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is
specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-
uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random
distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,
the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Power Down Mode( PD="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting
PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,
the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued
for IPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the
RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended
Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read
or write cycle. The Regular Mode Register has four function fields.
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K4C89183AF
The four fields are as follows :
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by
another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-
fined, therefore the Mode Register Set command must be issued before proper operation.
• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
0
A14~A0
0
0
1
Regular MRS cycle
Extended MRS cycle
Reserved
1
X
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 4 words.
A2
0
A1
0
A0
0
Burst Length
Reserved
Reserved
4 words
0
0
1
0
1
0
0
1
1
Reserved
Reserved
1
X
X
(R-2) Burst Type field (A3)
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is
selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3
0
Burst Type
Sequential
Interleave
1
• Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower address input to
the device.
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K4C89183AF
CAS Latency = 4 (Free Running QS mode)
CK
CK
Command
QS
RDA
LAL
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Access Address
Burst Length
Data 0
Data 1
Data 2
Data 3
n
n + 1
n + 2
n + 3
4 words(Address bits is LA1, LA0)
not carried from LA1~LA2
Functional Description (Continued)
• Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
Data
Access Address
Burst Length
Data 0
Data 1
Data 2
Data 3
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Addressing sequence for Interleave mode
A6
0
A5
0
A4
0
CAS Latency
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
5
6
7
1
0
1
1
1
0
1
1
1
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K4C89183AF
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
Extended Mode Register Fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver
Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
QS
DQ
Output Driver Impedance Control
A4
0
A3
0
A2
0
A1
0
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Reserved
0
1
0
1
1
0
1
0
1
1
1
1
(E-3) Strobe Select (A6/A5)
Two types of strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always clocking
A6
0
A5
0
Strobe Select
Reserved
0
1
Reserved
1
0
Unidirectional DS/QS mode
Unidirectional DS/Free running QS mode
1
1
(E-4)Reserved fied (A7 to A14)
These bits are reserved for future operations and must be set to "0" for normal operation.
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K4C89183AF
Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm)
10.50
± 0.10
#A1
1.00 x 5 = 5.00
2.50
#A1 Mark (Option)
1.50
1.50
Window Mold Area
1.00
1
2
6
5
3
4
10.50
± 0.10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
60 -
∅0.45 solder ball
0.35
1.10
± 0.05
TOP VIEW
±
0.10
BOTTOM VIEW
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REV. 0.7 Jan. 2005
K4C89183AF
General Information
Organization
288M(x9)
F6 (667Mbps@CL6)
FB (600Mbps@CL6 )
K4C89093AF-ACFB
K4C89183AF-ACFB
K4C89363AF-GCFB
F5 (500Mbps@CL6 )
K4C89093AF-AC(I)F5
K4C89183AF-AC(I)F5
K4C89363AF-GC(I)F5
K4C89093AF-ACF6
K4C89183AF-ACF6
K4C89363AF-GCF6
288M(x18)
288M(x36)
1
2
3
4
5
6
7
8
9
10 11
K 4 C XX XX X X X - X X XX
Memory
DRAM
Speed
Temperature & Power
Package
Small Classification
Density and Refresh
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
8. Version
F : 7th Generation
2. DRAM : 4
3. Small Classification
C : Network-DRAM
9. Package
A : 60 FBGA
G : 144 FBGA
4. Density & Refresh
89 : 288M 8K/32ms
10. Temperature & Power
C : (Commercial, Normal)
5. Organization
I
: (Industrial, Normal)
08 : x8
09 : x9
16 : x16
18 : x18
11. Speed
F6 : 667Mbps/pin (333MHz, CL=6)
FB :600Mbps/pin (300MHz,CL=6)
F5 : 500Mbps/pin (250MHz, CL=6)
6. Bank
3 : 4 Bank
7. Interface (VDD & VDDQ)
A: SSTL-2(2.5V, 1.8V)
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REV. 0.7 Jan. 2005
相关型号：
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