K3N7C4000B-DC12 [SAMSUNG]
MASK ROM, 4MX16, 120ns, CMOS, PDIP42, 0.600 INCH, DIP-42;型号: | K3N7C4000B-DC12 |
厂家: | SAMSUNG |
描述: | MASK ROM, 4MX16, 120ns, CMOS, PDIP42, 0.600 INCH, DIP-42 有原始数据的样本ROM 光电二极管 内存集成电路 |
文件: | 总3页 (文件大小:44K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3N7C4000B-DC
CMOS MASK ROM
64M-Bit (4Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· 4,194,304 x 16 bit organization
· Fast access time :
100ns(Max.) : CL=50pF
120ns(Max.) : CL=100pF
· Supply voltage : single +5V
· Current consumption
Operating : 70mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The K3N7C4000B-DC is a fully static mask programmable
ROM organized 4,194,304 x 16 bit. It is fabricated using sili-
con-gate CMOS process technology.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor and
data memory, character generator.
The K3N7C4000B-DC is packaged in a 42-DIP.
· Package
-. K3N7C4000B-DC : 42-DIP-600
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
X
A21
A18
1
2
42
41
40
A19
A8
MEMORY CELL
MATRIX
(4,194,304x16)
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
A17
A7
3
A9
A6
A5
A4
A3
4
39 A10
38 A11
5
6
A12
37
36
35
34
33
Y
SENSE AMP.
BUFFERS
7
A13
A14
A15
BUFFERS
AND
DECODER
A2
A1
8
A0
9
A0
10
11
12
A16
DIP
A21
VSS
32 A20
.
. .
VSS
Q15
Q7
31
30
29
28
27
13
14
15
16
17
18
19
20
OE
Q0
Q0
Q15
CONTROL
LOGIC
OE
Q8
Q1
Q9
Q14
Q6
26 Q13
Q2
Q10
Q3
Q5
25
24
23
Q12
Q4
Pin Name
A0 - A21
Q0 - Q15
OE
Pin Function
Address Inputs
Q11
21
22 VCC
Data Outputs
Output Enable
Power (+5V)
Ground
K3N7C4000B-DC
VCC
VSS
K3N7C4000B-DC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +7.0
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Min
4.5
0
Symbol
VCC
Typ
5.0
0
Max
5.5
0
Unit
V
Supply Voltage
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
Unit
Operating Current
ICC
-
70
mA
OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
Input Leakage Current
ILI
ILO
VIN=0 to VCC
-
-
10
10
mA
mA
V
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
VOUT=0 to VCC
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
-
V
VOH
VOL
IOH=-400mA
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
OE
Mode
Data
High-Z
Dout
Power
Active
Active
H
L
Operating
Operating
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
COUT
CIN
-
-
pF
pF
VIN=0V
12
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N7C4000B-DC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
K3N7C4000B-DC10
(CL=50pF)
K3N7C4000B-DC12
(CL=100pF)
K3N4C1000B-DC15
(CL=100pF)
Item
Symbol
Unit
Min
Max
Min
Max
Min
150
Max
Read Cycle Time
tRC
tAA
tOE
100
120
ns
ns
ns
Address Access Time
Output Enable Access Time
100
50
120
60
150
70
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A21
tRC
tDF(Note)
tAA
tOE
OE
tOH
DOUT
D0~D15
VALID DATA
VALID DATA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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