K1S3216B1C [SAMSUNG]
2Mx16 bit Uni-Transistor Random Access Memory; 2Mx16位的Uni-晶体管随机存取存储器
| 型号： | K1S3216B1C |
| 厂家： | 
SAMSUNG |
| 描述： | 2Mx16 bit Uni-Transistor Random Access Memory |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
K1S3216B1C
UtRAM
Document Title
2Mx16 bit Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
January 16, 2003
Advanced
0.1
Revised
June 9, 2003
Preliminary
- Changed Package Type from 48 TBGA into 48 FBGA 6.0 x 8.0
- Changed Standby Current(CMOS) from 80uA to 100uA
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.1
June 2003
- 1 -
Preliminary
K1S3216B1C
UtRAM
2M x 16 bit Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: CMOS
· Organization: 2M x16 bit
The K1S3216B1C is fabricated by SAMSUNG¢s advanced
CMOS technology using one transistor memory cell. The device
supports Industrial temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports dual chip selection for user interface.
· Power Supply Voltage: 1.7V~2.1V
· Three State Outputs
· Compatible with Low Power SRAM
· Dual Chip selection support
· Package Type: 48-FBGA-6.0x8.0
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temp.
Vcc Range
Speed
PKG Type
Standby
Operating
(ISB1, Max.)
(ICC2, Max.)
K1S3216B1C-I
Industrial(-40~85°C)
1.7V~2.1V
70/85ns
100mA
30mA
48-FBGA-6.0x8.0
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CS2
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
A20
Vcc
Vss
I/O9
I/O10
Vss
CS1
I/O2
I/O4
I/O5
I/O6
WE
Row
select
Row
Addresses
Memory array
I/O11
I/O12
I/O13
I/O14
A19
A5
A6
A17
NC
A14
A12
A9
A7
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Vcc
A16
A15
A13
A10
Data
cont
I/O9~I/O16
I/O15
I/O16
A18
Data
cont
Column Addresses
G
H
A8
A11
CS1
CS2
OE
WE
UB
48-FBGA: Top View(Ball Down)
Control Logic
LB
Name
Function
Name
Vcc
Vss
UB
Function
CS1,CS2 Chip Select Inputs
Power
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
Ground
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
No Connection1)
A0~A20
LB
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future use.
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 0.1
June 2003
- 2 -
Preliminary
K1S3216B1C
UtRAM
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200ms with CS1=high.or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
Min. 200ms
VCC(Min)
VCC
CS1
CS2
Power Up Mode
Normal Operation
POWER UP(1)
1. After VCC reaches VCC(Min.), wait 200ms with CS1 high. Then the device gets into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
Min. 200ms
VCC(Min)
VCC
CS1
CS2
Power Up Mode
Normal Operation
POWER UP(2)
1. After VCC reaches VCC(Min.), wait 200ms with CS2 low. Then the device gets into the normal operation.
Revision 0.1
June 2003
- 3 -
Preliminary
K1S3216B1C
UtRAM
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
X1)
L
Deselected
Deselected
X1)
H
H
H
H
H
H
H
H
Deselected
X1)
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
Active
L
L
H
H
Active
L
L
H
H
L
High-Z
Dout
Active
L
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
High-Z
Din
Active
L
L
L
L
Din
Active
1. X means don¢t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
Revision 0.1
June 2003
- 4 -
Preliminary
K1S3216B1C
UtRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K1S3216B1C-FI70
K1S3216B1C-FI85
48-FBGA, 70ns, 1.8V/2.0V
48-FBGA, 85ns, 1.8V/2.0V
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
1.7
0
Typ
Max
2.1
Unit
V
Supply voltage
Ground
1.8/2.0
Vss
0
-
0
V
VCC+0.22)
0.4
Input high voltage
Input low voltage
VIH
1.4
-0.23)
V
VIL
-
V
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width £20ns.
3. Undershoot: -1.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Symbol
Item
Test Conditions
Min
-1
Max Unit
Typ
Input leakage current
ILI
VIN=Vss to Vcc
-
1
1
mA
mA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,
VIO=Vss to Vcc
Output leakage current
ILO
-1
-
-
-
-
Cycle time=1ms, 100% duty, IIO=0mA, CS1£0.2V, LB£0.2V
or/and UB£0.2V, CS2³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
5
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH
LB=VIL or/and UB=VIL, VIN=VIH or VIL
-
30
Output low voltage
Output high voltage
VOL IOL = 0.1mA
VOH IOH = -0.1mA
-
-
-
0.2
-
V
V
1.4
Other inputs=0~Vcc
Standby Current(CMOS)
ISB1
-
-
100 mA
1) CS1³ VCC-0.2V, CS2³ VCC-0.2V(CS1 controlled) or
2) 0V £ CS2 £ 0.2V(CS2 controlled)
Revision 0.1
June 2003
- 5 -
Preliminary
K1S3216B1C
UtRAM
AC OPERATING CONDITIONS
Dout
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
Input rising and falling time: 5ns
CL
Input and output reference voltage: 0.5 x VCC
Output load (See right): CL=50pF
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=1.7~2.1V, TA=-40 to 85°C)
Speed Bins
85ns
Parameter List
Symbol
Units
70ns
Min
70
-
Max
Min
85
-
Max
Read Cycle Time
tRC
tAA
-
70
70
35
70
-
-
85
85
40
85
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
25
25
25
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
5
5
70
60
0
-
85
70
0
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
60
60
551)
0
-
70
70
601)
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
25
-
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
0
35
0
-
-
5
-
5
-
1. tWP(min)=70ns for continuous write operation over 50 times.
Revision 0.1
June 2003
- 6 -
Preliminary
K1S3216B1C
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
Revision 0.1
June 2003
- 7 -
Preliminary
K1S3216B1C
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
tAW
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 0.1
June 2003
- 8 -
Preliminary
K1S3216B1C
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
tAW
CS1
CS2
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
CS1
tWR(4)
tCW(2)
tAW
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
Revision 0.1
June 2003
- 9 -
Preliminary
K1S3216B1C
UtRAM
Unit: millimeters
PACKAGE DIMENSION
48 FINE PITCH BALL GRID ARRAY(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
6.00
3.75
8.00
5.25
0.45
0.90
0.55
0.35
-
Max
-
A
B
-
Notes.
5.90
6.10
-
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are ±0.050 unless
specified beside figures.
B1
C
-
7.90
8.10
-
C1
D
-
4. Typ : Typical
0.40
0.50
1.00
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.30
-
0.40
0.08
Revision 0.1
June 2003
- 10 -
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