ML9058E_技术文档

FEDL9058E-01

Issue Date: April. 13, 2007

LAPIS Semiconductor

ML9058E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

GENERAL DESCRIPTION

The ML9058E is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot

matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).

Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the

ML9058E makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips.

Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is

possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip,

it is possible to construct a graphic display system with a maximum of 65  132 dots. The display can be expanded

further using two chips. However, the ML9058E is not used in a multiple chip configuration when a line reversal

drive is set.

The ML9058E is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of

its features, and is therefore suitable for displays in battery-operated portable equipment.

The ML9058E has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of

up to 65  132 dots.

FEATURES

 Direct display of the RAM data using the bit map method

Display RAM data “1” ... Dot is displayed

Display RAM data “0” ... Dot is not displayed (during forward display)

 Display RAM capacity

65  132 = 8580 bits

 LCD Drive circuits

65 common outputs, 132 segment outputs

 MPU interface: Can select an 8-bit parallel or serial interface

 Built-in voltage multiplier circuit for the LCD drive power supply

 Built-in LCD drive voltage adjustment circuit

 Built-in LCD drive bias generator circuit

 Can select frame reversal drive or line reversal drive by command

 Built-in oscillator circuit (Internal RC oscillator/external clock input)

 A variety of commands

Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page

address, set display start address, etc.

 Power supply voltage

Logic power supply: V_DD-V_SS= 3.7 V to 5.5 V

Voltage multiplier reference voltage: V_IN-V_SS= 3.7 V to 5.5 V

(2- to 4-time multiplier available)

LCD Drive voltage: V_BI-V_SS= 6.0 to 18 V

 Package: Gold bump chip (Bump hardness: Low, DV)

: Gold bump chip (Bump hardness: High, CV)

 This device is not resistant to radiation and light.

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ML9058E

BLOCK DIAGRAM

V_DD

V1

V2

V3

V4

COMMON

Drivers

SEGMENT

Drivers

V5

V_SS

Common Output state

selection circuit

Display data latch circuit

VS1–

VS2–

VC3+

VC4+

VC5+

FRS

FR

CL

DOF

Display data RAM

VC6+

V_OUT

M/S

65  132

V_IN

VR

Column address circuit

VRS

IRS

CLS

TEST1

Bus holder

Command decoder

MPU lnterface

Status

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ML9058E

ABSOLUTE MAXIMUM RATINGS

V_SS= 0 V

Parameter

Power supply voltage

Bias voltage

Symbol

V_DD

Condition

Tj = 25°C

Rated value

–0.3 to +6.5

–0.3 to +20

Unit Applicable pins

V

V_DD

V_BI

V1 to V5

Voltage multiplier output

voltage

V_OUT

Tj = 25°C

–0.3 to +20

V

V_OUT

2-time multiplication

3-time multiplication

4-time multiplication

Tj = 25°C

–0.3 to +5.5

–0.3 to +5.0

–0.3 to V_DD+0.3

–55 to +125

Voltage multiplier reference

voltage

V_IN

V

V_IN

Input voltage

V_I

V

All inputs

—

Storage temperature range

T_STG

Chip

°C

Tj:Chip surface temperature

RECOMMENDED OPERATING CONDITIONS

V_SS= 0 V

Unit Applicable pins

Parameter

Power supply voltage

Bias voltage

Symbol

V_DD

Condition

—

Rated value

3.7 to 5.5

6 to 18

V

V_DD

V_BI

—

V1 to V5

2-time multiplication

3-time multiplication

4-time multiplication

3.7 to 5.5

3.7 to 4.5

Voltage multiplier reference

voltage

V_IN

V

V_IN

Voltage multiplier output

voltage

V_OUT

T_JOP

External input

—

6.0 to 18

V

V_OUT

—

Operating temperature range

–40 to +85

°C

Note 1: The electrical characteristics are influenced by COG trace resistance. This LSI always has to

be evaluated before using.

V_OUT

V1 to V5

V_IN

V_DD

V_CC

GND

V_SS

System (MPU)

ML9058E

Note 2: The voltages V_DD, V1 to V5, and V_OUTare values taking V_SS= 0 V as the reference.

Note 3: The highest bias potential is V1 and the lowest is V_SS.

Note 4: Always maintain the relationship V1  V2  V3  V4  V5  V_SSamong these voltages.

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Note 5: When using an external power supply, follow the procedure for power application.

When applying external power to the V_OUTpin only, apply V_OUTafter V_DD.

When applying external power to the V1 pin only, apply V1 after V_DD.

When applying external power to the V1 pin to V5 pin, apply V1 to V5 after V_DD.

Note that the above (Note 4) must be satisfied including transient state at power application.

Note 6: When using an external power supply, follow the procedure for power removal described

below.

When external power is in use for the V_OUTpin only, remove V_OUTafter V_DD.

When external power is in use for the V1 pin only, remove V1 after V_DD.

When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after V_DD.

Note that the above (Note 4) must be satisfied including transient state at power removal.

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ML9058E

ELECTRICAL CHARACTERISTICS

DC Characteristics

[V_SS= 0 V, V_DD= 3.7 to 5.5 V, Tj =–40 to +85°C]

Applicable

Parameter

Symbol

Condition

Min

Typ

Max

Unit

pins

“H” Input voltage

“L” Input voltage

“H” Input voltage

“L” Input voltage

Hysteresis width

“H” output voltage

“L” output voltage

“H” Input current

“L” Input current

V_IH

V_IL

V_IH

V_IL

V

V_OH

V_OL

I_IH

0.8  V_DD

0

—

1.0

—

V_DD

0.2  V_DD

V_DD

V

*1

0.8  V_DD

0

V

*2

0.2  V_DD

1.55

V_DD= 4.5 to 5.5 V

I_OH= –0.5 mA

I_OL= 0.5 mA

V_I= V_DD

0.85

0.8  V_DD

—

V

A

*3

0.2  V_DD

+1.0

–1.0

*4 *5

*1, *2

V1

I_IL

V_I= 0 V

–3.0

+3.0

Tj=25°C

Input capacitance

C_I

—

8

12

pF

F=10kHz

Tj = 25°C

V1 = 12 V

Tj = 25°C

*6

V1 output voltage

temperature gradient

Reference voltage

V1 output voltage

V1TC

–0.03

–0.05

–0.08

%/°C

V_REG

V1

2.925

10.58

3.00

3.075

11.12

V

V_RS

V1

10.85

3-time

multiplication *7

13.0

—

V

V_OUT

Voltage multiplier

output voltage

V_OUT

4-time

multiplication *8

15.9

0.6

—

V

V_OUT

V_OUT- V1 voltage

Vot1

R_ON

*9

V_OUT,V1

SEG1 to 131,

COMS0,

COMS1,

LCD driver ON

resistance

I_O= 50 µA

—

10

k

COM0 to 63

18

14

22

—

26

31

kHz

*10

Internal

oscillation

f_OSC

Tj = 25°C

Oscillator

frequency

External

input

f_EXT

18

22

26

kHz

CL*10

*1:

*2:

*3:

*4:

*5:

DB0 to DB5, DB7 (SI), FR, DOF Pins

A0, CS1, CS2, CLS, M/S, C86, P/S, IRS,RD (E), WR (R/W), RES, CL, DB6 (SCL) Pins

DB0 to DB7, FR, FRS, DOF, CL Pins

A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS Pins

Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF in the high impedance

state.

*6:

*7:

Tj = 25°C,  = 31, (1+Rb/Ra) = 4, V_OUT= 13.5 V (External input), LCD drive output = no-load

V_IN= 4.8 V, voltage multiplier capacitor C1 = 2.6 to 4.0 F, voltage multiplier output load current

I = 500 A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by command “2C”.

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ML9058E

*8:

V_IN= 4.5 V, voltage multiplier capacitor C1 = 2.6 to 4.0 F, voltage multiplier output load current

I = 500 A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by command “2C”.

*9:

V1 load current I = 400 A. 8 V is externally input to V_OUT.

The voltage adjustment circuit and V/F circuit operate by command “2B”. LCD output = no load

*10: See Table 1 for the relationship between the oscillator frequency and the frame frequency.

Table 1. Relationship among the oscillator frequency (f_OSC), external input frequency(f_EXT

)

display clock frequency (f_LCDCK), and LCD frame frequency (f_FR)

Display clock frequency

LCD frame frequency

(f_FR

Parameter

(f_LCDCK

f_OSC/4

f_EXT/4

)

When the internal oscillator is used

f_OSC/(4  65)

f_EXT/(4 65)

ML9058E

When the internal oscillator is not used

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ML9058E

 Operating current consumption value

(1) During display operation, internal power supply OFF (The current flowing through V_DDwith V1 to V5

externally applied when an external power supply is used, not including the current for the LCD drive)

[V_SS= 0 V, Tj = 25°C]

Rated value

Display mode

All-white

Symbol

I_DD

Condition

Unit

Min

—

Typ

16

12

16

12

Max

45

V_DD= 5 V, V1- V_SS= 11 V, no load

V_DD= 3.7 V, V1- V_SS= 8 V, no load

V_DD= 5 V, V1- V_SS= 11 V, no load

V_DD= 3.7 V, V1- V_SS= 8 V, no load

A

—

35

—

45

Checker pattern

I_DD

A

—

35

(2) During display operation, internal power supply ON (Total of currents flowing through V_DDand V_IN)

[V_SS= 0 V, Tj = 25°C]

Rated value

Display

mode

Symbol

Condition

Unit

Min

Typ

100

Max

Frame reversal,

_DD,V_IN= 5 V, 3-time

voltage multiplication

V1 - V_SS= 11 V, no load

Frame reversal,

V

—

170

190

170

V

_DD,V_IN= 3.7 V, 4-time

110

100

120

130

120

All-white

I_DDIN

A

voltage multiplication

V1 - V_SS= 8 V, no load

16-line reversal,

V_DD,V_IN= 5 V, 3-time

voltage multiplication

V1 - V_SS= 11 V, no load

Frame reversal,

V

_DD,V_IN= 5 V, 3-time

—

205

220

205

voltage multiplication

V1 - V_SS= 11 V, no load

Frame reversal,

V

_DD,V_IN= 3.7 V, 4-time

Checker

pattern

I_DDIN

A

voltage multiplication

V1 - V_SS= 8 V, no load

16-line reversal,

_DD,V_IN= 5 V, 3-time

voltage multiplication

V

V1 - V_SS= 11 V, no load

 Power save mode current consumption

[V_SS= 0 V, Tj = 25°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

—

Typ

0.3

9

Max

5

Sleep mode

I_DDS1

I_DDS2

V_DD= 3.7 V

A

Standby mode

—

15

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ML9058E

Parallel Interface Timing Characteristics

 System bus Write characteristics 1 (80-series MPU)

V_IH

V_IL

V_IH

V_IL

A0



t_AW8

t_AH8

CS1

(CS2 = “H”)



t_CYC8

t_CCLW

V_IH

WR

V_IL

t_CCHW

t_DS8

t_DH8

DB0 to DB7

(Write)

V_IH

V_IL

V_IH

V_IL

 System bus Read characteristics 1 (80-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

t_AH8

t_AW8

CS1

(CS2 = “H”)

t_CYC8

V_IH

t_CCLR

V_IH

RD

V_IL

t_CCHR

t_OH8

t_ACC8

V_OH

V_OL

V_OH

V_OL

DB0 to DB7

(Read)

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ML9058E

[V_DD= 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

5

Max

—

70

50

Address hold time

t_AH8

t_AW8

Address setup time

System cycle time

5

t_CYC8

t_CCLW

t_CCLR

t_CCHW

t_CCHR

t_DS8

166

30

70

55

30

10

—

5

Control L pulse width (WR)

Control L pulse width (RD)

Control H pulse width (WR)

Control H pulse width (RD)

Data setup time

ns

Data hold time

t_DH8

RD Access time

t_ACC8

t_OH8

CL = 100 pF

Output disable time

[V_DD= 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

5

Max

—

Address hold time

t_AH8

t_AW8

Address setup time

System cycle time

5

—

t_CYC8

t_CCLW

t_CCLR

t_CCHW

t_CCHR

t_DS8

300

60

120

60

40

15

—

Control L pulse width (WR)

Control L pulse width (RD)

Control H pulse width (WR)

Control H pulse width (RD)

Data setup time

—

ns

—

Data hold time

t_DH8

—

RD Access time

t_ACC8

t_OH8

140

100

CL = 100 pF

Output disable time

10

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)  (t_CYC8

t_CCLW– t_CCHW) or (tr + tf)  (t_CYC8– t_CCLR– t_CCHR).

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

–

Note 3: The values of t_CCLWand t_CCLRare specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “L” levels of WR and RD, respectively.

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ML9058E

 System bus Write characteristics 2 (68-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

t_AH6

t_AW6

R/W

V_IL

CS1

(CS2 = “H”)

t_CYC6

t_EWHW

E

V_IH

V_IL

t_EWLW

t_DS6

t_DH6

DB0 to DB7

(Write)

V_IH

V_IL

V_IH

V_IL

 System bus Read characteristics 2 (68-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

V_IH

t_AW6

t_AH6

V_IH

R/W

CS1

(CS2 = “H”)

t_CYC6

t_EWHR

E

V_IH

V_IL

t_EWLR

t_OH6

t_ACC6

V_OH

V_OL

V_OH

V_OL

DB0 to DB7

(Read)

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ML9058E

[V_DD= 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

5

Max

—

70

50

—

Address hold time

Address setup time

System cycle time

Data setup time

Data hold time

t_AH6

t_AW6

t_CYC6

t_DS6

5

166

30

10

—

t_DH6

ns

Access time

t_ACC6

t_OH6

CL = 100 pF

Output disable time

10

70

30

60

Read

Write

Read

Write

t_EWHR

t_EWHW

t_EWLR

t_EWLW

Enable H pulse width

Enable L pulse width

[V_DD= 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

5

Max

—

Address hold time

Address setup time

System cycle time

Data setup time

Data hold time

t_AH6

t_AW6

t_CYC6

t_DS6

5

—

300

40

15

—

t_DH6

—

ns

Access time

t_ACC6

t_OH6

140

100

—

CL = 100 pF

Output disable time

10

120

60

Read

Write

Read

Write

t_EWHR

t_EWHW

t_EWLR

t_EWLW

Enable H pulse width

Enable L pulse width

—

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)  (t_CYC6

t_EWLW– t_EWHW) or (tr + tf)  (t_CYC6– t_EWLR– t_EWHR).

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

–

Note 3: The values of t_EWLWand t_EWLRare specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “H” level of E.

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ML9058E

Serial Interface Timing Characteristics

 Serial interface

t_CSS

t_CSH

CS1

(CS2 = “1”)

V_IL

t_SAH

V_IH

V_IL

t_SCYC

V_IH

t_SAS

V_IH

V_IL

A0

t_SLW

V_IH

SCL

V_IL

t_f

t_SHW

t_r

t_SDH

t_SDS

V_IH

V_IL

V_IH

V_IL

SI

[V_DD= 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

200

75

Max

—

Serial clock period

t_SCYC

t_SHW

t_SLW

t_SAS

t_SAH

t_SDS

t_SDH

t_CSS

t_CSH

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time

75

50

ns

100

50

CS setup time

100

CS hold time

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

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ML9058E

[V_DD= 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

250

100

150

100

150

Max

—

Serial clock period

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time

t_SCYC

t_SHW

t_SLW

t_SAS

t_SAH

t_SDS

t_SDH

t_CSS

t_CSH

ns

CS setup time

CS hold time

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

 Display control output timing

V_OH

CL(OUT)

t_DFR

V_IH

V_IL

FR

[V_DD= 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Unit

Parameter

FR Delay time

Symbol

t_DFR

Condition

Min

—

Typ

10

Max

40

CL = 50 pF

ns

[V_DD= 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Unit

Parameter

FR Delay time

Symbol

t_DFR

Condition

Min

—

Typ

20

Max

80

CL = 50 pF

ns

Note 1: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

Note 2: Valid only when the device operates in master mode.

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ML9058E

 Reset input timing

t_f

t_r

t_RW

V_IH

V_IL

RES

t_R

Internal state

Being reset

Reset complete

[V_DD= 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Unit

Parameter

Symbol

Condition

Min

—

Typ

—

Max

0.5

—

Reset time

t_R

µs

Reset “L” pulse width

t_RW

0.5

—

[V_DD= 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Unit

Parameter

Symbol

Condition

Min

—

1

Typ

—

Max

1

Reset time

t_R

µs

Reset “L” pulse width

t_RW

—

Note 1: The input signal rise and fall times (t_r, t_f) are specified as 15 ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

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PIN DESCRIPTION

Function Pin name

ML9058E

Number

of pins

I/O

Description

These are 8-bit bi-directional data bus pins that can be connected to

8-bit standard MPU data bus pins. When a serial interface is selected

(P/S = “L”):

DB7: Serial data input pin (SI)

DB0 to

DB7

8

I/O DB6: Serial clock input pin (SCL)

In this case, DB0 to DB5 will be in the high impedance state. DB0 to

DB7 will all be in the high impedance state when the chip select is in

the inactive state.

Fix the DB0 to DB5 pins at “H” or “L” level.

Normally, the lowest bit of the MPU address bus is connected and

used for distinguishing between data and commands.

A0

1

I

A0 = “H”: Indicates that DB0 to DB7 is display data.

A1 = “L”: Indicates that DB0 to DB7 is control data.

Initial setting is made by making RES = “L”. The reset operation is

made during the active level of the RES signal.

RES

1

2

I

These are the chip select signals. The Chip Select of the LSI

becomes active when CS1 is “L” and also CS2 is “H” and allows the

input/output of data or commands.

CS1

I

CS2

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the RD signal of the 80-series MPU,

and the data bus of the ML9058E goes into the output state when this

signal is “L”.

MPU

Interface

RD

1

The active level of this signal is “H” when connected to a 68-series

MPU. This pin will be the Enable and clock input pin when connected

to a 68-series MPU.

(E)

When a serial interface is selected (P/S = “L”), fix this pin at “H” or “L”

level.

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the WR signal of the 80-series MPU.

The data on the data bus is latched into the ML9058E at the rising

edge of the WR signal.

WR

When connected to a 68-series MPU, this pin becomes the input pin

for the Read/Write control signal.

1

I

(R/W)

R/W = “H”: Read, R/W = “L”: Write

When a serial interface is selected (P/S = “L”), fix this pin at “H” or “L”

level.

This is the pin for selecting the MPU interface type.

C86 = “H”: 68-Series MPU interface.

C86

C86 = “L”: 80-Series MPU interface.

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FEDL9058E-01

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ML9058E

Number

of pins

Function Pin name

I/O

Description

This is the pin for selecting parallel data input or serial data input.

P/S = “H”: Parallel data input.

P/S = “L”: Serial data input.

The pins of the LSI have the following functions depending on the

state of P/S input.

MPU

Interface

P/S

1

I

P/S

“H”

“L”

Data/command

Data

DB0 to DB7

SI (D7)

Read/Write

RD, WR

—

Serial clock

—

A0

SCL(DB6)

During serial data input, it is not possible to read the display data in

the RAM

This is the pin for selecting whether to enable or disable the internal

oscillator circuit for the display clock.

Oscillator

CLS

CLS = “H”: The internal oscillator circuit is enabled.

1

I

circuit

CLS = “L”: The internal oscillator circuit is disabled (External input).

When CLS = “L”, the display clock is input at the pin CL.

This is the pin for selecting whether master operation or slave

operation is made towards the ML9058E. During slave operation,

the synchronization with the LCD display system is achieved by

inputting the timing signals necessary for LCD display.

M/S = “H”: Master operation

M/S = “L”: Slave operation

Display

The functions of the different circuits and pins will be as follows

depending on the states of M/S and CLS signals.

timing

generator

M/S

1

I

circuit

Oscillator

circuit

Power

supply circuit

Enabled

M/

S

CLS

CL

FR

FRS

DOF

“H”

“L”

“H”

“L”

Enabled

Disabled

Output

Input

Output

Input

Output

Input

“H”

“L”

Enabled

Disabled

Input

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Number

of pins

Function Pin name

I/O

Description

This is the clock input/output pin.

The function of this pin will be as follows depending on the states of

M/S and CLS signals.

M/S

CLS

“H”

“L”

CL

Output

Input

“H”

CL

1

“H”

“L”

When the ML9058E is used in the master/slave mode, the

corresponding CL pin has to be connected.

Display

timing

generator

circuit

FR

This is the input/output pin for LCD display frame reversal signal.

M/S = “H”: Output

M/S = “L”: Input

1

I/O

When the ML9058E is used in the master/slave mode, the

corresponding FR pin has to be connected.

This is the blanking control pin for the LCD display.

M/S = “H”: Output

DOF

1

I/O

O

M/S = “L”: Input

When the ML9058E is used in the master/slave mode, the

corresponding DOF pin has to be connected.

This is the output pin for static drive.

FRS

This pin is used in combination with the FR pin.

This is the pin for selecting the resistor for adjusting the voltage V1.

IRS = “H”: The internal resistor is used.

IRS = “L”: The internal resistor is not used. The voltage V1 is

adjusted using the external potential divider resistors connected to

the pins VR. This pin is effective only in the master operation. This

pin is tied to the “H” or the “L” level during slave operation.

IRS

1

I

Power

supply

circuit

V_DD

12

—

These pins are tied to the MPU power supply pin V_CC.

V_SS

V_IN

These are the 0 V pins connected to the system ground (GND).

These are the reference power supply pins of the voltage multiplier

circuit for driving the LCD.

—

5

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Number

of pins

Function Pin name

I/O

—

Description

These are the test pins for the LCD power supply voltage adjustment

circuit. Leave these pins open.

V_RS

2

These are the output pins during voltage multiplication. Connect a

V_OUT

I/O

capacitor between these pins and V_SS

.

These are the multiple level power supply pins for the LCD power

supply. The voltages specified for the LCD cells are applied to these

pins after resistor network voltage division or after impedance

transformation using operational amplifiers. The voltages are

specified taking V_SSas the reference, and the following relationship

should be maintained among them.

V1  V2  V3  V4  V5  V_SS

V1

V2

V3

V4

V5

Master operation: When the power supply is ON, the following

voltages are applied to V2 to V5 from the built-in power supply circuit.

The selection of voltages is determined by the LCD bias set

command.

10

I/O

ML9058E

V2

V3

V4

V5

8/9  V1

7/9  V1

2/9  V1

1/9  V1

6/7  V1

5/7  V1

2/7  V1

1/7  V1

Power

supply

circuit

Voltage adjustment pins. Voltages between V1 and V_SSare applied

using a resistance voltage divider.

These pins are effective only when the internal resistors for voltage

V1 adjustment are not used (IRS = “L”).

VR

2

I

Do not use these pins when the internal resistors for voltage V1

adjustment are used (IRS = “H”).

These are the pins for connecting the negative side of the capacitors

for voltage multiplication.

VS1–

VS2–

VC3+

3

O

Connect capacitors between these pins and VC3+, VC5+.

These are the pins for connecting the negative side of the capacitors

for voltage multiplication.

Connect capacitors between these pins and VC4+, VC6+.

These are the input pins for voltage multiplication.

Apply the voltage equal to V_INto the pins or leave them open,

depending on voltage multiplication values.

These are the pins for connecting the positive side of the capacitors

for voltage multiplication.

VC4+

3

O

Connect capacitors between VS2– and these pins.

For 3-time voltage multiplication, the pins are configured as inputs for

voltage multiplication.

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Number

of pins

Function Pin name

I/O

O

Description

These are the pins for connecting the positive side of the capacitors

for voltage multiplication.

Connect capacitors between VS1– and these pins.

For 2-time voltage multiplication, the pins are configured as inputs

for voltage multiplication.

VC5+

3

Power

supply

circuit

These are the pins for connecting the positive side of the capacitors

for voltage multiplication.

VC6+

O

Connect capacitors between VS2– and these pins.

These are the LCD segment drive outputs.

One of the levels among V1, V3, V4, and V_SSis selected depending

on the combination of the display RAM content and the FR signal

Output voltage

RAM Data

FR

Forward display Reverse display

H

L

V1

V_SS

V3

V4

V3

V4

V1

V_SS

SEG0 to

SEG131

132

O

H

L

H

L

Power save

—

V_SS

LCD

Drive

output

The output voltage is V_SSwhen the Display OFF command is

executed.

These are the LCD common drive outputs.

One of the levels among V1, V2, V5, and V_SSis selected depending

on the combination of the scan data and the FR signal.

Scan data

FR

H

Output voltage

H

V_SS

V1

COM0 to

COM63

H

L

64

O

L

H

V2

L

V5

Power save

—

V_SS

The output voltage is V_SSwhen the Display OFF command is

executed.

These are the common output pins only for indicators. Both pins

output the same signal. Leave these pins open when they are not

used. The same signal is output in both master and slave operation

modes.

COMS0

COMS1

2

O

These are the pins for testing the IC chip. Leave these pins open

during normal use.

Test pin

—

TEST1

1

O

DUMMY

67

11

—

Leave this pin open.

DUMMY-

B

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

FUNCTIONAL DESCRIPTION

MPU Interface

MPU

Read mode

Pin RD = “L”

Pin R/W = “H”

Pin E = “H”

Write mode

80-Series

Pin WR = “L”

Pin R/W = “L”

Pin E = “H”

68-Series

In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR

pin.

In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin.

 Selection of interface type

The ML9058E carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data

input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting

the P/S pin to the “H” or the “L” level.

Table 2 Selection of interface type (parallel/serial)

P/S

CS1

CS2

A0

RD

—

WR

—

C86

—

D7

SI

D6

DB0 to DB5

H: Parallel input

L: Serial input

DB0 to DB5

—

SCL

A hyphen (—) indicates that the pin can be tied to the “H” or the “L” level.

 Parallel interface

When the parallel interface is selected, (P/S = “H”), it is possible to connect this LSI directly to the MPU bus of

either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to “H”

or “L”.

Table 3 Selection of MPU during parallel interface (80–/68–series)

C86

CS1

CS2

A0

RD

E

WR

R/W

WR

DB0 to DB7

H: 68-Series MPU bus

L: 80-Series MPU bus

RD

The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD

(E), and WR (R/W) of Table 3.

Table 4 Identification of data bus signals during parallel interface

Common

68-Series

80-Series

A0

1

R/W

RD

0

WR

1

Display data read

Display data write

Status read

1

0

1

0

1

0

1

Control data write (command)

0

1

0

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Serial Interface

When the serial interface is selected (P/S = “L”), the serial data input (SI) and the serial clock input (SCL) can be

accepted if the chip is in the active state (CS1 = “L” and CS2 = “H”). The serial interface consists of an 8-bit shift

register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, ... ,

DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial

clock pulse and processed further. The identification of whether the serial data is display data or command is

judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command when A0 is

“L”. The A0 input is read in and identified at the rising edge of the (8  n) th serial clock pulse after the chip has

become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register

and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is

necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL

signal. We recommend verification of operation in an actual unit.)

CS1

CS2

DB7

1

DB5

3

DB7

9

DB3

DB6 DB5 DB4 DB2

DB6

2

DB4 DB3 DB2 DB1 DB0

SI

SCL

A0

4

5

6

7

8

10 11 12 13 14

Fig. 1 Signal chart during serial interface

 Chip select

The ML9058E has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled

only when CS1 = “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines

will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface

has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state.

 Accessing the display data RAM and the internal registers

Accessing the ML9058E from the MPU side requires merely that the cycle time (t_CYC) be satisfied, and high speed

data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the

ML9058E carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data

bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus

holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU

reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in

the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a

restriction on the read sequence of the display data RAM, which is that the read instruction immediately after

setting the address does not read out the data of that address, but that data is output as the data of the address

specified during the second data read sequence, and hence care should be taken about this during reading.

Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The

status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b).

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

 Data write

WR

Dn

Dn + 1

Dn + 2

Dn + 3

DATA

Latch

Dn

Dn + 1

Dn + 2

BUS Holder

Write Signal

Fig. 2(a) Write sequence of display data RAM

 Data read

WR

RD

N

unknown

Dn

Dn + 1

DATA

Address

Preset

Read Signal

Column

Address

Increment N + 1

Dn

Preset N

unknown

N + 2

Dn + 1

Dn + 2

BUS Holder

Data Read

Dn

Address Set

N

Data Read

Dn + 1

Data Read

(Dummy)

Fig. 2(b) Read sequence of display data RAM

Dn = Data

N = Address data

 Busy flag

The busy flag being “1” indicates that the ML9058E is carrying out reset operations, and hence no instruction other

than a status read instruction is accepted during this period. The busy flag is output at pin DB7 when a status read

instruction is executed.

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Display Data RAM

 Display data RAM

This is the RAM storing the dot data for display and has an organization of 65 (8 pages  8 bits +1)  132 bits. It

is possible to access any required bit by specifying the page address and the column address. Since the display data

DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig.

3, there are fewer restrictions during display data transfer when the ML9058E is used in a multiple chip

configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the

display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the

signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when

the display data RAM is accessed asynchronously during the LCD display operation.

DB0

DB1

DB2

DB3

DB4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0





0

COM0

COM1

COM2

COM3

COM4



Display data RAM

LCD Display

Fig. 3 Relationship between display data RAM and LCD display

 Page address circuit

The page address of the display data RAM is specified using the page address set command as shown in Fig. 4.

Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1,

DB0  1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page.

 Column address circuit

The column address of the display data RAM is specified using the column address set command as shown in Fig.

4. Since the specified column address is incremented (by +1) every time a display data read/write command is

issued, the MPU can access the display data continuously. Further, the incrementing of the column address is

stopped at the column address of 83(H). Since the column address and the page address are independent of each

other, it is necessary, for example, to specify separately the new page address and the new column address when

changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to

reverse the correspondence relationship between the display data RAM column address and the segment output

using the ADC command (the segment driver direction select command). This reduces the IC placement

restrictions at the time of assembling LCD modules.

Table 5 Correspondence relationship between the display data RAM column address

and the segment output

SEGMENT Output

ADC

SEG0

0(H)

SEG131

83(H)

0(H)

DB0 = “0”

DB0 = “1”





Column Address





83(H)

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

 Line address circuit

The line address circuit is used for specifying the line address corresponding to the common output when

displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is

specified using the display start line address set command (COM0 output in the forward display state of the

common output, and COM63 output in the reverse display state). The display area is 64 lines in the direction of

increasing line address from the specified display start line address. When the indicator–dedicated common output

pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start

line address. COMS selection is 65th in order.

It is possible to carry out screen scrolling by dynamically changing the line address using the display start line

address set command.



 Display data latch circuit

The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being

output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the

display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.

Oscillator Circuit

This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = “H”

and also CLS = “H”. The oscillations will be stopped when CLS = “L”, and the display clock has to be input to the

CL pin.

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

When the common

output state is

Line

COM

Page Address

Data

Address

Output

normal display

DB0

DB1

DB2

DB3

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

40H

COM0

COM1

COM2

COM3

0

1

0

1

0

1

0

1

0

1

0

1

0

Page0

Page1

Page2

Page3

Page4

Page5

Page6

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

(Start)

0

1

0

1

0

1

0

Page7

Page8

COMS

The 40(H) is displayed

irrespective of the

display start line

address.

Fig. 4 Display data RAM address map

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Display Timing Generator Circuit

This circuit generates the timing signals for the line address circuit and the display data latch circuit from the

display clock. The display data is latched in the display data latch circuit and is output to the segment drive output

pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit

and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit

and is output to the segment drive output pins in synchronization with the display clock. The read out of the

display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU.

As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed

asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals

are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method

shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal

drive method shown in Fig. 5(b) are also generated by the command.

48 49

1

2

3

4

5

6

44 45 46 47 48 49

1

2

3

4

5

6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V_SS

V1

V2

COM1

V5

V_SS

RAM

DATA

V1

V3

V4

V_SS

SEGn

Fig. 5(a) Waveforms in the frame reversal drive method

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

49

48

1

2

3

4

5

6

44 45 46 47 48 49

1

2

3

4

5

6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V_SS

V1

V2

COM1

V5

V_SS

RAM

DATA

V1

V3

V4

V_SS

SEGn

Fig. 5(b) Waveforms in the line reversal drive method

When the ML9058E is used in a multiple chip configuration, it is necessary to supply the slave side display timing

signals (FR, CL, and DOF) from the master side. However, when the line reversal drive is set, the ML9058E is not

used in a multiple chip configuration.

The statuses of the signals FR, CL, and DOF are shown in Table 6.

Table 6 Display timing signals in master mode and slave mode

Operating mode

FR

CL

DOF

Output

Input

Internal oscillator circuit enabled (CLS = H)

Internal oscillator circuit disabled (CLS = L)

Internal oscillator circuit disabled (CLS = H)

Internal oscillator circuit disabled (CLS = L)

Output

Input

Output

Input

Master mode (M/S = “H”)

Slave mode (M/S = “L”)

Input

Note: During master mode, the oscillator circuit operates from the time the power is applied. The

oscillator circuit can be stopped only in the sleep state.

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Common Output State Selection Circuit (see Table 7)

Since the common output scanning directions can be set using the common output state selection command in the

ML9058E, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules.

Table 7 Common output state settings

State

Common Scanning direction

COM0  COM63

Forward Display

Reverse Display

COM63  COM0

LCD Drive Circuit

This LSI incorporates 181 sets of multiplexers for the ML9058E, that generate 4-level outputs for driving the LCD.

These output the LCD drive voltage in accordance with the combination of the display data, common scanning

signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame

reversal drive method.

Static Indicator Circuit

The FR pin is connected to one side of the LCD drive electrode of the static indicator and the FRS pin is connected

to the other side.

The static indicator display is controlled by a command only independently of other display control commands.

The electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode.

If the wiring pattern is placed too near to the dynamic drive electrode, the LCD and electrode may be degraded.

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

COM0

V_DD

V_SS

COM1

COM2

COM3

COM4

COM5

COM6

COM7

FR

V1

V2

V3

V4

V5

COM0

V_SS

COM8

COM9

V1

V2

V3

COM10

COM11

COM12

COM13

COM14

COM15

COM1

COM2

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

SEG0

SEG1

SEG2

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

V4

V5

0V

-V5

-V4

COM0-SEG0

-V3

-V2

-V1

V1

V2

V3

V4

V5

0V

-V5

-V4

COM0-SEG1

-V3

-V2

-V1

Fig. 6 Output waveforms in the frame reversal drive method

(FR waveform/common waveform/segment waveform/voltage difference

between common and segment)

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

Power Supply Circuit

This is the low power consumption type power supply circuit for generating the voltages necessary for driving

LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits.

In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier,

voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is

also possible to use parts of the functions of both the external power supply and the internal power supply. Table

8 shows the functions controlled by the 3-bit data of the power control set command and Table 9 shows a sample

combination.

Table 8 Details of functions controlled by the bits of the power control set command

Control bit

DB2

Function controlled by the bit

Voltage multiplier circuit control bit

DB1

Voltage adjustment circuit (V1 voltage adjustment circuit) control bit

Voltage follower circuit (V/F circuit) control bit

DB0

Table 9 Sample combination for reference

Circuit

V

External

voltage

input

Voltage

multiplier

pins *1

State used

DB2 DB1 DB0

Voltage

multiplier

V/F

Adjustment

Only the internal power

supply is used

1



V_IN

Used

Only V adjustment and

V/F circuits are used

0

1

0

1

0





V_OUT

V1

OPEN

Only V/F circuits are used



Only the external power

supply is used



V1 to V5

*1:

The voltage multiplier pins are the pins VS1–, VS2–, VC3+, VC4+, VC5+, and VC6+.

If combinations other than the above are used, normal operation is not guaranteed.

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ML9058E

 Voltage multiplier circuits

The connections for 2- to 4-time voltage multiplier circuits are shown below.

V_IN

V_SS

+

V_OUT

VC6+

VC4+

V_OUT

VC6+

VC4+

V_OUT

VC6+

VC4+

+

OPEN

VS2–

VC5+

VC3+

VS2–

VC5+

VC3+

VS2–

VC5+

VC3+

+

OPEN

VS1–

2-time voltage

4-time voltage

3-time voltage

multiplier circuit

Fig. 7 Connection examples for voltage multiplier circuits

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The voltage relationships in voltage multiplication are shown in Fig. 8.

V_OUT= 3  V_IN

V_OUT= 4  V_IN

= 15.0 V

= 18 V

*1 V_IN= 5.0 V

V_SS= 0 V

*1 V_IN= 4.5 V

V_SS= 0 V

Voltage relationship in 3-time multiplication

Voltage relationship in 4-time multiplication

Fig. 8 Voltage relationships in voltage multiplication

*1:

The voltage range of V_INshould be set from 6V to 18.33V so that the voltage at the pin V_OUTdoes

not exceed the voltage multiplier output voltage operating range.

 Voltage adjustment circuit

The voltage multiplier output V_OUTproduces the LCD drive voltage V1 via the voltage adjustment circuit. Since

the ML9058E incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer

function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment

circuit with very few components. In addition, the ML9058E is available with the temperature gradients of a

VREG - about –0.05%/°C.

(a) When the internal resistors for voltage V1 adjustment are used

It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using

commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the

electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in

the range of V1<VOUT.

V1 = (1 + (Rb/Ra))  VEV = (1 + (Rb/Ra))  (1 – (/324))  VREG (Eqn. A-1)

VEV (Constant voltage supply +

electronic potentiometer)

+

V1

–

VRS

(VREG)

VR

Internal Rb

Internal Ra

Fig. 9 V1 voltage adjustment circuit (equivalent circuit)

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VREG is a constant voltage generated inside the IC and VRS pin output voltage.

Here,  is the electronic potentiometer function which allows one level among 64 levels to be selected by merely

setting the data in the 6-bit electronic potentiometer register. The values of  set by the electronic potentiometer

register are shown in Table 10.

Table 10 Relationship between electronic potentiometer register and 



63

62

61

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

0

1

0

1

Rb/Ra is the voltage V1 adjustment internal resistor ratio and can be adjusted to one of 7 levels by the voltage V1

adjustment internal resistor ratio set command. The reference values of the ratio (1 + Rb/Ra) according to the 3-bit

data set in the voltage V1 adjustment internal resistor ratio setting register are listed in Table 11.

Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio

(1+Rb/Ra) (Nominal)

Register

(1 + Rb/Ra)

DB2

0

DB1

0

DB0

0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

1

0

1

0

1

0

1

0

1

0

Note: Use V1 gain in the range from 3 to 6 times. Because this LSI has temperature gradient, V1

voltage rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic

potentiometer so that V1 voltage does not exceed 18 V.

When V1 is set using the built-in resistance ratio, the accuracies are shown in Table 12.

Table 12 Relation between V1 Output Voltage Accuracy and V1 Gain Using Built-in Resistor

V1 gain

Parameter

Unit

3 times

2.5

9

3.5 times

4 times

2.5

12

4.5 times

5 times

2.5

15

5.5 times

6 times

2.5

18

V1 output voltage accuracy

V1 maximum output voltage

2.5

%

V

10.5

13.5

16.5

Note: The V1 maximum output voltages in Table 12 are nominal values when Tj = 25°C, and electronic

potentiometer  = 0. The V1 output voltage accuracy in Table 12 are values when V1 load current

I = 0 A, 20 V is externally input to V_OUT, and display is turned OFF.

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(b) When external resistors are used (voltage V1 adjustment internal resistors are not used)

It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1

adjustment but connecting external resistors (Ra' and Rb') between V_SS& VR and between VR & V1. Even in this

case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using

commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation B-1 in the range of V1<V_OUTby setting the external

resistors Ra' and Rb' appropriately.

V1 = (1 + (Rb'/Ra'))  VEV = (1 + (Rb'/Ra'))  (1 – (/324))  VREG (Eqn. B-1)

External Rb'

VR

External Ra'

–

+

V_SS

V1

VEV (Constant voltage supply +

electronic potentiometer)

Fig. 10 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 = 7 V at Tj = 25°C

When the electronic potentiometer register value is set to the middle value of (DB5, DB4, DB3, DB2, DB1, DB0)

= (1, 0, 0, 0, 0, 0), the value of  will be 31 and that of VREG will be 3.0 V, and hence the equation B-1 becomes

as follows:

V1 = (1 + (Rb'/Ra'))  (1 – (/324))  VREG

7 = (1 + (Rb'/Ra'))  (1 – (31/324))  3.0 (Eqn. B-2)

Further, if the current flowing through Ra' and Rb' is set as 5 µA, the value of Ra' + Rb' will be - Ra' + Rb' = 1.4

M (Eqn. B-3)

and hence,

Rb'/Ra' = 1.58, Ra' = 543 k, Rb' = 857 k.

In this case, the variability range of voltage V1 using the electronic potentiometer function will be as given in

Table 13.

Table 13 Example 1 of V1 variable-voltage range using electronic potentiometer function

V1

Min

Typ

Max

Unit

[V]

Variable-voltage range

6.24 ( = 63)

7.0 ( = 31)

7.74 ( = 0)

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(c) When external resistors are used (voltage V1 adjustment internal resistors are not used) and a variable resistor

is also used

It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a

variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control

the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic

potentiometer function is used.

The voltage V1 can be obtained by the following equation C-1 in the range of V1<V_OUTby setting the external

resistors R₁, R₂(variable resistor), and R₃appropriately and making fine adjustment of R₂(R₂).

V1 = (1 + (R₃+ R₂– R₂)/(R₁+ R₂))  VEV

= (1 + (R₃+ R₂– R₂)/(R₁+ R₂))  (1 – (/324))  VREG (Eqn. C-1)

External R₃

Rb'

External R₂

VR

–

+

 R₂

V1

Ra'

External R₁

VEV (Constant voltage supply +

electronic potentiometer)

V_SS

Fig. 11 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 in the range 5 V to 9 V using R₂at Tj = 25°C .

When the electronic potentiometer register value is set to (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0),

the value of  will be 31 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when R₂= 0, the

equation C-1 becomes as follows:

9 = (1 + (R₃+ R₂)/R₁)  (1 – (31/324))  (3.0) (Eqn. C-2)

In order to make V1 = 5 V when R₂= R₂,

5 = (1 + R₃/(R₁+R₂))  (1 – (31/324))  (3.0) (Eqn. C-3)

Further, if the current flowing between V_SSand V1 is set as 5 µA, the value of R₁+ R₂+ R₃becomes-

R₁+ R₂+ R₃= 1.8 M (Eqn. C-4)

and hence,

R₁= 542 k, R₂= 436 k, R₃= 822 k.

In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size

will be as given in Table 13.

Table 14 Example 2 of V1 variable-voltage range using electronic potentiometer function and

variable resistor

V1

Min

Typ

Max

Unit

[V]

Variable-voltage range

4.45 ( = 63)

7.0 ( = 31)

9.96 ( = 0)

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ML9058E

In Figures 10 and 11, the voltage VEV is obtained by the following equation by setting the electronic

potentiometer between 0 and 63.

VEV = (1 - (/324))  VREG

 = 0: VEV = (1 – (0/324))  3.0 V = 3.0 V

 = 31: VEV = (1 – (31/324))  3.0 V = 2.712 V

 = 63: VEV = (1 – (63/324))  3.0 V = 2.416 V

The increment size of the electronic potentiometer at VEV when VREG = 3.0 is :

3.0 – 2.416

 =

= 9.27 mV (Nominal)

63

When VREG = 3.069 V,  = 0 : VEV = 3.069 V,  = 63 : VEV = 2.472 V

The increment size is :

3.069 V – 2.472 V

 =

= 9.476 mV

63

When VREG = 2.931 V,  = 0 : VEV = 2.931 V,  = 63 : VEV = 2.361 V

The increment size is :

2.931 V – 2.361 V

 =

= 9.047 mV

63

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* When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary

to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the

power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply a

voltage externally to the V_OUTpin.

* The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = “L”).

Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = “H”).

* Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using

short wiring length or a shielded wire .

* The supply current increases in proportion to the panel capacitance. When power consumption increases, the

V_OUTlevel may fall. The voltage (V_OUT– V1) should be more than 3 V.

 LCD Drive voltage generator circuits

The voltage V1 is divided using resistors inside the IC to generate the voltages V2, V3, V4, and V5 that are

necessary for driving the LCD. In addition, these voltages V2, V3, V4, and V5 are impedance transformed using

voltage follower circuits and fed to the LCD drive circuits. The bias ratio of 1/9 or 1/7 can be selected using the

LCD bias setting command.

 At built-in power-on, and transition from power save state to display mode

After built-in power-on, at the command "2F(H)" input, or on transition from power save state to display mode, the

display does not operate for a maximum period of 300 ms until the built-in power is stabilized. This period of no

display is not influenced by display ON/OFF command. Despite input of display ON command during this period,

the display does not operate for this period. However, the command is valid. After the wait time is finished, the

display operates. (During this period of no display, all commands are acceptable.)

 Command sequence for shutting off the internal power supply

When shutting off the internal power supply, it is recommended to use the procedure given in Fig. 12 of switching

OFF the power after putting the LSI in the power save state using the following command sequence.

Procedure

Description

(Command, status)

Display OFF



Commands

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Step1



1

0

1

0

1

0

Power save commands

(multiple commands)

Step2

Display all ON

1

0

1

0

1

0

1



End

Internal power supply OFF

Fig. 12 Command sequence for shutting off the internal power supply

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 Application circuits

(Two V1 pins are described in the following examples for explanation, but they are the same.)

(1) When the voltage multiplier circuit, voltage

adjustment circuit, and V/F circuits are all used

(2) When the voltage multiplier circuit, voltage

adjustment circuit, and V/F circuits are all used

When not using the internal voltage V1 adjustment resistors

V_IN= V_DD3-time voltage multiplication

When using the internal voltage V1 adjustment resistors

V_IN= V_DD3-time voltage multiplication

V_DD

IRS

M/S

V_IN

+

VC6+

VC4+

VC6+

VC4+

C1

VS2–

VC5+

VC3+

VC5+

VC3+

C1

OPEN

VS1–

V1

VR

VS1–

V1

VR

R₁R₂R₃

OPEN

V_SS

C1

C2

C1

C2

+

V_OUT

V1

V2

V3

V4

V_OUT

V1

V2

V3

V4

Rall=R1+R2+R3

Rall: *3

C1:*1

C1: *1

C2: *2

V5

C2: *2

(3) When only the voltage adjustment circuit and V/F circuits

are used

(4) When only the voltage adjustment circuit and V/F circuits

are used

When not using the internal voltage V1 adjustment resistors When using the internal voltage V1 adjustment resistors

V_DD

IRS

M/S

IRS

M/S

V_IN

VC6+

VC4+

OPEN

VC6+

VC4+

OPEN

VS2–

OPEN

VS2–

OPEN

VC5+

VC3+

VS1–

OPEN

VC5+

VC3+

VS1–

OPEN

R₁R₂

V1

VR

V_SS

R₃

V1

VR

V_SS

OPEN

V_SS

External

V_OUT

External

power supply

+

C1

C2

V_OUT

power supply

V1

V2

V3

V4

V5

C1

C2

+

V1

V2

V3

V4

V5

+

Rall=R1+R2+R3

Rall: *3

C1: *1

C2: *2

C2 +

C1: *1

C2: *2

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ML9058E

(5) When only the V/F circuits are used

(6) When not using the internal power supply

V_DD

IRS

M/S

IRS

V_IN

VC6+

VC4+

M/S

V_IN

VC6+

VC4+

OPEN

VS2–

OPEN

VC5+

VC3+

VS1–

VC5+

VC3+

VS1–

OPEN

V1

VR

V_SS

V1

VR

V_SS

OPEN

V_SS

V_OUT

V1

External

power

supply

V1

V2

V3

V4

V5

C2

+

External

power

supply

V2

V3

V4

V5

C2: *2

Note: When trace resistance external to COG-mounted chip does not exist,

 when C1 (*1) = 0.9 F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F,

use in the range Rall (*3) = 1 M to 5 M.

 when C1 (*1) = 1.8 F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F,

use in the range Rall (*3) = 500 k to 1 M.

Make sure that voltage multiplier output voltage, and V1 output voltage have enough margin

before using this LSI.

 Initial setting

Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1

to V5) and the V_SSpin, a malfunction might occur: the display screen gets dark for an instant when powered

on.

To avoid a malfunction at power-on, it is recommended to follow the flowchart in the “EXAMPLES OF

SETTINGS FOR THE INSTRUCTIONS” section in page 54.

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LIST OF OPERATION

DBn

No

1

Operation

Comment

7 6 5 4 3 2 1 0

1 0 1 0 1 1 1 0

1 0 1 0 1 1 1 1

A0

0

RD

1

WR

0

Display OFF

Display ON

LCD Display:

OFF when DB0 = 0 ON when DB0 = 1

0

1

0

The display starting line address in the

display RAM is set.

2

3

Display start line set 0 1 Address

0

1

0

The page address in the display RAM is

set.

Page address set

1 0 1 1 Address

Column address set

(upper bits)

0 0 0 1 Address

(upper)

The upper 4 bits of the column address in

the display RAM is set.

4

Column address set

(lower bits)

0 0 0 0 Address

(lower)

The lower 4 bits of the column address in

the display RAM is set.

0

1

0

1

Status * * * *

The status information is read out from the

upper 4 bits.

5

Status read

6

7

Display data write

Display data read

Write data

Read data

1

0

1

Writes data to the display data RAM.

Reads data from the display data RAM.

Correspondence to the segment output for

the display data RAM address

Forward when DB0 = 0

Reverse when DB0 = 1

Forward 1 0 1 0 0 0 0 0

Reverse 1 0 1 0 0 0 0 1

0

1

0

8

ADC select

Display

Forward or reverse LCD display mode

Forward when DB0 = 0

Reverse when DB0 = 1

Forward 1 0 1 0 0 1 1 0

Reverse 1 0 1 0 0 1 1 1

0

1

0

9

OFF(Normal

1 0 1 0 0 1 0 0

display)

LCD

0

1

0

LCD

All-on display

10

Normal display when DB0 = 0

All-on display when DB0 = 1

ON

1 0 1 0 0 1 0 1

1 0 1 0 0 0 1 0

1 0 1 0 0 0 1 1

0

1

0

Sets the LCD drive voltage bias ratio.

1/9 when DB0 = 0 and 1/7 when DB0 = 1

11 LCD bias set

Incrementing column address

During a write: +1

12 Read-modify-write

1 1 1 0 0 0 0 0

0

1

0

During a read: 0

13 End

1 1 1 0 1 1 1 0

1 1 1 0 0 0 1 0

0

1

0

Releases the read-modify-write state.

Internal reset

14 Reset

Selects the common output scanning

direction.

Forward when DB3 = 0

Reverse when DB3 = 1

1 1 0 0 0 * * *

1 1 0 0 1 * * *

0

1

0

Common output

state select

15

0 0 1 0 1

Operating state

0 0 1 0 0

Resistance

ratio setting

Selects the operating state of the internal

power supply. Set the lower 3 bits.

16 Power control set

Voltage V1

17 adjustment internal

Selects the internal resistor ratio.

Set the lower 3 bits.

0

1

0

resistance ratio set

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ML9058E

DBn

No

18

Operation

Comment

7 6 5 4 3 2 1 0

A0 RD WR

Sets a 6-bit data in the

electronic potentiometer

register to adjust the V1

output voltage.

Electronic

Potentiometer

1 0 0 0 0 0 0 1

0

1

0

mode set

Electronic

potentiometer

Electronic

* * Electronic

(2-byte command)

potentiometer

register set

potentiometer

value

OFF

ON

1 0 1 0 1 1 0 0

1 0 1 0 1 1 0 1

0

1

0

OFF when DB0 = 0

ON when DB0 = 1

Sets the blinking state.

(2-byte command)

Frame reversal when

DB3 = 0.

Static indicator

19

Static indicator register set

LCD drive method set

* * * * * * State

1 1 0 1 0 * * *

0

1

0

1

0

20

1 1 0 1 1 * * *

Line reversal when DB3 = 1

1)

Sets the number (2-byte

command) of line reversal.

Line reversal number set

* * * Number of lines

Compound command of

Display OFF and Display

all-on.

21 Power save

The “No Operation”

command.

22 NOP

23 Test

1 1 1 0 0 0 1 1

1 1 1 1 * * * *

0

1

0

The command for factory

testing of the IC chip.

*: Invalid data (input: Don’t care, output: Unknown)

Note 1: When the line reversal drive is set, the ML9058E is not used in a multiple chip configuration.

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DESCRIPTIONS OF OPERATION

Display ON/OFF (Write)

This is the command for controlling the turning on or off the LCD panel. The LCD display is turned on when a “1”

is written in bit DB0 and is turned off when a “0” is written in this bit.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

1

DB0

1

Display ON

Display OFF

0

1

0

1

0

1

0

Display Start Line Set (Write)

This command specifies the display starting line address in the display data RAM.

Normally, the topmost line in the display is specified using the display start line set command.

It is possible to scroll the display screen by dynamically changing the address using the display start line set

command.

Line address

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

2

0

1

0

1

0

1

0

62

63

0

1

0

1

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Page Address Set (Write)

This command specifies the page address which corresponds to the lower address when accessing the display data

RAM from the MPU side.

It is possible to access any required bit in the display data RAM by specifying the page address and the column

address.

Page address

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

2

1

0

1

0

1

0

1

0

7

8

0

1

0

1

0

1

0

1

0

1

0

Note: Do not specify values that do not exist as an address.

Column Address Set (Write)

This command specifies the column address of the display data RAM. The column address is specified by

successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented

(by + 1) every time the display data RAM is accessed, the MPU can read or write the display data continuously.

The incrementing of the column address is stopped at the address 83(H).

A0

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

a7

DB2

a6

DB1

a5

DB0

a4

Upper bits

Lower bits

0

a3

a2

a1

a0

Column address

a7

0

a6

a5

a4

0

a3

0

a2

a1

a0

0

1

2

0

1

0

1

0

130

131

1

0

1

0

1

Note: Do not specify values that do not exist as an address.

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ML9058E

Status Read (Read)

A0

0

DB7

DB6

ADC

DB5

DB4

DB3

*

DB2

*

DB1

*

DB0

*

BUSY

ON/OFF

RESET

*: Invalid data

BUSY

When BUSY is '1', it indicates that the internal operations are being made or the LSI is

being reset. Although no command is accepted until BUSY becomes '0', there is no

need to check this bit if the cycle time can be satisfied.

This bit indicates the relationship between the column address and the segment driver.

0: Reverse (SEG131  SEG0); column address 0(H)  83(H)

1: Forward (SEG0  SEG131); column address 0(H)  83(H)

(Opposite to the polarity of the ADC command.)

ADC

This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the

display ON/OFF command.)

ON/OFF

RESET

0: Display ON

1: Display OFF

This bit indicates that the LSI is being reset due to the RES signal or the reset

command.

0: Operating state

1: Being reset

Display Data Write (Write)

This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is

automatically incremented (by +1) after writing the data, the MPU can write successive display data to the display

data RAM.

A0

1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write data

Display Data Read (Read)

This command read the 8-bit data from the specified address of the display data RAM. Since the column address is

automatically incremented (by +1) after reading the data, the MPU can read successive display data from the

display data RAM. Further, one dummy read operation is necessary immediately after setting the column data.

The display data cannot be read out when the serial interface is being used.

A0

1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Read data

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ML9058E

ADC Select (Segment driver direction select) (Write)

Using this command it is possible to reverse the relationship of correspondence between the column address of the

display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver

output pin by the command.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

Forward

Reverse

0

1

0

1

0

1

Forward/Reverse Display Mode (Write)

It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In

this case, the contents of the display data RAM will be retained.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RAM Data

Display on when “H”

Display on when “L”

Forward

Reverse

0

1

0

1

0

1

0

1

LCD Display All-on ON/OFF (Write)

Using this command, it is possible to forcibly turn ON all the dots in the display irrespective of the contents of the

display data RAM. In this case, the contents of the display data RAM will be retained.

This command is given priority over the Forward/reverse display mode command.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

0

DB2

1

DB1

0

DB0

0

All-on display OFF

(Normal display)

All-on display ON

0

1

0

1

0

1

0

1

The power save mode will be entered into when the Display all-on ON command is executed in the display OFF

condition.

LCD Bias Set (Write)

This command is used for selecting the bias ratio of the voltage necessary for driving the LCD device or panel.

LCD bias

1/9 bias

1/7 bias

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

0

DB2

0

DB1

1

DB0

0

1

0

1

0

1

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ML9058E

Read Modify Write (Write)

This command is used in combination with the End command. When this command is issued once, the column

address is not changed when the Display data read command is issued, but is incremented (by +1) only when the

Display data write command is issued. This condition is maintained until the End command is issued. When the

End command is issued, the column address is restored to the address that was effective at the time the

Read-modify-write command was issued last. Using this function, it is possible to reduce the overhead on the

MPU when repeatedly changing the data in special display area such as a blinking cursor.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

End (Write)

This command releases the read-modify-write mode and restores the column address to the value at the beginning

of the mode.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

1

DB2

1

DB1

1

DB0

0

Restored

....

N

N + 1 N + 2

N + m

N

N + 3

Column address

Read-modify-write mode set

End

Reset (Write)

This command initializes the display start line number, column address, page address, common output state,

voltage V1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function,

and also releases the read-modify-write mode or the test mode. This command does not affect the contents of the

display data RAM.

The reset operation is made after issuing the reset command.

The initialization after switching on the power is carried out by the reset signal input to the RES pin.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

1

DB0

0

Common Output State Select (Write)

This command is used for selecting the scanning direction of the common output pins.

Scanning direction

COM0  COM63

COM63  COM0

A0

0

DB7

1

DB6

1

DB5

0

DB4

0

DB3

0

DB2

DB1

DB0

Forward

Reverse

*

0

1

0

1

*: Invalid data

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ML9058E

Power Control Set (Write)

This command set the functions of the power supply circuits.

A0

0

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

0

DB1

DB0

Voltage multiplier circuit: OFF

Voltage multiplier circuit: ON

Voltage adjustment circuit: OFF

Voltage adjustment circuit: ON

Voltage follower circuits: OFF

Voltage follower circuits: ON

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Voltage V1 Adjustment Internal Resistor Ratio Set

This command sets the ratios of the internal resistors for adjusting the voltage V1.

Resistor ratio

A0

0

DB7

0

DB6

0

DB5

1

DB4

0

DB3

0

DB2

DB1

DB0

3.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3.5

0

1

0

4.0

0

1

0

4.5

0

1

0

5.0

0

1

0

5.5

6.0

0

1

0

1

0

Input inhibiting code

0

1

0

Note: Because this LSI has temperature gradient, V1 rises at lower temperatures. When using V1 gain

of 6 times, adjust the built-in electronic potentiometer so that V1 does not exceed 18 V.

Electronic Potentiometer (2-byte command)

This command is used for controlling the LCD drive voltage V1 output by the voltage adjustment circuit of the

internal LCD power supply and for adjusting the intensity of the LCD display.

This is a two-byte command consisting of the Electronic potentiometer mode set command and the Electronic

potentiometer register set command, both of which should always be issued successively as a pair.

 Electronic potentiometer mode set (Write)

When this command is issued, the electronic potentiometer register set command becomes effective.

Once the electronic potentiometer mode is set, it is not possible to issue any command other than the Electronic

potentiometer register set command. This condition is released after data has been set in the register using the

Electronic potentiometer register set command.

A0

0

DB7

1

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

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LAPIS Semiconductor

ML9058E

 Electronic potentiometer register set (Write)

By setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the LCD

drive voltage V1 to one of the 64 voltage levels.

The electronic potentiometer mode is released after some data has been set in the electronic potentiometer register

using this command.



63

62

61

60

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

*

0

1

0

1

0

1

0

1

0

1

0

*

*: Invalid data

Set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function.

Sequence of setting the electronic potentiometer register:

Electronic potentiometer mode set



Electronic potentiometer register set

The electronic potentiometer mode is released



Static Indicator (2-byte command)

This command is used for controlling the static drive type indicator display.

Static indicator display is controlled only by this command and is independent of all other display control

commands.

Since the Static indicator ON command is a two-byte command used in combination with the static indictor

register set command, these two commands should always be used together.

(The Static indicator OFF command is a single byte command.)

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ML9058E

 Static indicator ON/OFF (Write)

When the Static indicator ON command is issued, the Static indicator register set command becomes effective.

Once the Static indicator ON command is issued, it is not possible to issue any command other than the Static

indicator register set command. This condition is released only after some data is written into the register using the

static indicator register set command.

Static indicator

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

0

OFF

ON

0

1

0

1

0

1

0

1

 Static indicator register set (Write)

This command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static

indicator.

Indicator

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

OFF

*

0

1

0

1

0

1

ON(Blinking at about 1sec intervals)

ON(Blinking at about 0.5sec intervals)

ON(Continuously ON)

0

*: Invalid data

Sequence of setting the static indicator register:

Static indicator ON

Static indicator register set

The static indicator mode is released

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ML9058E

LCD Drive Method Set (Write)

This command sets the LCD drive method.

 Line reversal drive (2-byte command)/frame reversal drive select

Line or frame reversal drive can be selected as the LCD drive method.

When selecting line reversal drive, which is 2-byte command used with line reversal number set command, be sure

to use both commands successively.

Once line reversal drive is set, commands other than line reversal number set command cannot be used. This state

is released after data is set to the register by line reversal number set command.

The frame reversal set command is a single byte command.

LCD drive method

Frame reversal

A0

0

DB7

1

DB6

1

DB5

0

DB4

1

DB3

0

DB2

DB1

DB0

*

Line reversal

0

1

0

1

*: Invalid data

 Line reversal number set (Write)

The number of lines is set when the line reversal is set using the LCD drive method set command.

Number of line reversal

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

2

3

4

*

0

1

0

1

0

1

0

31

32

1

0

1

0

*

*: Invalid data

LCD drive method set

Number of line is set in case of line reversal

Note 1: Because the number of line reversal depends on panel size and panel load capacitance, set

the optimum number of lines at the time of ES evaluation.

Note 2: When line reversal drive is used, a multiple chip configuration cannot be achieved.

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ML9058E

Power Save (Compound command)

The LSI goes into the power save state when the Display all-on ON command is issued when the LSI is in the

display OFF state, and it is possible to greatly reduce the current consumption in this state. The power save state is

of two types, namely, the sleep state and the standby state, and the LSI goes into the standby state when the static

indicator has been made ON.

The display data and the operating mode just before entering the power save mode are retained in both the sleep

state and the standby state, and also the MPU can access the display data RAM and other registers in these states.

The power save mode is released by issuing the Display all-on OFF command. (See the following figure.)

Static indicator ON

Static indicator OFF

Sleep state

Power save command issue (compound command)

Standby state

Power save OFF command

(Display all-on OFF command)

Standby state released

Sleep state released

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ML9058E

 Sleep state

In this state, all the operations of the LCD display system are stopped and it is possible to reduce the current

consumption to a level near the idle state current consumption unless there are accesses from the MPU. The

internal conditions in the sleep state are as follows:

(1) The oscillator circuit and the LCD power supply are stopped.

(2) All the LCD drive circuits are stopped and the segment and common driver outputs will be at the V_SSlevel.

 Standby state

All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators

operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions

in the standby state are as follows:

(1) The power supply circuit for LCD drive is stopped. The oscillator circuit will be operating.

(2) The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at

the V_SSlevel. The static display section will be operating.

Note: When using an external power supply, stop external power supply at power save start-up.

For example, when providing each level of LCD drive voltage with external voltage divider, add a circuit

for cutting off current flowing through the resistors of the voltage divider when initiating power save.

The ML9058E has LCD display blanking control pin, DOF, which goes "L" at power save start-up. The

external power supply can be stopped using DOF output.

NOP (Write)

This is a No Operation command.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

1

DB0

1

Test (Write)

This is a command for testing the IC chip. Do not use this command. When the test command is issued by mistake,

this state can be released by issuing a NOP command.

A0

0

DB7

1

DB6

1

DB5

1

DB4

1

DB3

*

DB2

*

DB1

*

DB0

*

*: Invalid data

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ML9058E

Initialized Condition Using the RES pin

This LSI goes into the initialized condition when the RES input goes to the “L” level. The initialized condition

consists of the following conditions.

(1) Display OFF

(2) Forward display mode

(3) ADC select: Incremented (ADC command DB0 = “L”)

(4) Power control register: (DB2, DB1, DB0) = (0, 0, 0)

(5) The registers and data in the serial interface are cleared.

(6) LCD Power supply bias ratio: 1/9 bias

(7) All display dots OFF

(8) Read-modify-write: OFF

(9) Static indicator: OFF

Static indicator register: (DB1, DB0) = (0, 0)

(10) Line 1 is set as the display start line.

(11) The column address is set to address 0.

(12) The page address is set to 0.

(13) Common output state: Forward

(14) Voltage V1 adjustment internal resistor ratio register: (DB2, DB1, DB0) = (1, 0, 0)

(15) The electronic potentiometer register set mode is released.

Electronic potentiometer register: (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0 ,0, 0, 0)

(16) The LCD drive method is set to the frame reversal drive.

Line reversal number register: (DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0)

On the other hand, when the reset command is used, only the conditions (8) to (15) above are set.

As is shown in the “MPU Interface (example for reference)”, the RES pin is connected to the Reset pin of the MPU

and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be

reset using the RES pin at the time the power is switched ON. Also, excessive current can flow through this LSI

when the control signal from the MPU is in the high impedance state. It is necessary to take measures to ensure

that the input pins of this LSI do not go into the high impedance state after the power has been switched ON. When

the built-in LCD drive power supply circuit of the ML9058E is not used, it is necessary that RES = “L” when the

external LCD drive power supply goes ON. During the period when RES = “L”, although the oscillator circuit is

operating, the display timing generator would have stopped and the pins CL, FR, FRS, and DOF would have been

tied to the “H” level. There is no effect on the pins DB0 to DB7.

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ML9058E

EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS

When Using the Internal Power Supply Immediately After Power-on

V_DD-V_SSPower supply ON when the pin RES = “L”

Power supply stabilization

Release reset state (RES Pin = “H”)

Initial settings state (default)

*1

Function setting using command input (user settings)

*2

*3

*4

*5

LCD bias set

ADC select

Common output state select

Line reversal/frame reversal drive select

*(a)

Function setting using command input (user settings)

Setting voltage V1 adjustment internal resistor ratio

*6

Electronic potentiometer

*7

Function stabilization using command input (user settings)

Power control set

*8

*(b)

Wait for more than 300 ms

Initial setting state complete

*(a): Carry out power control set within 5ms after releasing the reset state.

The 5ms duration changes depending on the panel characteristics and the value of the smoothing

capacitor. We recommend verification of operation using an actual unit.

*(b): When trace resistance in COG mounting does not exist, wait for over 300 ms.

Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier

capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI.

Notes: Sections to be referred to

*1:

*2:

*3:

*4:

*5:

*6:

Functional description “Reset circuit”

Description of operation “LCD bias set”

Description of operation “ADC select”

Description of operation “Common output state select”

Description of operation “Line reversal/frame reversal drive select”

Functional description “Power supply circuit”, Operation description “Voltage V1 adjustment

internal resistor ratio set”

*7:

*8:

Functional description “Power supply circuit”, Description of operation “Electronic

potentiometer”

Functional description “Power supply circuit”, Description of operation “Power control set”

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When Not Using the Internal Power Supply Immediately After Power-on

V_DD-V_SSPower supply ON when the pin RES = “L”

Power supply stabilization

Release reset state (RES Pin = “H”)

Initial settings state (default)

*1

*(a)

Start power save mode (compound command) *9

Function setting using command input (user settings)

*2

*3

*4

*5

LCD bias set

ADC select

Common output state select

Line reversal/frame reversal drive

select

Function setting using command input (user settings)

Setting voltage V1 adjustment internal resistor ratio

Electronic potentiometer

*6

*7

*9

Power save OFF

*(b)

Function setting using command input (user settings)

Power control set

*8

*(c)

Wait for more than 300 ms

Initial setting state complete

*(a): Enter the power save state within 5ms after releasing the reset state.

*(b): Carry out power control set within 5ms after releasing the power save state.

The 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of

the smoothing capacitor. We recommend verification of operation using an actual unit.

*(c): When trace resistance in COG mounting does not exist, wait for over 300 ms.

Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier

capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI.

Notes: Sections to be referred to

*1: Functional description “Reset circuit”

*2: Description of operation “LCD bias set”

*3: Description of operation “ADC select”

*4: Description of operation “Common output state select”

*5: Description of operation “Line reversal/frame reversal drive select”

*6: Functional description “Power supply circuit”, Description of operation “Voltage V1 adjustment

internal resistor ratio set”

*7: Functional description “Power supply circuit”, Description of operation “Electronic

potentiometer”

*8: Functional description “Power supply circuit”, Description of operation “Power control set”

*9: The power save state can be either the sleep state or the standby state.

Description of operation “Power save (compound command)”

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ML9058E

Data Display

End of initial settings

Function stabilization using command input (user settings)

Display start line set

*10

Function stabilization using command input (user settings)

Page address set *11

Function stabilization using command input (user settings)

Column address set *12

Function stabilization using command input (user settings)

Display data write

*13

No

End of page write?

Yes

No

End of display data write?

Yes

Function stabilization using command input (user settings)

Display ON/OFF *14

End of data display

Notes: Sections to be referred to

*10: Description of operation “Display start line set”

*11: Description of operation “Page address set”

*12: Description of operation “Column address set”

*13: Description of operation “Display data write”

*14: Description of operation “Display ON/OFF”

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ML9058E

Power Supply OFF (*15)

Any state

Function stabilization using command input (user settings)

Power save

*16

V_DD-V_SSPower supply OFF

Notes: Sections to be referred to

*15:

The power supply of this LSI is switched OFF after switching OFF the internal power supply.

Function description “Power supply circuit”

If the power supply of this LSI is switched OFF when the internal power supply is still ON, since

the state of supplying power to the built-in LCD drive circuits continues for a short duration, it

may affect the display quality of the LCD panel. Always follow the power supply switching OFF

sequence.

*16:

*17:

Description of operation “Power save”

After reset is input the power supply may off without obeying above sequence.



Refresh

Although the ML9058E holds operation state by commands, excessive external noise might change the internal

state.

On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from

occurring. It is recommended to use the refresh sequence periodically to control sudden noise.

- LCD bias set

- ADC select

- Display Forwar/Reverse

- Set “LCD ALL-on display“ ON

- Common output state select

Set to the state in which all commands have been set.

- LCD drive mode set

- Static indecator register set

- Voltage V1 adjustment internal

resistance ratio set

- Electronic potnetiometer

- Power control set

- Release the read-modify-write sate(END)

(*18)

- Set “NOP” operation

Test mode release command

(E3(H))

- Display start line set

- Page address set

- Column address set

- Display data write

- Display ON

Refresh RAM

*18: Regardless of presence of setting of “Read-modify-write”commanfd, please carry out “END”

command.

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ML9058E

MPU INTERFACE

The ML9058E series ICs can be connected directly to the 80-series and 68-series MPUs.

Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines.

In addition, it is possible to expand the display area by using the ML9058E series LSIs in a multiple chip

configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals.



80-Series MPU

V_CC

V_DD

A0

A1 to A7

IORQ

A0

C86

CS1

CS2

Decoder

DB0 to DB7

RD

DB0 to DB7

RD

WR

RES

S

P/

V_SS

GND

RESET

V_SS



68-Series MPU

V_CC

V_DD

A0

A1 to A15

VMA

C86

CS1

Decoder

CS2

DB0 to DB7

E

DB0 to DB7

E

W

R/

RES

S

P/

V_SS

GND

RESET

V_SS



Serial interface

V_CC

V_DD

A0

Port 3

Port 4

C86

CS1

CS2

Port 5

Can be tied to

either level.

Port1

Port2

RES

SI

SCL

RES

S

P/

GND

V_SS

RESET

V_SS

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ML9058E

PAD CONFIGURATION

Pad Layout

Chip Size : 9.164  2.982 mm

308

149

309

148

105

347

1

104

Pad Coordinates

Pad No.

Pad Name

DUMMY

DUMMY-B

V_SS

X (µm)

-4462.5

-4377.5

-4292.5

-4207.5

-4122.5

-4037.5

-3952.5

-3867.5

-3782.5

-3697.5

-3612.5

-3527.5

-3442.5

-3357.5

-3272.5

-3187.5

-3102.5

-3017.5

-2932.5

-2847.5

Y (µm)

-1376.0

Pad No.

21

Pad Name

CS1

CS2

V_DD

X (µm)

-2762.5

-2677.5

-2592.5

-2507.5

-2422.5

-2337.5

-2252.5

-2167.5

-2082.5

-1997.5

-1912.5

-1827.5

-1742.5

-1657.5

-1572.5

-1487.5

-1402.5

-1317.5

-1232.5

-1147.5

Y (µm)

-1376.0

1

2

22

3

23

4

24

RES

A0

5

25

6

26

V_SS

7

27

WR

8

28

RD

9

29

V_DD

10

11

12

13

14

15

16

17

18

19

20

DUMMY-B

TEST1

30

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DUMMY-B

V_DD

31

32

33

34

35

FRS

36

FR

37

CL

38

DOF

39

V_SS

40

V_DD

Note: Leave DUMMY and DUMMY-B pads open.

Do not run traces around. Run traces through DUMMY and DUMMY-B pads individually, not in

common.

59/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

Pad No.

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

Pad Name

X (µm)

-1062.5

-977.5

-892.5

-807.5

-722.5

-637.5

-552.5

-467.5

-382.5

-297.5

-212.5

-127.5

-42.5

Y (µm)

-1376.0

Pad No.

81

Pad Name

V1

X (µm)

2337.5

2422.5

2507.5

2592.5

2677.5

2762.5

2847.5

2932.5

3017.5

3102.5

3187.5

3272.5

3357.5

3442.5

3527.5

3612.5

3697.5

3782.5

3867.5

3952.5

4037.5

4122.5

4207.5

4292.5

4443.0

Y (µm)

-1376.0

-1049.9

-997.9

V_DD

82

V1

V_DD

83

V2

V_DD

84

V2

V_IN

85

V3

V_IN

86

V3

V_IN

87

V4

V_IN

88

V4

V_IN

89

V5

V_SS

90

V5

V_SS

91

VR

V_SS

92

VR

V_SS

93

V_DD

V_SS

42.5

94

M/S

V_SS

127.5

95

CLS

V_SS

212.5

96

V_SS

V_OUT

VC6+

VC4+

VS2-

VS1-

VC5+

VC3+

V_SS

297.5

97

C86

382.5

98

P/S

467.5

99

V_DD

552.5

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

DUMMY

V_SS

637.5

722.5

IRS

807.5

V_DD

892.5

DUMMY

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM24

977.5

1062.5

1147.5

1232.5

1317.5

1402.5

1487.5

1572.5

1657.5

1742.5

1827.5

1912.5

1997.5

2082.5

2167.5

2252.5

-945.9

-893.9

-841.9

-789.9

-737.9

-685.9

-633.9

-581.9

-529.9

-477.9

-425.9

V_RS

-373.9

V_RS

-321.9

V_DD

-269.9

60/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

Pad No.

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

Pad Name

X (µm)

4443.0

4128.7

4076.7

4024.7

3972.7

3920.7

3868.7

3816.7

3764.7

3712.7

3660.7

3608.7

3556.7

Y (µm)

-217.9

-165.9

-113.9

-61.9

Pad No.

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Pad Name

DUMMY

SEG0

X (µm)

3504.7

3452.7

3400.7

3348.7

3296.7

3244.7

3192.7

3140.7

3088.7

3036.7

2984.7

2932.7

2880.7

2828.7

2776.7

2724.7

2672.7

2620.7

2568.7

2516.7

2464.7

2412.7

2360.7

2308.7

2256.7

2204.7

2152.7

2100.7

2048.7

1996.7

1944.7

1892.7

1840.7

1788.7

1736.7

1684.7

1632.7

1580.7

1528.7

1476.7

Y (µm)

1352.5

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

-9.9

SEG1

42.1

SEG2

94.1

SEG3

146.1

198.1

250.1

302.1

354.1

406.1

458.1

510.1

562.1

614.1

666.1

718.1

770.1

822.1

874.1

926.1

978.1

1030.1

1082.1

1134.1

1186.1

1352.5

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

COMS1

DUMMY

61/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

Pad No.

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Pad Name

X (µm)

1424.7

1372.7

1320.7

1268.7

1216.7

1164.7

1112.7

1060.7

1008.7

956.7

904.7

852.7

800.7

748.7

696.7

644.7

592.7

540.7

488.7

436.7

384.7

332.7

280.7

228.7

176.7

124.7

72.7

Y (µm)

1352.5

Pad No.

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

Pad Name

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

SEG100

SEG101

SEG102

SEG103

SEG104

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

SEG111

SEG112

SEG113

SEG114

SEG115

SEG116

X (µm)

-655.3

Y (µm)

1352.5

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

-707.3

-759.3

-811.3

-863.3

-915.3

-967.3

-1019.3

-1071.3

-1123.3

-1175.3

-1227.3

-1279.3

-1331.3

-1383.3

-1435.3

-1487.3

-1539.3

-1591.3

-1643.3

-1695.3

-1747.3

-1799.3

-1851.3

-1903.3

-1955.3

-2007.3

-2059.3

-2111.3

-2163.3

-2215.3

-2267.3

-2319.3

-2371.3

-2423.3

-2475.3

-2527.3

-2579.3

-2631.3

-2683.3

20.7

-31.3

-83.3

-135.3

-187.3

-239.3

-291.3

-343.3

-395.3

-447.3

-499.3

-551.3

-603.3

62/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

Pad No.

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

Pad Name

X (µm)

-2735.3

-2787.3

-2839.3

-2891.3

-2943.3

-2995.3

-3047.3

-3099.3

-3151.3

-3203.3

-3255.3

-3307.3

-3359.3

-3411.3

-3463.3

-3515.3

-3567.3

-3619.3

-3671.3

-3723.3

-3775.3

-3827.3

-3879.3

-3931.3

-3983.3

-4035.3

-4087.3

-4139.3

-4443.0

Y (µm)

1352.5

1186.1

1134.1

1082.1

1030.1

978.1

Pad No.

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

Pad Name

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COMS0

DUMMY

X (µm)

-4443.0

Y (µm)

874.1

822.1

770.1

718.1

666.1

614.1

562.1

510.1

458.1

406.1

354.1

302.1

250.1

198.1

146.1

94.1

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

DUMMY

COM32

COM33

COM34

42.1

-9.9

-61.9

-113.9

-165.9

-217.9

-269.9

-321.9

-373.9

-425.9

-477.9

-529.9

-581.9

-633.9

-685.9

-737.9

-789.9

926.1

63/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

ML9058E ALIGNMENT MARK SPECIFICATION 1

Alignment Mark Coordinates

Y

B

E

A

         

X

(0,0)

(0

C

F



D

Alignment mark

X(µm)

–4270.3

4259.7

4455

Y(µm)

A

B

C

D

E

F

1364.5

–1180.9

1368

Coordinate point

–4455

–4458.5

4458.5

–1368

Alignment Mark Construction Layer

A,B,C,D: Metal Layer E,F:Bump Layer

Alignment Mark Specification

Coordinate point

Symbol

a

Parameter

Mark

A,B,C,D

E,F

Size(µm)

34

Alignment mark Width

Alignment mark Size

43

A,B,C,D

E,F

100

98

b

c

A,B,C

D

60

Alignment mark-to-adjacent pad metal Distance (MIN.)

Alignment mark-to-adjacent pad bump Distance (MIN.)

106.6

109.4

77

E

F

b

c

a

b

c

Bump

a

Metal

a

c

b

c

a

Bump

Metal

64/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

ML9058E GOLD BUMP SPECIFICATION

Gold Bump Specification

Symbo

Parameter

Min.

Typ.

Max.

Unit

l

A

B

C

D

Bump Pitch (Min.Section: Segment Section)

Bump Size (Segment Section: Pitch Direction)

Bump Size (Segment Section: Depth Direction)

Bumo-to-Bump Distance

52

29

—

32

—

35

m

114

17

117

20

120

23

(Segment Section: Pitch Direction)

Bump Pitch (Min.Section: Input Section)

Bump Size (Input Section: Pitch Direction)

Bump Size (Input Section: Depth Direction)

Bumo-to-Bump Distance

E

F

85

57

67

22

—

60

70

25

—

63

73

28

m

G

H

(Input Section: Pitch Direction)

I

Bump Size (Figure “L” alignment mark: Length)

Bump Size (Figure “L” alignment mark: Width)

Pad center to Bump center allowable error

Bump Height

95

40

—

12

—

18

50

30

98

43

—

15

—

101

46

2

m

g

J

—

K

18

3

—

L

Bumph Height Dispersion Inside Chip (Range)

Bump Edge Height

3

—

Shear Strength (g)

—

110

70

Bump hardness: High (Hv: 25g load)

Bump hardness: Low (Hv: 25g load)

Hv

 Chip Thickness: 625 15 m

 Chip Size: 9.164mm  2.982mm

Top View and Cross Section View

A

B

Figure “L”

Alignment Mark

Segment

Section

D

Cross Section View

F

E

Input Section

H

65/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

EXAMPLE OF VOLTAGE MULTIPLIER CONNECTION

An example of the 3.5-time voltage multiplier connection is shown below, as a variation of the 4-time voltage

multiplier.

R

V_IN

V_SS

+

V_OUT

VC6+

VC4+

+

VS2–

VC5+

VC3+

+

VS1–

Example of voltage multiplier connection

For the 3.5-time voltage multiplier, V_INshould be in the voltage

range shown below:

4.8V V_IN 5.2V

(V_OUT= 3(V_IN)+(VC3+)  18.33V)

VC3+ should be in the range of (V_IN)/22%.

66/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

REFERENCE DATA

VIN=4.8V

R

VOUT

VIN

VSS

+

C1

R

I LOAD



VC6+



+

R

VC4+

VS2

R

VS1

VC5+

VC3+

C1



+

OPEN

ML9058E Chip

Equivalent circuit to 3-time voltage multiplier with trace resistances external to COG-mounted chip

ML9058E voltage multiplier load characteristics

- Load current dependency at 3-time multiplication

15

14

13

12

11

10

9

R=0Ω

R=100Ω

R=200Ω

Evaluation

Conditions

Tj=90C

Voltage multiplier

Capacitor

C1=1F

VIN=4.8V,3-time

multiplication

8

Only a voltage

multiplier circuit

operates by power

control set command

“2C”

7

6

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Load current ILoad [mA]

67/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

REFERENCE DATA

R

VIN=4.5V

R

VOUT

VIN

VSS

+

C1

R

I LOAD



VC6+



+

C1

R

VC4+

VS2

R

VS1

VC5+

VC3+

C1



+

R

ML9058E Chip

Equivalent circuit to 4-time voltage multiplier with trace resistances external to COG-mounted chip

ML9058E voltage multiplier load characteristics

- Load current dependency at 4-time multiplication

18

Evaluation

Conditions

Tj=90C

17

16

15

14

13

12

11

10

9

Voltage multiplier

Capacitor

C1=1F

VIN=4.5V,4-time

multiplication

Only a voltage

multiplier circuit

operates by power

control set command

“2C”

R=0Ω

R=100Ω

R=200Ω

8

7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Load current ILoad [mA]

68/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

REFERENCE DATA

R

VIN=4.8V

R

VOUT

VIN

VSS

500

+

500

C1

I LOAD



R

VC6+



+

C1

R

VC4+



C1

VS2

R

VS1

VC5+



+

R

VC3+

VC3+=2.4V

ML9058E Chip

Equivalent circuit to 3.5-time voltage multiplier with trace resistances external to COG-mounted chip

ML9058E voltage multiplier load characterisics

-Load current dependency at 3.5-time multiplication

17

Evaluation

Conditions

16

15

14

13

12

11

10

9

Tj=90°C

Voltage Multiplier

Capacitor

C1=1μF

VIN=4.8V

3.5-time

multiplication

Only a voltage

multiplier

circuit operates

by power control set

command

"2C"

R=0Ω

R=100Ω

R=200Ω

8

7

6

5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Load current ILoad [mA]

69/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

EQUIVALENT CIRCUIT FOR EVALUATING POWER-UP STABILIZATION TIME IN COG MOUNTING

VIN=5.0V

C1

C2

200

R

VIN

V1

V2

V3

V4

V5



+

R

VSS

C1

VOUT



+

R

C2

VC6+



+

Dummy

VC4+

C2

R

+

VS2

VS1

VC5+

VC3+

C2

200

R



+

C1



+

OPEN

ML9058E

Chip

3-time voltage multiplier measuring circuit

VIN=4.5V

200

C1

R

V1

VIN



+

R

VSS

C2

C1

V2

V3

V4

VOUT



+



C1

+

R

C2

VC6+



+



+

Dummy

VC4+

R

C1

C2



+

VS2

C2

R

V5



VS1

C1

VC5+



+

R

VC3+

ML9058E

Chip

4-time voltage multiplier measuring circuit

70/76

FEDL9058E-01

LAPIS Semiconductor

REFERENCE DATA

ML9058E

(The rise time until V1-V5 is stabilized when command “2F” is input after power-on in COG mounting.)

3-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VIN=5V, 3-time multiplication, V1=12V, trace resistance external to COG-mounted chip

R=150, Tj=40C to +85C

300

Parameter, smoothing capacitor C2

250

C2=0.47μF

C2=1.0μF

200

150

100

50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Value of voltage multiplier capacitor C1 [F]

4-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VIN=4.5V, 4-time multiplication, V1=12V, trace resistance external to COG-mounted chip

R=150, Tj=40C to +85C

300

250

200

150

100

50

Parameter: smoothing capacitor C2

C2=0.47μF

C2=1.0μF

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Value of voltage multiplier capacitor C1 [F]

71/76

FEDL9058E-01

LAPIS Semiconductor

REFERENCE DATA

ML9058E

(The rise time until V1-V5 is stabilized when command “2F” is input after power-on in COG mounting.)

3-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VIN=5V, 3-time multiplication, Tj=40C to +85C

Voltage multiplier capacitor C1=3.3F, smoothing capacitor C2=1F

300

Parameter: trace resistance external to COG-mounted chip

250

R=100Ω

R=200Ω

200

150

100

50

0

10

10.5

11

11.5

12

12.5

13

13.5

14

14.5

15

V1 Voltage [V]

4-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VIN=4.5V ,4-time multiplication, Tj=40C to +85C

Voltage multiplier capacitor C1=3.3F, smoothing capacitor C2=1F

300

250

200

150

100

50

Parameter: trace resistance external to COG-mounted chip

R=100Ω

R=200Ω

0

10

10.5

11

11.5

12

12.5

13

13.5

14

14.5

15

V1 Voltage [V]

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FEDL9058E-01

LAPIS Semiconductor

ML9058E

EQUVALENT CIRCUIT FOR EVALUATING POWER-UP STABILIZATION TIME IN COG MOUNTING

R

C1

R

VIN

V1

V2



+

VIN=4.8V

C1

R

VSS

C2

R

VOUT



C1

+

R

VC6+

R



+

V3

V4

V5

R

C1

VC4+



VS2

R

VS1

C1

VC5+



+

VC3+

ML9058E

Chip

3.5-time voltage multiplier measuring circuit

73/76

FEDL9058E-01

LAPIS Semiconductor

REFERENCE DATA

ML9058E

(The rise time until V1-V5 is stabilized when command “2F” is input after power-on in COG mounting.)

3.5-time multiplication

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VDD=VIN=4.8V, 3.5-time multiplication, V1=12V, Tj=40°C to +85°C

Trace resistance external to COG-mounted chip R=150,

VC3+ is provided by dividing VIN using resistor R=500

350

Parameter: smoothing capacitor C2

300

250

200

150

100

50

C2=0.47uF

C2=1.0uF

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

C1[F]

Reference value of V1-V5 rise stabilization time in ML9058E COG mounting

Conditions: VDD=VIN=4.8V, 3.5-time multiplication, Tj=40°C to +85°C,

Voltage multiplier capacitor C1=3.3F, smoothing capacitor C2=1F

VC3+ is provided by dividing VIN using resistor R=500Ω

350

300

250

200

150

100

50

Parameter: trace resistance external to COG-mounted chip

R=100Ω

R=200Ω

0

10

10.5

11

11.5

12

12.5

13

13.5

14

14.5

15

V1 Voltage [V]

74/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

REVISION HISTORY

Page

Document No.

Date

April. 13, 2007

Description

Previous Current

Edition

FEDL9058E-01

–

Final edition 1

75/76

FEDL9058E-01

LAPIS Semiconductor

ML9058E

NOTICE

No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS

Semiconductor Co., Ltd.

The content specified herein is subject to change for improvement without notice.

The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be

obtained from LAPIS Semiconductor upon request.

Examples of application circuits, circuit constants and any other information contained herein illustrate the

standard usage and operations of the Products. The peripheral conditions must be taken into account when

designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specified in this document. However, should

you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor

shall bear no responsibility for such damage.

The technical information specified herein is intended only to show the typical functions of and examples of

application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any

license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.

LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such

technical information.

The Products specified in this document are intended to be used with general-use electronic equipment or

devices (such as audio visual equipment, office-automation equipment, communication devices, electronic

appliances and amusement devices).

The Products specified in this document are not designed to be radiation tolerant.

While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the

possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such

as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility

whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the

instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system which

requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat

to human life or create a risk of human injury (such as a medical instrument, transportation equipment,

aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS

Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special

purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales

representative before purchasing.

If you intend to export or ship overseas any Product or technology specified herein that may be controlled

under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit

under the Law.

.

76/76


型号：	ML9058E
厂家：	ROHM
描述：	ML9058E是进行位图显示的点阵图形液晶显示用LSI。在8位微处理器（以下简称“MPU”）的控制下，驱动点阵图形液晶显示面板。由于位图方式的液晶驱动所需的所有功能都已内置在1枚芯片中，因此使用ML9058E可以用更少的芯片数量来实现位图方式的点阵图形液晶显示系统。采用位图方式，显示用RAM的1位数据与显示面板1个点的亮灯和非亮灯相对应，因此可支持汉字显示等需要更高灵活性的显示。1枚芯片最大可构建65 ×132点的图形显示系统。而且，还可以通过使用2枚芯片来扩展显示。但是，使用行反转驱动时不能采用多芯片结构。ML9058E采用的是CMOS工艺。内置RAM，具有低功耗的特点，适用于电池驱动的便携设备的显示应用。ML9058E内置65路公共信号输出和132路段信号输出功能，可用1枚芯片实现65 × 132点的显示。电池驱动微处理器
文件：	总77页 (文件大小：446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML9058E [ROHM]

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