ML7630 [ROHM]

;


型号：	ML7630
厂家：	ROHM
描述：
文件：	总13页 (文件大小：390K)
中文：	中文翻译
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Dear customer

LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1^stday of October,

2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which

LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS

Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.

Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"

and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."

Furthermore, there are no changes to the documents relating to our products other than

the company name, the company trademark, logo, etc.

Thank you for your understanding.

LAPIS Technology Co., Ltd.

October 1, 2020

FEDL7630-02

Published：Nov. 18, 2019

ML7630

13.56MHz wireless charging Rx LSI

 Overview

The ML7630 is a wireless charging Rx LSI using 13.56MHz carrier frequency, which enables to receive 200mW

power wirelessly from a Tx device using the ML7631. The ML7630 also supports the NFC Forum Type3 TAG

functions, and a TAG data is read out by the NFC readers including smartphones and tablets.

The ML7630 is equipped with an I²C slave port for host interface and a 10bit SA-ADC for measuring output

current to control charging current by software. This is an ideal solution for small rechargeable devices such as

headset, ear-pads and wearables.

 Features

 Charging control

−

Charging power output funcion

Charging output(LDO): Setting of output voltage and setting of current limitation

200mW receiving available

−

Abnormaly detection by software control and hardware control

 Communication control

−

NFC Forum Type3 TAG function included

Communication speed: 212kbps (13.56MHz/64)

1kbyte data flash for storing TAG data contents

 Host interface(I²C slave)

−

Normal mode(100kbit/s), Fast mode(400kbit/s) available

Each internal controller and external HOST microcontroller can access register function

 General Port(PORT)

−

Input/Output port×15ch

 Successive approximation type A/D converter(SA-ADC)

−

Resolution 10bit

 Reset

−

Reset by RESET_N port

Power on reset by magnetic field detection

Reset by WDT overflow

 Clock

−

Low speed clock : Built-in RC oscillation (32.768kHz) for internal timer

High speed clock : From magnetic field(13.56MHz) for internal control logic

 Package

WL-CSP34pin

−

1/12

FEDL7630-02

ML7630

 Functional block structure

P02

P03

P05

P10

P11

TEST0

FLASH

Data : 1KByte

TEST1_N

VPP

Other

Circuit

TEST_OUT

P12

P13

Control Logic

P14

P16

RESET_N

P06

Clock

Generator

System Clock

P07

RX0

RX1

SRAM

256Byte

Communication

Analog

Communication

Logic

P01 / SCL_S

P00 / SDA_S

P04 / INT_S

Host I/F

(I²C Slave)

BAT

Power

Output

P15 / AIN0

BAT2

10bit-ADC

P_ANT

WDT

Regulator

LDO1V8

LDO1V5

2/12

FEDL7630-02

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 Pin assignment

（Top View）

P_ANT

TEST0

P03

RESET_N

P07

P06

P10

P13

RX1

RX0

TEST1_N

P05

P02

VPP

P11

TEST_

OUT

VSS3

BAT

VSS1

VSS0

VDD_IO

P01 /

SCL_S

BAT2

LDO1V8

P12

P14

P00 /

SDA_S

LDO1V5

P04 /

INT_S

P15 /

AIN0

VSS4

ISO_V

VSS2

P16

（Bottom View）

P16

VDD_IO

P14

VSS0

VSS1

P13

P06

P10

P07

P15 /

AIN0

TEST_

OUT

P12

P04 /

INT_S

P11

VPP

P02

P05

RESET_N

P03

P00 /

SDA_S

P01 /

SCL_S

VSS2

TEST1_N

ISO_V

LDO1V5

BAT

VSS3

TEST0

VSS4

LDO1V8

BAT2

RX0

RX1

P_ANT

3/12

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 Pin description

● Power ∙ GND ∙ reference voltage pins

In reset

(*1)

I/O

(*2)

Active

level

Process in

not use

PIN No.

Pin name

Description

VSS0

VSS1

VSS2

−

Ground

−

VSS3

VSS4

VDD_IO

LDO1V5

LDO1V8

P_ANT

ISO_V

BAT

−

H(A)

−

Logic IO voltage

−

Core 1.5V voltage output

ADC 1.8V voltage output

−

Rectify output

−

Logic IO voltage (for host communication)

Charging voltage output

−

BAT2

−

Battery voltage monitoring/Flash writing power

GND

● Analog signal pins

In reset

(*1)

I/O

(*2)

Active

level

Process in

not use

PIN No.

Pin name

Description

RX0

RX1

−

Antenna（Plus） / Data receiving

Antenna（Minus） / Data receiving

−

● Reset pin

PIN No.

In reset

(*1)

I/O

(*2)

Supply

power

Active

level

Process in

not use

Pin name

RESET_N

Description

VDD_IO

Reset input

Open

● General pins

Since the settings differ depending on the FW Ver., refer to the application note for details.

In reset

(*1)

I/O

(*2)

Supply

power

Active

level

PIN No.

Pin name

Description

Input/Output port

P00 /

SDA_S

P01 /

SCL_S

P02

I/O

ISO_V

−

HostIF(I²C slave) Data

Input/Output port

HostIF(I²C slave) Clock

Input/Output port

HostIF INToutput

Input/Output port

AD input

I/O

VDD_IO

−

P03

P04 /

INT_S

P05

P06

P07

P10

P11

P12

P13

I/O

ISO_V

−

I/O

I_DA/O

I/O

VDD_IO

ISO_V

VDD_IO

−

I/O

P14

P15 /

AIN0

P16

I_DA/O

I/O

VDD_IO

−

Input/Output port

4/12

FEDL7630-02

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● Test pins

In reset

(*1)

−

I/O

(*2)

I/O

Supply

power

Active

level

−

Process in

PIN No.

Pin name

Description

not use

Open

TEST0

TEST1_N

VPP

VDD_IO

−

For test/For debugger

Power supply for Flash test

Test output port

TEST_OUT

L(A)

VDD_IO

(*1)

In reset state :

Pin state

L(O)

H(O)

L(A)

H(A)

“L” level output

“H” level output

Analog “L” level output

Analog “H” level output

Pull-Up

definition

in reset state

Pull-Down

Floating state

(*2)

I/O : For I/O definition, using under abbreviation

I/O definition

I/O

I_DA/O

Analog input

Analog output

Digital input

Bi-directional pin

Bi-directional pin, Input are digital and analog shared

Digital output

5/12

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 Electrical characteristics

● Absolue maximum ratings

Item

Symbol

VDD_IO Ta=25°C

Condition

Rating

Unit

Power voltage

-0.3 to +6.5

-0.3 to +2.0

-0.3 to +6.5

ISO_V

P_ANT

BAT2

LDO1V5 Ta=25°C

LDO1V8 Ta=25°C

Ta=25°C

Core power voltage

Analog power voltage

Input voltage

VDIN

Ta=25°C, Digital port

Ta=25°C, RX0/RX1

-0.3 to V_DD+0.3

Input current

Ta=25°C, Digital port

Ta=25°C

Ta=25°C, Digital port

Ta=25°C

–

-10 to +10

100

-0.3 to VDD+0.3

-12 to +20

0.9

I_{P_ANT}

VDO

IDO

Tstg

Output voltage

Digital output current

Power dissipation

Storage temperature

-55 to +150

°C

V_DD: Refer to Pin Description table, in case “Supply Power” column equals “VDD_IO”, VDD is VDD_IO voltage and

column equals “ISO_V”, VDD is ISO_V voltage.

● Recommended operating conditions

Item

Symbol

VDD_IO

ISO_V

Condition

Min.

1.8

Typ.

–

Max.

5.5

Unit

Operating voltage

–

P_ANT

Normal

Charging

Normal

Charging

Normal

Charging

2.0

–

0.5

–

-40

-10

5.0

–

+25

5.5

–

+85

+50

°C

Input current

P_ANT

Operating temperature

Ta1

Ta2

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-0.05%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

LDO1V5 outside Capacitor

P_ANT outside Capacitor

LDO1V8 outside Capacitor

VDD_IO outside Capacitor

ISO_V outside Capacitor

Antenna input frequency

C_LDO1V5

C_PANT

C_LDO1V8

C_VDDIO

C_ISOV

–

2.2

μF

0.47

0.1

μF

0.1

μF

Typ

+0.05%

F_ANT

13.56

MHz

● Flash memory operating conditions

Item

Operating temperature (Ambience)

Operating voltage

Write time

Symbol

Condition

Range

Unit

°C

T_OP

write/erase

-20 to +60

2.7 to 5.5

10,000

P_ANT

Write/erase

–

times

–

C_EPD

Erase unit

–

Sector erase

Erase time (Maximum)

Write time

Block erase / Sector erase

100

–

1 word (2 byte)

6/12

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ML7630

● RF charactaristics

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Input Level

Input data amplitude

Communication speed

Load modulation resistance

Symbol

V_RX1

V_RX2

F_RX

R_MOD

Condition

Min.

2.0

–

105

Typ.

–

212

–

Max.

5.5

–

220

Unit

kbps

RX0/RX1

● Power suppycharactaristics

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

V_BAT

V_{BAT_LOAD}45mA load

Condition

Min.

–

V_BAT-0.5

Typ.

5.0

–

Max.

––

–

Unit

BAT pin output voltage

BAT pin Load Characteristic

No load

Refer to the application note for how to set the BAT pin output voltage.

● Notification charactaristics

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

V_PANT1

V_PANT2

Condition

Norma

In case of abnormality notice

Min.

–

Typ.

–

3.0

Max.

5.5

–

Unit

P_ANT limiter

● Oscillation characteristic

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V)

Item

Symbol

f_LCR

Condition

Min.

Typ.

Max.

Unit

Low speed embedded RC

oscillator frequency ^*1

*1 : 1024 cycle average

-5%

32.768

+5%

kHz

● SA-ADC characteristics

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Resolution

–

bit

Integral non-linearity error

Differential non-linearity error

Zero scale error

INL

DNL

ZSE

FSE

LDO1V8=1.8V

-6

–

LSB

LDO1V8=1.8V

–

Full scale error

–

Input impedance

–

1.8

SA-ADC reference voltage

V_REF

LDO1V8=V_REF

–

● Reset characteristics

(VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

P_RST

Condition

Min.

Typ.

Max.

Unit

RESET_N pulse width

–

200

–

μs

RESET_N noise removal

Pulse width

P_NRST

–

0.3

μs

7/12

FEDL7630-02

ML7630

● ACcharacteristics (I²C bus interface: Standard mode 100 kHz)

(VDD_IO/ISO_V=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

f_SCL

–

100

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

4.0

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

4.7

4.0

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

4.7

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

μs

0.25

SDA_S setup time

(P: Stop condition)

–

4.0

4.7

–

μs

Bus free time

● AC characteristics (I²C bus interface: Fast mode 400 kHz)

(VDD_IO/ISO_V=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

f_SCL

–

400

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

0.6

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

1.3

0.6

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

0.6

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

μs

0.1

SDA_S setup time

(P: Stop condition)

–

0.6

1.3

–

μs

Bus free time

Start

condition

Repeated START

condition

Stop

condition

SDA_S

SCL_S

t_BUF

t_SU:STO

t_HD:STA

t_LOWt_HIGH

t_SU:STA

t_SU:DATt_HD:DAT

If powering off ISO_V of this LSI, it disables communications of other devices on the I²C bus.

If there is a power supply of ISO_V of this LSI even if powering off P_ANT of this LSI,

SDA_S/SCL_S maintains Hi-z state.

8/12

FEDL7630-02

ML7630

● IO characteristics

(Unless otherwise specified, VDD_IO=1.8 to 5.5V, P_ANT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

VOH1

IOH=-1.0mA

V_DD-0.5

–

Output voltage 1

(P00-P07, P10-P16)

VOL1

VOL2

IOL=+0.5mA

–

0.4

0.6

0.4

2.7V≤V_DD≤5.5V

IOL=+5.0mA

Output voltage 2

(P00-P07, P10-P16)

(LED pin)

IOL=+2.0mA

Output voltage 3

(SCL_S,SDA_S)

(I²C pin)

IOL3= +3mA (I²Cspec)

(VDD_IO ≥2V, ISO_V≥2V)

VOL3

–

0.4

Output voltage 4

(SCL_S,SDA_S)

(I²C pin)

Output leakage 1

(P00-P07, P10-P16,

SCL_S, SDA_S)

IOL4= +2mA (I²Cspec)

(VDD_IO <2V, ISO_V<2V)

VOL4

–

V_DD×0.2

IOOH1

VOH=V_DD(at high impedance)

A

IOOL1

IIH1

VOL=VSS (at high impedance)

VIH1=V_DD

-1

–

A

–

Input current 1

(RESET_N, TEST1_N)

IIL1

VIL1=VSS

-900

-300

300

–

-20

900

–

IIH2

VIH2=V_DD

Input current 2

(TEST0)

IIL2

VIL2=VSS

-1

IIH3

VIH3=V_DD(In pull down)

VIL3=VSS (In pull up)

VIH3=V_DD(at high impedance)

VIL3=VSS (at high impedance)

–

-15

–

200

-1

IIL3

-200

Input current 3

(P00-P07, P10-P16)

IIH3Z

IIL3Z

VIH1

–

-1

0.7×V_DD

–

Input voltage 1

(RESET_N, TEST0, TEST1_N,

P00-P07, P10-P16)

–

V_DD

0.3×V_DD

VIL1

–

Input pincapacitance

f=10kHz

(RESET_N, TEST0, TEST1_N,

P00-P07, P10-P16)

CIN

Vrms=50mV

Ta=25°C

Voltage supply to the ISO_V

terminal,

–

Leak current

I_ISOV

100

no magnetic field input

V_DD: Refer to Pin Description table, in case “Supply Power” column equals “VDD_IO”, VDD is VDD_IO voltage and

column equals “ISO_V”, VDD is ISO_V voltage.

Typ. standard is at Ta=25°C, VDD_IO=3.0V

9/12

FEDL7630-02

ML7630

 Package dimensions

10/12

FEDL7630-02

ML7630

 Revision historys

Page

Change contents

Document No.

Issue date

Current

edition

PEDL7630-01

FEDL7630-01

FJDL7630-02

Oct. 25, 2016

Mar. 23, 2018

Jan. 15, 2019

–

Preliminary edition 1

–

Final edition 1

Revise IO-pin description

Nov. 18, 2019

Delet Unused block

Add Reset pin category

Rename Other pins to General pins

Added note for application note to general pin

Delete Sample Circuit

(Described in the application note because it depends

on the FW)

Add TOP VIEW

Add description when BAT2 is not used

Change the connection destination of BAT2 to ADC

Revise BAT output voltage description

11/12

FEDL7630-02

ML7630

Notes

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can

break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,

please take safety measures such as complying with the derating characteristics, implementing redundant and fire

prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for

any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate

the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing

circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and examples of

application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property

rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this

document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights

owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,

gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and

consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary

communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and

power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power

control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the

recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.

However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have

no responsibility for any damages arising from any inaccuracy or misprint of such information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no

responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

12/12

ML7630 [ROHM]

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