ML62Q2502 (新产品)

FEDL62Q2500-03

Issue Date: Feb 2, 2023

ML62Q2500 Group

16-bit micro controller

GENERAL DESCRIPTION

ML62Q2500 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU

nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash (Erase

unit:128byte, Write unit:1byte) and rich peripheral functions such as the multiplier/divider, CRC generator, Clock

generator, Timer, General Purpose Ports, UART, Synchronous serial port, I2C bus interface unit(Master, Slave),

Voltage Level Supervisor(VLS), Successive approximation type 12bit A/D converter, Safety function

(IEC60730/60335 Class B) and so on.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline

architecture parallel processing.

The built-in on-chip debug function enables debugging and programming the software. Also, ISP (In-System

Programming) function supports the Flash programming in production line.

The ML62Q2500 Group has products as show in the Table1 with multiple package and memory size

combinations.

Table 1 Product List

32pin

TQFP32

WQFN32

40pin

WQFN40

48pin

TQFP48

WQFN48

Program

memory

Data memory

(RAM)

Data

Flash

128Kbyte

64Kbyte

ML62Q2504

ML62Q2502

ML62Q2524

ML62Q2522

ML62Q2534

ML62Q2532

8Kbyte

4Kbyte

Please see the last 2 pages “Notes for product usage” and “Notes” in this document on use with this product.

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FEDL62Q2500-03

ML62Q2500 Group

FEATURES

 CPU

– 16-bit RISC CPU : nX-U16/100 (A35 core)

– Instruction system : 16-bit length instructions

– Instruction set

: Transfer, arithmetic operations, comparison, logic operations, multiplication/division,

bit manipulations, bit logic operations, jump, conditional jump, call return stack

manipulations, arithmetic shift, and so on

– Built-in On-chip debug function (connect to the Lapis Technolofy on-chip debug emulator)

– Minimum instruction execution time : 1 count of system clock

Approximately 30.5 μs/62.5ns/41.6ns (at 32.768 kHz/16 MHz/24MHz system clock)

 Coprocessor for multiplication and division

– Signed or Unsigned is selectable

Parameter

Multiplication

Division

Expression

16bit × 16bit

32bit ÷ 16bit

32bit ÷ 32bit

Operation time [cycle]

4

8

16

Multiply-accumulate

(non-saturating, non-saturating)

16bit × 16bit + 32bit

4

 Operating voltage and temperature

– Operating voltage

: V_DD= 1.8 to 5.5 V

– Operating temperature : -40 °C to +105 °C

 Flash memory

Parameter

Erase/Write count

Write unit

Program memory area

Data Flash memory area

10,000 cycles

100 cycles

32bit(4byte)

8bit(1byte)

Erase unit

Erase/Write temperature

16Kbyte/1Kbyte

0 °C to +40 °C

all area/128byte

-40 °C to +85 °C

– Background Operation (CPU can work while erasing and rewriting to the Data Flash memory area.)

– The built-in on-chip debug function and ISP (In-System Programming) function enable Flash

programming

This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.

Super Flash® is a registered trademark of Silicon Storage Technology, Inc.

 Data RAM area

– Rewrite unit: 8bit/16bit (1byte/2byte)

– Parity check function is available (interrupt or reset is generatable at Parity error)

 Clock generation circuit

– Low-speed clock (LSCLK)

Internal low-speed RC oscillation (RC32K)

External low-speed clock input (EXT32K)

: Approximately 32.768 kHz

External low-speed crystal oscillation (XT32K) : Approximately 32.768 kHz,

4 selectable crystal oscillation mode

(Tough, Normal, Low power mode, and Ultra low

power mode)

– High-speed clock (HSCLK)

PLL oscillation: 3 selectable oscillation frequency (24MHz ,16MHz and 1MHz) by code option

– Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1.024kHz)

– High-speed time base clock (HTBCLK)

Generates a clock with a period of 2 to 8 times that of HSCLK as a peripheral clock.

 Reset

– System Resets by reset input pin, Power-On Reset, voltage level supervisor (VLS), WDT overflow, WDT

invalid clear, RAM parity error, and PC error (unused ROM area access (instruction access) )

– Software reset by BRK instruction (reset CPU only)

– Reset the peripherals individually/collectively by software

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FEDL62Q2500-03

ML62Q2500 Group

 Power management

– Optimal power management with various standby modes

– STOP/STOP-D mode(All clocks are stopped), HALT-D mode(clocks for System and part of the

periferal block are stopped), HALT/HALT-H mode(clocks for System are stopped)

– HALT-D mode is suitable for long term standby, HALT-H mode is suitable for short term Intermittent

operation standby

– Indivisual clock input controll to the peripheral blocks by software

– High-speed clock frequency(HSCLK) is configurable (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of PLL clock, Max

7steps)

– Clock gear: High-speed system clock frequency is changeable dynamically

(1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of HSCLK, Max 6steps)

 Interrupt controller

– Non-maskable interrupt source : 1 (Internal sources: WDT)

– Maskable interrupt sources

– Four step interrupt levels

– External interrupt ports

: 34 (included the external interrupt 8 sources)

: 8 (selectable from max.24 pins) with sampling filter

and edge(rise, fall, both) selection.

 General-purpose ports (GPIO)

– I/O port : Max. 40 (Including pins for shared functions)

– Input port: Max. 3 (Including one pin for shared on-chip debug and two pins for shared low speed crystal

oscillation)

– Carrier frequency output function (for IR communication)

 Watchdog timer (WDT) : 1 channel

– Overflow period

: 8selectable (7.8，15.6，31.3，62.5，125，500，2000，8000[ms])

– Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow

period) with invalid clear. When disable, Interrupts the first overflow and resets the second overflow.

When enable, reset occurs for the first overflow.

– Selectable WDT operation : select Enable or Disable by code option

– Selectable operation in HALT/HALT-H mode and HALT-D mode(Continue counting/Stop counting)

– Readable WDT counter: WDT counter monitor function

 Low-speed Time base counter(LTBC) : 2 channels

– Generate 8 frequency (128，64，32，16，8，4，2，1[Hz]) internal pulse signals by dividing the Low-speed

clock (LSCLK)

– 4 interrupts are generatable from 8 different frequencys internal pulse signals

– One of internal pulse signals selected to interrupt can be output from general purpose port (TBCO)

 Functional timer : 2 channels

– Various modes (Continuous, One shot, capture, PWM with the same period and different duties, and

complementary PWM output with the dead time)

– Event trigger (external terminal, 16bit timer, functional timer, LTBC, RC1K)

– Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, external

clock)

 16-bit General timers : 6 channels

– Timer output (toggled by overflow)

– Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, LTBC,

RC1K, and external clock)

– Timer X is shared with waiting for the stability of low-speed crystal oscillation

 Synchronous Serial Port : 2 channels (with FIFO: 1channel, without FIFO: 1channel)

– FIFO: 4steps for each transmitting and receiving

– Selectable from Master and Slave

– Selectable from LSB first or MSB first

– Selectable 8-bit length or 16-bit length

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FEDL62Q2500-03

ML62Q2500 Group

 UART (Full-duplex communication mode): 3 channels

– Selectable from 5 to 8bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits,

Positive logic or Negative logic, LSB first or MSB first

– Sampling filter for receiving data and start bit

– Built-in baud rate generator (HSCLK@16MHz: 4800bps to 920kbps, LSCLK: up to 2400bps)

 I²C bus : 2 channels

– Select from Master mode or Slave mode: 1channel. Master mode only: 1channel

– Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)

– 7bit address format

– Master mode: Handshake (Clock synchronization), 10bit slave address format is supported

– Slave mode: Clock stretch function,

 • Successive approximation type 12bit A/D converter (SA-ADC) : input 14 channels

– Conversion time: Min. 1.375μs / ch (When the V_DDis higher than 2.7V and the conversion clock is 16MHz)

– Reference voltages are selectable from VDD pin input voltage or External reference voltage (VREF pin)

– dedicated result register for each channel

– Continuous conversion, Trigger start, Interrupt determining by upper limit or lower limit threshold of

conversion result

 Voltage Level Supervisor (VLS) : 1 channel

– Threshold voltage: 15 selectable (from 1.85V to 4.00V)

– Functional Voltage level detection reset (VLS reset) or Functional Voltage level detection interrupt (VLS0

interrupt) is generatable

– Equipped with single mode / with sampling filter / low consumption operation

 CRC (Cyclic Redundancy Check) generator

– Generation equation: X¹⁶+X¹²+X⁵+1

– Selectable from LSB first or MSB first

– Built-in Automatic program memory CRC calculation mode in HALT mode

 Safety Function

– Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation

stopped

– RAM/SFR guard

– Automatic program memory CRC calculation

– RAM parity error detection

– ROM unused area access reset (instruction access)

– Clock mutual monitoring, WDT counter monitoring

– SA-ADC test

– Communication loop back test (UART, Synchronous serial port, I²C bus(master))

– GPIO test

 Shipping package

Body size (including lead)

[mm × mm]

Pin pitch

[mm]

Package

Product name

32 pin plastic TQFP

48 pin plastic TQFP

32 pin plastic WQFN

40 pin plastic WQFN

48 pin plastic WQFN

7.0 × 7.0 (9.0 × 9.0)

5.0 × 5.0 ( - )

6.0 × 6.0 ( - )

7.0 × 7.0 ( - )

0.80

ML62Q2502/2504-xxxTB

ML62Q2532/2534-xxxTB

ML62Q2502/2504-xxxGD

ML62Q2522/2524-xxxGD

ML62Q2532/2534-xxxGD

0.50

xxx: ROM code number, (NNN: ROM code is blank)

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FEDL62Q2500-03

ML62Q2500 Group

How To Read The Part Number

ML 62 Q 25 3 4 – xxx TB

Package Type

GD

TB

: WQFN

: TQFP

ROM Code Number

NNN : Blank

XXX

: Custom Code Number

Program Memory Size

2

4

: 64KB

: 128KB

Pin Count

0

2

3

: 32

: 40

: 48

Group Name

25

: 2500 Group

Program Memory Type

Q

: Flash Memory

CPU Type

62

: 16bit CPU nX-U16/100

LAPIS Technology Logic Product

Figure 1 Part Number

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FEDL62Q2500-03

ML62Q2500 Group

Main Function List

Table 2 Main Function List

Interrupt Timer

Communication Analog

Part number

ML62Q2502

ML62Q2504

ML62Q2522

ML62Q2524

ML62Q2532

ML62Q2534

32

40

48

24 16

32 19

40 24

3

1

3

8

1

26

6

2

4

1

2

1

3

1

14

1

*¹: Shared with pins for crystal oscillation and debug input.

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FEDL62Q2500-03

ML62Q2500 Group

BLOCK DIAGRAM

CPU（nX-U16/100）

ECSR1～3

DSR/CSR

PC

EPSW1～3

ELR1～3

LR

Multiplier/Divider

(Coprocessor)

GREG

0 ～15

PSW

EA

Timing

Controller

ALU

SP

Program

Memory

（FLASH）

BUS

Controller

Instruction

Decoder

Instruction

Register

TEST1_N

TEST0

On-Chip ICE /

ISP

INT

SCKF0

SDIF0

SDOF0

SSNF0

VDD

VSS

RAM

Power

Circuit

SSIO

Unit

SCLK0

SIN0

Data FLASH

VDDL

SOUT0

FLASH

Controller

Reset

Function

RESET_N

INT

RXD0

TXD0

RXD1

TXD1

RXD2

TXD2

UART

Unit

Interrupt

INT

Clock

Generation

Circuit

LCKO

HCKO

INT

WDT

VLS

INT

SDAU0

SCLU0

Low-speed

RC

Oscillation

I²C Bus

Unit

SDAM0

SCLM0

RC1K

Oscillation

INT

CRC

Generator

16-bit

Timer

TMOn

Low-speed

Crystal

Oscillation

XT0

XT1

Functional

Timer

FTOn

FTOnN

INT

Safety

Function

Low Speed

Time Base

Counter

INT

TBCO

VREF

AINn

SA-ADC

P02~P73

*1

GPIO

(External Interrupt)

P00

PI0,PI1 ^*2

EXI0-7

*1 : Not available as the input port when connecting to the on-chip debug emulator.

*2 : Not available as the input port when connecting to the crystal resonator.

Figure 2 Block Diagram

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FEDL62Q2500-03

ML62Q2500 Group

PIN CONFIGURATION

▉

36 35 34 33 32 31 30 29 28 27 26 25

VREF FTO0 RXD0 SCLK0 EXI4 P30

AIN8 FTO0N TXD0 SOUT0 EXI5 P31

AIN9 FTO1 RXD1 SIN0 EXI6 P32

AIN10 FTO1N TXD1 EXI7 P33

EXI0 P34

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

P13 SSNF0 FTO1N TMOX AIN13

P12 EXI7 SDIF0 FTO1 TMO4

P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO *

P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO

P07 EXI4 TXD1 HCKO *

P06 EXI3 SIN0 RXD1 TMO4

P05 EXI2 SOUT0 TXD0 TMO3

P04 EXI1 SCLK0 RXD0 TMO2

P57 FTO1N

ML62Q253x

EXI1 P35

TQFP48

(Top View)

EXI2 P36

EXI3 P37

AIN11 TMO2 FTO0 SCLU0 P70

AIN12 LCKO TMO3 FTO0N SDAU0 P71

TMO4 FTO1 SCLM0 RXD2 EXI0 P72

* TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73

P56 FTO1

P55 FTO0N

P54 FTO0

1

2

3

4

5

6

7

8

9

10 11 12

▉

*: Supported Carrier frequency output

*: キャリア周波数出力対応

Fig.3-1 48 pin TQFP

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FEDL62Q2500-03

ML62Q2500 Group

36 35 34 33 32 31 30 29 28 27 26 25

▉

VREF FTO0 RXD0 SCLK0 EXI4 P30 37

AIN8 FTO0N TXD0 SOUT0 EXI5 P31 38

AIN9 FTO1 RXD1 SIN0 EXI6 P32 39

AIN10 FTO1N TXD1 EXI7 P33 40

EXI0 P34 41

24 P13 SSNF0 FTO1N TMOX AIN13

23 P12 EXI7 SDIF0 FTO1 TMO4

22 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO *

21 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO

20 P07 EXI4 TXD1 HCKO *

19 P06 EXI3 SIN0 RXD1 TMO4

18 P05 EXI2 SOUT0 TXD0 TMO3

17 P04 EXI1 SCLK0 RXD0 TMO2

16 P57 FTO1N

ML62Q253x

EXI1 P35 42

WQFN48

(Top View)

EXI2 P36 43

EXI3 P37 44

AIN11 TMO2 FTO0 SCLU0 P70 45

AIN12 LCKO TMO3 FTO0N SDAU0 P71 46

TMO4 FTO1 SCLM0 RXD2 EXI0 P72 47

* TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 48

15 P56 FTO1

14 P55 FTO0N

13 P54 FTO0

▉

1

2

3

4

5

6

7

8

9

10 11 12

DIE PAD = N.C.

DIE PAD = NC

*^*:^:S^キu^ャp^リp^アo^周rte^波d^数C^出a^力rr^対ier^応frequency output

Fig.3-2 48 pin WQFN

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FEDL62Q2500-03

ML62Q2500 Group

30 29 28 27 26 25 24 23 22 21

▉

AIN8 FTO0N TXD0 SOUT0 EXI5 P31 31

AIN9 FTO1 RXD1 SIN0 EXI6 P32 32

AIN10 FTO1N TXD1 EXI7 P33 33

EXI0 P34 34

20 P13 SSNF0 FTO1N TMOX AIN13

19 P12 EXI7 SDIF0 FTO1 TMO4

18 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO *

17 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO

16 P07 EXI4 TXD1 HCKO *

ML62Q252x

EXI1 P35 35

WQFN40

(Top View)

EXI2 P36 36

15 P06 EXI3 SIN0 RXD1 TMO4

14 P05 EXI2 SOUT0 TXD0 TMO3

13 P04 EXI1 SCLK0 RXD0 TMO2

12 P55 FTO0N

AIN11 TMO2 FTO0 SCLU0 P70 37

AIN12 LCKO TMO3 FTO0N SDAU0 P71 38

TMO4 FTO1 SCLM0 RXD2 EXI0 P72 39

* TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 40

11 P54 FTO0

▉

1

2

3

4

5

6

7

8

9

10

DIE PAD = N.C.

DIE PAD = NC

*: キャリア周波数出力対応

*: Supported Carrier frequency output

Fig.3-3 40 pin WQFN

10/40

FEDL62Q2500-03

ML62Q2500 Group

▉

24 23 22 21 20 19 18 17

VREF FTO0 RXD0 SCLK0 EXI4 P30

AIN8 FTO0N TXD0 SOUT0 EXI5 P31

AIN9 FTO1 RXD1 SIN0 EXI6 P32

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

P13 SSNF0 FTO1N TMOX AIN13

P12 EXI7 SDIF0 FTO1 TMO4

P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO *

P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO

P07 EXI4 TXD1 HCKO *

ML62Q250x

AIN10 FTO1N TXD1 EXI7 P33

TQFP32

(Top View)

AIN11 TMO2 FTO0 SCLU0 P70

AIN12 LCKO TMO3 FTO0N SDAU0 P71

TMO4 FTO1 SCLM0 RXD2 EXI0 P72

* TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73

P06 EXI3 SIN0 RXD1 TMO4

P05 EXI2 SOUT0 TXD0 TMO3

P04 EXI1 SCLK0 RXD0 TMO2

1

2

3

4

5

6

7

8

▉

*: Supported Carrier frequency output

*: キャリア周波数出力対応

Fig.3-4 32 pin TQFP

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FEDL62Q2500-03

ML62Q2500 Group

24 23 22 21 20 19 18 17

▉

VREF FTO0 RXD0 SCLK0 EXI4 P30 25

AIN8 FTO0N TXD0 SOUT0 EXI5 P31 26

AIN9 FTO1 RXD1 SIN0 EXI6 P32 27

16 P13 SSNF0 FTO1N TMOX AIN13

15 P12 EXI7 SDIF0 FTO1 TMO4

14 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO *

13 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO

12 P07 EXI4 TXD1 HCKO *

ML62Q250x

AIN10 FTO1N TXD1 EXI7 P33 28

WQFN32

AIN11 TMO2 FTO0 SCLU0 P70 29

(Top View)

AIN12 LCKO TMO3 FTO0N SDAU0 P71 30

TMO4 FTO1 SCLM0 RXD2 EXI0 P72 31

* TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 32

11 P06 EXI3 SIN0 RXD1 TMO4

10 P05 EXI2 SOUT0 TXD0 TMO3

9

P04 EXI1 SCLK0 RXD0 TMO2

▉

1

2

3

4

5

6

7

8

DIE PAD = N.C.

DIE PAD = NC

*: キャリア周波数出力対応

*: Supported Carrier frequency output

Fig.3-5 32 pin WQFN

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FEDL62Q2500-03

ML62Q2500 Group

PIN LIST

Table 3 Pin List

1^stfunc. 1^stfunc. 2^ndfunc. 3^rdfunc. 4^thfunc. 5^thfunc. 6^thfunc. 7^thfunc.

Pin No.

Career

frequency

output

Pin name

CLKOUT/

LTBC**

GPI/EXI

ADC

SSIO*/** UART

I²C*

FTM**

Timer

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

XT0

XT1

―

●

PI0/EXI1

PI1

―

EXI0

―

EXI1

EXI2

EXI3

EXI4

EXI5

EXI6

EXI7

―

RXD1

TXD1

―

VDD

VSS

VDDL

RESET_N

TEST1_N

P00/TEST0

P02

―

9

10 10

13 17

P03

P04

P05

P06

P07

P10

P11

P12

P13

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

P52

P53

P54

P55

P56

P57

―

LCKO

―

SCLK0-0 RXD0

SOUT0-0 TXD0

SIN0-0

TMO2

TMO3

TMO4

―

TMO2

TMO3

TMO4

TMOX

―

10 14 18

11 15 19

12 16 20

13 17 21

14 18 22

15 19 23

16 20 24

RXD1

TXD1

―

HCKO

LCKO

―

TBCO

―

TBCO

―

LCKO

―

TBCO

―

●

SCKF0-0 RXD2

SDOF0-0 TXD2

SDIF0-0

FTO0

FTO0N

FTO1

FTO1N

―

●

AIN13 SSNF0-0

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

―

11

12

―

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

VREF

AIN8

AIN9

AIN10

―

AIN11

AIN12

―

17

18

19

20

21

22

23

24

25

26

27

28

―

29

30

31

32

DIE

25

26

27

28

29

30

31

32

33

37

38

39

40

41

42

43

44

11

12

13

14

15

16

34

35

36

45

46

47

48

DIE

―

SCKF0-1 RXD0

SDOF0-1 TXD0

FTO0

FTO0N

―

●

SDIF0-1

SSNF0-1

SCLK0-1

SOUT0-1

SIN0-1

―

SCLK0-2 RXD0

SOUT0-2 TXD0

SIN0-2

―

SCLM0-0 FTO1

SDAM0-0 FTO1N

SCLU0-0

SDAU0-0

―

EXI2

EXI4

EXI5

EXI6

EXI7

EXI0

EXI1

EXI2

EXI3

EXI4

EXI5

―

EXI6

EXI7

―

FTO0

FTO0N

FTO1

FTO1N

―

RXD1

TXD1

―

RXD0

TXD0

―

FTO0

FTO0N

FTO1

FTO1N

―

P60

P61

P62

P70

P71

P72

P73

NC

TMO2

TMO3

TMO4

TMO2

TMO3

TMO4

TMOX

―

37

38

39

40

DIE

―

SCLU0-1 FTO0

SDAU0-1 FTO0N

EXI0

EXI3

―

RXD2 SCLM0-1 FTO1

TXD2 SDAM0-1 FTO1N

―

*: The SSIO and I²C use with a combination of the same suffix pins.

**: Assign each function; SCLK0/SCKF0/FTOn/FTOnN/HCKO, to only one LSI pin each.

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FEDL62Q2500-03

ML62Q2500 Group

PIN DESCRIPTION

“I/O” Field in the below table define the pin type (“-“ : power supply pin, “I” : Input pin, “O” : Out put pin, “I/O” bi-directional pin)

Table 4 Pin Description

Functional pin

Function

Power

LSI pin name I/O

Description

name

Negative power supply pin (-)

Define the potential of this terminal as V_SS

Positive power supply pin (+).

Connect a capacitor C_V(more than 1µF) between this pin and

VSS. Define the potential of this terminal as V_DD.

Power supply for internal logic (internal regulator’s output).

Connect a capacitor C_L(1μF) between this pin and VSS_.

Input/output for testing

－

VSS

VDD

－

VDDL

P00/

TEST0

This pin which is shared with P00 is used as on-chip debug

interface and ISP function and is initialized as pull-up input

mode by the system reset.

TEST0

TEST1_N

RESET_N

PI0, PI1

I/O

Debug

ISP

Input for testing

TEST1_N

RESET_N

XT0, XT1

I

This pin is used as on-chip debug interface and ISP function and

is initialized as pull-up input mode by the system reset.

Reset input.

Applying “L” level shifts the MCU in system reset mode.

Applying “H” level shifts the CPU in program running mode.

No pull-up resistor is installed.

Reset

General purpose input.

- High-impedance (initial value)

- Input without Pull-up

General input port

(GPI)

General purpose input.

- Input with Pull-up (initial value)

- Input without Pull-up

Not available as general inputs when using the on-chip debug

interface or ISP function.

P00/

TEST0

P00

I

P02 ~ P07

P10 ~ P17

P20 ~ P27

P30 ~ P37

P52 ~ P57

P60 ~ P62

P70 ~ P73

P02 ~ P07

P10 ~ P17

P20 ~ P27

P30 ~ P37

P52 ~ P57

P60 ~ P62

P70 ~ P73

General purpose input/output

- High-impedance (initial value)

- Input with Pull-up

- Input without Pull-up

- CMOS output

General port

(GPIO)

I/O

- N channel (N-ch) open drain output

Connect to the Low speed crystal resonator

Connect 32.768kHz crystal resonator and connect capacitors

between the pin and V_SS. When inputting a square wave,

Connect to XT1 pin

XT0

XT1

XT0

XT1

I

Clock Input

I/O

HCKO

LCKO

TBCO

P07 P10

P03 P11 P71

P17 P27 P73

P07 P11

P21 P73

High-speed clock output.

Low-speed clock output.

Low-speed time base counter output.

Clock Output

(7^thfunc.)

O

Career frequency

output

―

Career frequency output

EXI0

EXI1

EXI2

EXI3

EXI4

EXI5

EXI6

EXI7

P00 P72 P34

External Maskable Interrupt 0 Input

External Maskable Interrupt 1 Input

External Maskable Interrupt 2 Input

External Maskable Interrupt 3 Input

External Maskable Interrupt 4 Input

External Maskable Interrupt 5 Input

External Maskable Interrupt 6 Input

External Maskable Interrupt 7 Input

P04 XT0 P35

P05 P27 P36

P06 P73 P37

P07 P30 P52

P10 P31 P53

P11 P32 P60

P12 P33 P61

External Interrupt

(1^stfunc.)

I

P04 P10

P60 P70

TMO2

TMO3

TMO4

TMOX

16bit General Timer 2 output

16bit General Timer 3 output

16bit General Timer 4 output

16bit General Timer X output

P05 P11

P61 P71

16bit General

Timer

O

P06 P12

P62 P72

(6^thfunc.)

P13 P73

14/40

FEDL62Q2500-03

ML62Q2500 Group

Functional pin

name

Function

LSI pin name I/O

Description

Functional Timer0 P output

P10 P20 P30

P54 P70

P11 P21 P31

FTO0

FTO0N

FTO1

Functional Timer0 N output

Functional Timer1 P output

Functional Timer1 N output

P55 P71

P12 P22 P32

Functional Timer

(5^thfunc.)

O

P56 P72

P13 P23 P33

P57 P73

FTO1N

SCLU0

SDAU0

SCLM0

SDAM0

P24 P70

I²C Unit0 Clock input/output

I²C Unit0 Data input/output

I²C Master0 Clock input/output

I²C Master0 Data input/output

I²C Bus

P25 P71

I/O

(4^thfunc.)

P22 P72

P23 P73

P04 P20

I

RXD0

TXD0

RXD1

TXD1

RXD2

TXD2

UART0 received data input

P30 P52

P05 P21

P31 P53

O

UART0 transmission data output

UART1 received data input

P02 P06

P32

I

UART

(3^rdfunc.)

P03 P07

P33

O

UART1 transmission data output

UART2 received data input

P10 P72

P11 P73

I

O

UART2 transmission data output

SCKF0

SDIF0

SDOF0

SSNF0

SCLK1

SIN1

P10 P20

P12 P22

P11 P21

P13 P23

I/O

I

Synchronous serial0 (with FIFO) clock input/output

Synchronous serial0 (with FIFO) data input

Synchronous serial0 (with FIFO) data output

Synchronous serial0 (with FIFO) slave select input/output

Synchronous serial0 clock input/output

Synchronous serial0 data input

O

Synchronous

Serial Port

(2^ndfunc.)

I/O

P04 P24 P30 I/O

P06 P26 P32

P05 P25 P31

I

SOUT1

O

Synchronous serial0 data output

SA-ADC external reference voltage input

Define the potential of reference voltage for SA-ADC as V_REF

VREF

P30

I

Successive

approximation

type A/D converter

(SA-ADC)

P13

P27-P20

P33-P31

P71-P70

AIN0~AIN13

I

SA-ADC channel 0 to 13 analog input

(1^stfunc.)

15/40

FEDL62Q2500-03

ML62Q2500 Group

TERMINATION OF UNUSED PINS

Table 5 shows the processing of unused pins.

Table 5 Termination of unused pins

pin termination

NC

Open

RESET_N

TEST1_N

P00/TEST0

XT0, XT1

Connect to V_DD

Open the pin with the initial condition of pulled-up input mode

P02 ~ P07

P10 ~ P17

P20 ~ P27

P30 ~ P37

P52 ~ P57

P60 ~ P62

P70 ~ P73

Open the pins with the initial condition of Hi-impedance mode.

[Note]



Terminate unused input pins according to the table 5 in order to avoid unexpected through-current in the

pins.

16/40

FEDL62Q2500-03

ML62Q2500 Group

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(V_SS= 0V)

Parameter

Power supply voltage 1

Power supply voltage 2

Input voltage

Symbol

V_DD

Condition

Ta = +25°C

Rating

Unit

V

-0.3 to +6.5

-0.3 to +2.0

-0.3 to V_DD+0.3*¹

-40*²

V_DDL

V_IN

V

Output voltage1

V_OUT1

V

1pin

Total

1pin

Total

“H” level output current

“L” level output current

I_OUTH

I_OUTL

mA

Ta = +25°C

-180*²

+40

+180

Power dissipation

PD

1

W

Storage temperature

T_STG

―

-55 to +150^*3

°C

*1: 6.5V or lower

*2: The current flowing out the LSI through the pin is described in the negative number.

The applicable maximum current is the absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*3: Please observe a storage conditions shown in the document “Board Mounting (soldering)” about the storage conditions until

implementation.

[Note]



Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to

the device.

These are stress ratings only and functional operation of the device at these conditions is not implied.

Recommended Operating Conditions

(V_SS= 0V)

Unit

Parameter

Symbol

Ta

Condition

Range

Operating temperature (Ambient)

Operating temperature (Chip-Junction)

Operating voltage 1

―

-40 to +105

-40 to +115

1.8 to 5.5

30k to 25M

1.0 ±30%

°C

V

Tj

―

V_DD

f_OP

―

V_DD= 1.8 to 5.5V

―

Operating frequency (CPU)

VDDL pin external capacitance

Hz

μF

C_L

17/40

FEDL62Q2500-03

ML62Q2500 Group

Thermal characteristics

The maximum chip-junction temperature, T_jmax, may be calculated using the following equation.

ꢀ

ꢁ ꢂꢃꢄ

= ꢀ

+ ꢅ_{ꢆ ꢂꢃꢄ}× ꢇ

ꢃ ꢂꢃꢄ ꢁꢃ

ꢀ

ꢃ ꢂꢃꢄ

: maximum ambient temperature

ꢅ_{ꢆ ꢂꢃꢄ}∶ LSI maximum power dissipation

: Package junction to ambient thermal resistance

ꢇ

ꢁꢃ

Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to

satisfy the recommended conditions.

The following table shows the each package’s thermal resistance for thermal design reference estimated by

simulation based on the PCB (printed circuit board) conditions define as a below.

Value

Parameter

Symbol

Package type

Unit

L1

L2

WQFN32

TQFP32

WQFN40

WQFN48

TQFP48

50.6

67.6

32.8

31.1

60.2

43.5

61.8

28.9

27.4

56.9

Thermal

resistance

θ_ja

°C/W

PCB conditions:

PCB name

PCB size (L / W / T)

Number of layer

Wiring density

L1

L2

Unit

mm

layer

―

114.3 / 76.2 / 1.6

1

114.3 / 76.2 / 1.6

2

60% (top layer)

60% (top and bottom layer)

Wind condition

No wind (0m/s)

―

18/40

FEDL62Q2500-03

ML62Q2500 Group

Current Consumption

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition

Max.

Parameter

Min.

Typ.^*2

Operating mode

circuit state ^*1

Tj≤

+95^oC

Tj≤

+115^oC

IDD0

IDD1

STOP-D

STOP

All clocks are stopped.

―

0.33

0.4

25

30

55

70

μA

mA

RC32K is oscillating.

XT32K/PLL are stopped.

IDD2-0R

IDD2-0X

IDD2-1R

IDD3

HALT-D

HALT

0.6

28

60

XT32K is oscillating with

LP mode, without

noise-filter.

RC32K/PLL are stopped.

1.0

30

65

RC32K is oscillating.

XT32K/PLL are stopped.

0.9

30

70

1

CPU running in

wait-mode

SYSCLK=32.768kHz

RC32K is oscillating.

XT32K/PLL are stopped.

10

45

75

PLL is oscillating as

PLL1M mode.

HSCLK = 1MHz

IDD4-H1

IDD4-H16

IDD5-H16

IDD5-H24

0.22

0.32

2.4

0.33

0.48

3.24

4.4

0.35

0.5

3.3

4.5

CPU running in

wait-mode

SYSCLK=1MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 1MHz

CPU running in

wait-mode

SYSCLK=16MHz

PLL is oscillating as

PLL16M mode.

HSCLK = 16MHz

CPU running in

wait-mode

PLL is oscillating as

PLL24M mode.

3.5

SYSCLK=24MHz

HSCLK = 24MHz

*1: LTBC0 and WDT is operating except IDD0/1, and all clocks peripheral circuits are stopped by block control. LSCLK1

is stopped. The code option VLMD is "1".

*2: On the condition of VDD=3.0V, Ta=+25°C

19/40

FEDL62Q2500-03

ML62Q2500 Group

Low speed Crystal Oscillation

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Crystal oscillation frequency *¹*²

Symbol

f_XTL

Condition

Min.

―

Typ.

32.768

―

Max.

―

Unit

kHz

s

―

Crystal oscillation start time

T_XTL

―

2

*1: The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance (C_GL/C_DL). As

those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB circuit for matching. Ask

crystal resonator makers for matching and confirm the oscillation characteristics.

*2: The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring capacitance or

parasitic capacitance on the external circuits. Note for designing the external circuit.

- Make the wires on the external circuit as short as possible.

- Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between the external

capacitance and crystal resonator as short as possible.

- Ensure no signal line flowing big current runs near the oscillation circuit.

- Ensure no signal line runs under and near the oscillation circuit.

- Make ground of external capacitance the same as MCU ground V_SSpin and connect them to the ground that has low

variation of current and voltage.

- The quality of oscillation characteristics might be lost depending on operating environment due to moisture absorption of

PCB and condensation of PCB surface, recommended to have measures such as covering the oscillation circuit with

resin.

Low speed Crystal Oscillation external circuit example

XT0

XT1

V_SS

Crystal resonator

(32.768kHz)

C_GL

C_DL

External Clock Input

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

f_EXCK

Condition

Min.

Typ.

Max.

Unit

Typ.

-1.0%

Typ.

+1.0%

Input Frequency

―

32.768

kHz

Input pulse width

t_EXCKW

―

14.5

―

μs

20/40

FEDL62Q2500-03

ML62Q2500 Group

On-chip Oscillator

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

f_RCL1

Condition

Min.

Typ.

Max.

Unit

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +85°C

except HALT-D mode

Typ.

-2.0%

Typ.

+2.0%

Ta= -40 to +105°C

except HALT-D mode

RC32K frequency

32.768

kHz

Typ.

-10%

Typ.

+10%

f_RCL2

HALT-D mode

Typ.

-1.5%

Typ.

+1.5%

Ta= -40 to +85°C

24.002560

16.007168

0.999424

with RC32K

PLL oscillation frequency

PLL oscillation start time

f_PLL1

MHz

ms

Typ.

-2.0%

Typ.

+2.0%

Ta= -40 to +105°C

with RC32K

1

―

2

wake-up from HALT-H

VLMD=0

no temperature variation

between before/after

HALT-H

T_PLL

―

300

μs

Typ.

-15%

Typ.

+15%

Ta= -20 to +85°C

Ta= -40 to +105°C

RC1K frequency

(for WDT)

f_RC1K

1.024

kHz

Typ.

-25%

Typ.

+25%

*: The frequency is the factory default specification. It may vary depending on the board mounting.

21/40

FEDL62Q2500-03

ML62Q2500 Group

Input / Output pin 1

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measur

Parameter

Symbol

VOH1

Condition

Min.

Typ.

Max.

Unit

ing

circuit

IOH1=-10mA

V_DD≥4.5V

IOH1=-1mA

V_DD≥1.8V

IOL1=+10mA

V_DD≥4.5V

IOL1=+1mA

V_DD≥1.8V

V_DD

-1.5

V_DD

-0.5

―

Output voltage1

“H”/“L” level

(all input/output port)

―

1.5

0.5

VOL1

IOL2=+15mA

V_DD≥4.5V

―

0.7

0.5

0.4

V

2

IOL2=+8mA

V_DD≥3.0V

Output voltage2

“L” level

(all input/output port

except P00/TEST0)

When N-ch open

drain output mode

is selected

VOL2

IOL2=+3mA

V_DD≥2.0V

IOL2=+2mA

V_DD≥1.8V

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuri

ng circuit

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

IIH1

IIL1

VIH1=V_DD

VIL1=V_SS

―

1

―

Input current1

(RESET_N)

-1^*1

μA

kΩ

μA

kΩ

IIL2

VIL2=V_SS(pull-up mode) *²

VIH2=V_DD(High impedance mode)

VIL2=V_SS(High impedance mode)

VIL1=V_SS(pull-up mode) *²

VIL1= V_SS(pull-up mode) *²

VIH1=V_DD(High impedance mode)

VIL1=V_SS(High impedance mode)

VIH1=V_DD

-1500^*1-300^*1

-20^*1

80

1

V/IIL2

IIH2Z

IIL2Z

IIL3

3.7

―

10

―

Input current2

(P00/TEST0)

-1^*1

-250^*1

22

―

4

-30^*1

100

―

-2^*1

800

1

Input current3

(all input port except

RESET_N, TEST1N,

P00/TEST0,

V/IIL3

IIH3Z

IIL3Z

IIH4

―

input/output port)

-1^*1

―

μA

―

1

Input current4

(PI0, PI1)

IIL4

VIL1=V_SS

-1^*1

―

0.7

×V_DD

VIH1

VIL1

―

V_DD

Input voltage1

(all input port,

input/output port)

V

5

0.3

×V_DD

―

0

―

Pin capacitance

(all input port,

input/output port)

f = 10kHz

Ta = 25^oC

CPIN

―

10

pF

―

*1: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the

absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*2: Measurement conditions: Typ: V_DD= 3.0V, Max: V_DD= 1.8V, Min: V_DD= 5.5V

22/40

FEDL62Q2500-03

ML62Q2500 Group

Input / Output pin 2

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measu

ring

circuit

Symb

ol

Parameter

Condition

Min.

Typ.

Max.

Unit

mA

μA

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥3.0V

V_DD≥2.0V

V_DD≥1.8V

V_DD≥4.5V

V_DD≥1.8V

-10*³*⁵

-1*³*⁵

-90*⁵

-20*⁵

-180*⁵

-40*⁵

―

“H” level output

current1 *⁶

IOH1

IOH3

IOL1

IOL2

1pin

―

Total of group A or B ^**

(duty ≤ 50%)

―

“H” level output total

current1 *¹*⁴

―

All pin total

(duty ≤ 50%)

―

10*³

1*³

15*³

8*³

3*³

2*³

90

“L” level output

current1 *⁶

1pin

(CMOS output mode)

―

1pin

(N-ch open drain output

mode)

―

“L” level output

current2 *⁶

3

―

Total of group A or B ^**

(N-ch open drain output

mode, duty≤50%)

―

40

―

15

“L” level output total

current *²*⁴

IOL3

―

10

All pin total

―

180

20

(N-ch open drain output

mode, duty≤50%)

―

IOOH

IOOL

VOH=V_DD(High impedance mode)

VOL=V_SS(High impedance mode)

―

+1

―

Output leak

(all input/output port)

-1*⁵

** : Group A is “P02 to P07, P10 to P17 and P52 to P57”, group B is “P20 to P27, P30 to P37, P60 to P62 and P70 to P73”.

*1: Sink-out current from V_DDto the output pin, which can guarantee the device operation.

*2: Sink-in current from the output pin to V_SS, which can guarantee the device operation.

*3: Do not exceed total current.

*4: The total current is on the condition of Duty≤50% (same applies to IOH1).

When the duty ＞50% the total current is calculated by following formula.

Total current = IOL3 x 50/n (When the duty is n%)

<For an example> When IOL3=100mA and n=80%,

Total current = IOL3 x 50/80 = 62.5mA

Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.

Do not apply current larger than Absolute Maximum Ratings.

*5: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the

absolute value.

For example, -1mA means the maximum current 1mA flows out the LSI through the pin.

*6: These values are satisfied with VOH1, VOL1 and VOL2.

23/40

FEDL62Q2500-03

ML62Q2500 Group

I²C Bus Interface

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Condition / Rating

Parameter

Symbol

Standard Mode

Fast Mode

Typ.

1Mbps Mode

Unit

Min.

Typ.

Max.

Min.

1.8

Max.

5.5

Min.

Typ.

Max.

Operating Voltage

V_DD

f_SCL

t_HD:STA

t_LOW

1.8

0

―

5.5

100

―

2.7

0

―

5.5

1000

―

V

kHz

μs

SCL clock frequency

―

0

400

―

SCL hold time

(start/restart condition)

4.0

4.7

4.0

4.7

0

0.6

1.3

0.6

0

0.26

0.5

0.26

0

SCL “L” level time

SCL “H” level time

―

t_HIGH

―

SCL setup time

(restart condition)

t_SU:STA

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

―

SDA hold time

SDA setup time

―

0.25

4.0

4.7

―

0.1

0.6

1.3

0.1

0.26

0.5

―

SDA setup time

(stop condition)

―

Bus-free time

―

When using the I²C as the master, configure the I²C master 0 mode register(I2M0MOD) and I²C bus 0 mode register

(master side, I2U0MOD) so that meet these specifications.

Start

Re-start

Stop

Condition

SDAU0

SDAM0

0.7×V_DD

0.3×V_DD

SCLU0

SCLM0

0.7×V_DD

0.3×V_DD

t_HD:STA

t_LOWt_HIGH

t_SU:STAt_HD:STA

t_SU:DATt_HD:DATt_SU:STOt_BUF

24/40

FEDL62Q2500-03

ML62Q2500 Group

Synchronous Serial Port

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

1^*1

Typ.

Max.

Unit

μs

ns

SCLK input cycle

―

SCLK input pulse width

t_SCYCx 0.4

―

V_DD≥2.4V

V_DD≥1.8V

―

80

50

―

100

200

―

SOUT output delay time

t_SD

―

ns

SIN input setup time

SIN input hold time

t_SS

t_SH

―

ns

―

ns

*1: Need input cycles of SYSCLK x 4 or longer

Master mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

Typ.

SCLK^*2

Max.

Unit

V_DD≥2.4V

250

―

ns

SCLK output cycle

SCLK output pulse width

SOUT output delay time

V_DD≥1.8V

―

500

t_SCYC×0.4

―

t_SCYC×0.6

100

160

―

ns

t_SCYC×0.5

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

―

t_SD

―

120

SIN input setup time

SIN input hold time

t_SS

180

―

80

―

t_SH

100

―

*2: Clock cycle selected by bit12 to 8(S0CK4 to 0) of the serial port 0 mode register (SIO0MOD)

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SCLK

SOUT

SIN

t_SD

0.7×V_DD

0.3×V_DD

t_SS

t_SH

0.7×V_DD

0.3×V_DD

25/40

FEDL62Q2500-03

ML62Q2500 Group

Synchronous Serial Port with FIFO

Slave mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

1^*1

Typ.

Max.

Unit

μs

ns

SCKF input cycle

―

SCKF input pulse width

t_SCYCx 0.4

―

V_DD≥2.4V

V_DD≥1.8V

―

80

50

―

100

200

―

SDOF output delay time

t_SD

―

ns

SDIF input setup time

SDIF input hold time

t_SS

t_SH

―

ns

―

ns

*1: Need input cycles of SYSCLK x 4 or longer

Master mode

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_SCYC

t_SW

Condition

Min.

Typ.

SCLK^*2

Max.

Unit

V_DD≥2.4V

250

―

ns

SCKF output cycle

SCKF output pulse width

SDOF output delay time

V_DD≥1.8V

―

500

t_SCYC×0.4

―

t_SCYC×0.6

100

160

―

ns

t_SCYC×0.5

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

V_DD≥2.4V

V_DD≥1.8V

―

t_SD

―

120

SDIF input setup time

SDIF input hold time

t_SS

180

―

80

―

t_SH

100

―

*2: Clock cycle selected by bit9 to 0(SF0BR9 to 0) of the SIOF0 baud rate register (SF0BRR)

t_SCYC

t_SW

0.7×V_DD

0.3×V_DD

SCKF

SDOF

SDIF

t_SD

0.7×V_DD

0.3×V_DD

t_SS

t_SH

0.7×V_DD

0.3×V_DD

26/40

FEDL62Q2500-03

ML62Q2500 Group

ISP interface

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

t_TCYC

t_TW

Condition

Min.

Typ.

Max.

660

―

Unit

ns

TEST1_N clock input cycle

TEST1_N input pulse width

―

400

―

t_TCYCx 0.4

―

V_DD≥2.7V

V_DD≥1.8V

―

80

50

―

80

TEST0 output delay time

t_TD

―

200

―

TEST0 input setup time

TEST0 input hold time

t_TS

t_TH

―

t_TCYC

t_TW

0.7×V_DD

0.3×V_DD

TEST1_N

t_TD

TEST0

(output)

0.7×V_DD

0.3×V_DD

t_TS

t_TH

0.7×V_DD

0.3×V_DD

TEST0

(input)

EXl0~7 Timer Clock Input

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Symbol

f_EXI

Condition

Min.

―

Typ.

―

Max.

3

Unit

MHz

ns

Input Frequency

Input pulse width

―

t_WEXI

135

―

27/40

FEDL62Q2500-03

ML62Q2500 Group

Reset

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

P_RST

Condition

Min.

10

Typ.

Max.

Unit

Reset pulse width^*1

―

μs

1

RESET_N

VIH1

VIL1

P_RST

[Note]



RESET_N input shorter pulse than the Reset pulse width (P_RST) valid time should be avoided.

The shorter pulse input may cause unexpected behavior.

Slope of Power supply and Power On Reset

(V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power on rising slope

Power on falling slope

S_VR

S_VF

―

60

2

V/ms

V

―

V_PORR

V_PORF

At Power up (rising)

At Power down (falling)

1.50

1.35

1.63

1.60

1.80

1.75

1

Power on reset detection voltage

V

Power on reset minimum pulse

width

P_POR

―

500

13

―

μs

CPU operation start time

(from the release of reset to the

CPU starts to run)

t_CPUI

21

35

ms

―

At Power supply voltage level change

S_VR

At Power supply restart

S_VF

S_VR

V_DD

1.8V

V_PORR

V_PORF

0V

P_POR

t_CPUI

At power on

At Power off

[Note]



If a pulse shorter than the Power on reset minimum pulse width is asserted to V_DD, it may cause the MCU

malfunction. Apply prevent measurement such as bypass capacitors or external reset input, and so on.

Set V_DDto 1.8V or higher before starting CPU operation.



28/40

FEDL62Q2500-03

ML62Q2500 Group

VLS

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Falling

V_VLSF

Rising

V_VLSR

Condition

VLS0LV^*1

Measuring

circuit

Parameter

Symbol

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

3.83

3.53

2.92

2.84

2.72

2.65

2.55

2.43

2.35

2.25

2.15

2.07

1.96

1.87

1.77

3.99

3.68

3.05

2.96

2.84

2.76

2.66

2.54

2.45

2.35

2.24

2.16

2.05

1.95

1.85

4.15

3.83

3.18

3.08

2.96

2.87

2.77

2.65

2.55

2.45

2.33

2.25

2.14

2.03

1.93

3.84

3.55

2.94

2.85

2.74

2.66

2.56

2.45

2.36

2.27

2.16

2.08

1.98

1.89

1.78

4.05

3.74

3.10

3.01

2.89

2.80

2.70

2.58

2.49

2.39

2.28

2.19

2.09

1.99

1.88

4.26

3.93

3.26

3.17

3.04

2.94

2.84

2.71

2.62

2.51

2.40

2.30

2.20

2.09

1.98

VLS threshold

voltage

V_VLSR

V_VLSF

V

1

^*1: Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).

(V_DD=1.8 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Measuring

circuit

Parameter

Symbol

I_VLS

Condition

Min.

Typ.

10

Max.

Unit

nA

VLS current

consumption

―

1

29/40

FEDL62Q2500-03

ML62Q2500 Group

Successive Approximation Type A/D Converter

(V_DD=2.1 to 5.5V, V_SS=0V, Ta=-40 to +105°C, unless otherwise specified)

Parameter

Resolution

Symbol

n_AD

Condition

Min.

Typ.

Max.

Unit

―

－

12

bit

nominal value, V_DD≥ 2.7V, V_REF≥ 2.7V

nominal value, V_DD≥ 2.4V, V_REF≥ 2.4V

nominal value, V_DD≥ 2.1V, V_REF≥ 2.1V

32.768

1.375

－

16000

8000

1000

－

kHz

Conversion clock

f_ADCLK

－

kHz

μs

f

_ADCLK= 16MHz

－

Conversion time

t_CONV

f_ADCLK= 32.768kHz

V_DD≥ V_REF

518.799

－

μs

V

A/D reference voltage

Overall error

V_REF

2.1

-6

V_DD

+6

－

4.5V ≤ V_REF≤ 5.5V

－

LSB

f_ADCLK= 16MHz

2.7V ≤ V_REF

2.4V ≤ V_REF

2.1V ≤ V_REF

2.7V ≤ V_REF

2.4V ≤ V_REF

2.1V ≤ V_REF

-4

－

+4

Integral non-linearity

error

INL_AD

DNL_AD

ZSE

f_ADCLK= 8MHz

f_ADCLK= 1MHz

f_ADCLK= 16MHz

f_ADCLK= 8MHz

f_ADCLK= 1MHz

-7

－

+7

-8

－

+8

-3

－

+3

Differential

non-linearity error

-5

－

+5

-7

－

+7

LSB

f_ADCLK= 16MHz

-8

－

+8

Zero-scale error

Full-scale error

f_ADCLK= 8MHz

f_ADCLK= 1MHz

f_ADCLK= 16MHz

f_ADCLK= 8MHz

f_ADCLK= 1MHz

-8

－

+8

-10

-8

－

+10

+8

－

FSE

-8

－

+8

-10

－

+10

VDD

VDDL

1.0μF

A

RI ≤ 1kΩ

0.1μF

-

1.0μF

AINx

+

Analog input

VSS

The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog

signal source 1kΩ or smaller. Also, putting 0.1µF capacitor on the ADC input pin is recommended to reduce the

noise.

30/40

FEDL62Q2500-03

ML62Q2500 Group

Flash Memory

(V_SS= 0V)

Unit

Parameter

Symbol

T_OP

Condition

Data flash memory, At write/erase

Flash ROM, At write/erase

At write/erase

Range

-40 to +85

0 to +40

+1.8 to +5.5

10000

100

Operating temperature

Operating voltage

°C

V

V_DD

CEPD

CEPP

Data Flash

Maximum rewrite count

times

Program Flash

Block erasing

16K

―

Byte

Data Flash

all area

1K

Erasing unit

Program Flash

Sector erasing

―

Byte

ms

Data Flash

128

Block erasing /

Sector erasing

Erasing time (Max.)

Writing unit

50

Program Flash

Data Flash

4

Byte

1

―

Program Flash

80

40

15

Writing time (Max.)

μs

Data Flash

Data retention period

YDR

rewriting count 100 times

years

31/40

FEDL62Q2500-03

ML62Q2500 Group

Measuring circuit

Measuring circuit 1

VDD

VDDL

C_L

XT0 XT1

Crystal resonator

VSS

C_V: 1.0μF

C_L: 1.0μF

C_DL: 12pF

C_GL: 12pF

(32.768kHz)

A

C_V

C_GL

C_DL

Measuring circuit 2

VIH

Measuring circuit 3

VIH

(*2)

V

(*1)

A

(*1)

VIL

VDD VDDL VSS

VDD

VSS

VDDL

Measuring circuit 4

(*2)

Measuring circuit 5

VIH

A

(*1)

VDD

VSS

VDDL

VIL

VDD

VSS

VDDL

(*1) Input logic circuit to determine the specified measuring conditions

(*2) Measured connecting specified pins

32/40

FEDL62Q2500-03

ML62Q2500 Group

PACKAGE DIMENSIONS

48pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

33/40

FEDL62Q2500-03

ML62Q2500 Group

32pin TQFP Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

34/40

FEDL62Q2500-03

ML62Q2500 Group

48pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

35/40

FEDL62Q2500-03

ML62Q2500 Group

40pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

36/40

FEDL62Q2500-03

ML62Q2500 Group

32pin WQFN Package

(Unit: mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

Note for the package with exposed die pad

The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.

37/40

FEDL62Q2500-03

ML62Q2500 Group

REVISION HISTORY

Page

Document

No.

Date

Description

Current

Edition

FEDL62Q2500-01

FEDL62Q2500-02

Oct. 20, 2022

Nov.9, 2022

-

1st Edition

Corrected typo, corrected appearance

-

19

Corrected typo, HSCLK condition of IDD4-H16

FEDL62Q2500-03

Feb.2, 2023

New addition of Tj≤+95^oC specification of IDD3, IDD4-H1,

IDD4-H16, IDD5-H16 and IDD5-H24

19

38/40

FEDL62Q2500-03

ML62Q2500 Group

Notes for product usage

Notes on this page are applicable to the all LAPIS Technology microcontroller products.

For individual notes on each LAPIS Technology microcontroller product, refer to [Note]

in the chapters of each user's manual.

The individual notes of each user’s manual take priority over those contents in this page if they are different.

1. HANDLING OF UNUSED INPUT PINS

Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or

increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters,

follow the instruction.

2. STATE AT POWER ON

At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage

reaches to the recommended operating condition and "L" level is input to the reset pin.

On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers

and output of the ports are undefined until the power on reset is generated.

Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and

output of the ports.

3. ACCESS TO UNUSED MEMORY

If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed.

4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCT

Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each

microcontroller product.

When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the

apparatus/system which implemented LAPIS Technology microcontroller products.

5. USE ENVIRONMENT

When using LAPIS Technology microcontroller products in a high humidity environment and an environment where dew

condensation, take moisture-proof measures.

39/40

FEDL62Q2500-03

ML62Q2500 Group

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within

the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of

or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without

observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and

malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down

or malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.

You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology

or any third party with respect to LAPIS Technology Products or the information contained in this document (including but

not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS

Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising

out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications

requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative

and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment,

traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems,

etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by

using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability,

such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws

or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export

Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

40/40


型号：	ML62Q2502 (新产品)
厂家：	ROHM
描述：	ML62Q2500系列是内置16bit CPU nX-U16/100、并集成了程序存储器（Flash存储器）、数据存储器（RAM）、Date Flash（擦除单位128Byte，写入单位1Byte）、乘除法运算器、CRC运算器、时钟发生电路、定时器、通用端口、UART、同步串行端口、I2C总线（主/从）、电压电平检测功能（VLS）、高速逐次比较型12位A/D转换器、安全功能（IEC60730/60335 Class B）等丰富外围功能的高性能CMOS 16bit 微控制器。16Bit CPU nX-U16/100可通过流水线架构的并行处理实现一个时钟周期一个指令的高效指令执行。ML62Q2500系列具有片上调试功能，可在开发板上进行软件调试及软件改写。另外还具有ISP（In-System Programming）功能，可轻松实现在量产生产线上的Flash存储器写入。时钟生产线控制器微控制器存储转换器
文件：	总40页 (文件大小：1754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML62Q2502 (新产品) [ROHM]

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