ML5810A [ROHM]
ML5810A是用于工业设备电池组充电/放电高边开关Nch功率MOSFET的栅极驱动器。另外,搭载Pch MOSFET驱动器,可在电池过放电时以低电流进行预充电。;型号: | ML5810A |
厂家: | ROHM |
描述: | ML5810A是用于工业设备电池组充电/放电高边开关Nch功率MOSFET的栅极驱动器。另外,搭载Pch MOSFET驱动器,可在电池过放电时以低电流进行预充电。 电池 开关 栅极驱动 驱动器 |
文件: | 总13页 (文件大小:562K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FEDL5810A-06
9, June. 2023
ML5810A
High-Side Switch Driver IC for Battery Pack
■General Description
ML5810A is charge/discharge high-side switch Nch power MOSFET gate driver for battery pack. ML5810A
assert external input reference voltage(CFS, DFS)+12V(typ) as the voltage for drive by charge pump. And also,
built-in PchMOSFET gate driver for low current precharge in battery over-discharge state.
■Features
•High-side switch Nch power MOSFET gate driver for battery pack protection
•Built-in Pch MOSFET gate driver for low current precharge/predischarge
•80V breakdown voltage applicable to 48V battery system
•Built-in charge pump
•Gate driver for charge/discharge ”H” output voltage
•Gate driver for precharge/predischarge ”L” output voltage
: Reference voltage(CFS, DFS)+10V (min)
: Reference voltage (PCFS)-9V (min)
• Current consumption
• Power supply voltage range
: 210uA(typ), 480uA(max)
+6.5V to +64V
(Absolute Maximum Rating: 80V)
:
• Operating temperature range
• Package
: -40℃ to +105℃
: 20pin TSSOP
• Application
: 12V to 48V Battery pack for industrial
eBikes, Energy Storage Systems (ESS) and
Uninterruptible Power Supplies (UPS)
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether
your application corresponds to such special purposes, please contact your local ROHM sales
representative in advance.
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FEDL5810A-06
ML5810A
■Block Diagram
CPHD
CPLC
CPLD
CPHC
VDD
Charge Pump
VREG
VREG
OSC
PCFS
PCFETON
PC_FET
I/O
CFETON
DFETON
C_FET
CFS
D_FET
DFS
GND
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FEDL5810A-06
ML5810A
■Pin Configuration(Top View)
VDD
NC
1
2
3
4
5
6
20
CFS
C_FET
CPHC
CPLC
PCFS
19
18
17
16
15
14
DFETON
PCFETON
CFETON
TEST_N
PC_FET
CPLD
CPHD
D_FET
7
8
TEST1
TEST2
13
12
9
GND
VREG
10
DFS
11
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FEDL5810A-06
ML5810A
■Pin Description
Pin No.
Pin
I/O
Description
Power supply.
1
VDD
―
Connect an external CR filter for noise rejection.
NC
2
3
―
―
DFETON
I
D_FET enable input.(pulldown resistance:1M)
PCFETON
CFETON
I
I
4
5
PC_FET enable input.(pulldown resistance:1M)
C_FET enable input.(pulldown resistance:1M)
TEST_N input.
6
7
TEST_N
TEST1
I
I
Should be fixed to VDD.
TEST1 input.(pulldown resistance:1M)
Should be fixed to GND.
TEST2 input.(pulldown resistance:1M)
Should be fixed to GND.
TEST2
GND
8
9
I
―
O
Ground.
Built-in 3.3V regurator output. Connect a 4.7F capacitor between this pin
and GND.
VREG
10
Reference voltage input for the D_FET drive charge pump. Connect to the
source pin of the discharge FET.
11
12
DFS
I
Discharge Nch-FET gate drive. Connect to the gate pin of the external
Nch-FET. In the ON state, the DFS level +12V (typ) is asserted.In the OFF
state DFS level is asserted.
D_FET
O
CPHD
CPLD
13
14
O
O
Charge pump capacitor input for D_FET drive. Connect a capacitor which
approximately 8-times of the discharge FET gate capacitance, between the
CPHD and CPLD pins.
Precharge/predischarge Pch-FET gate drive. Connected to the gate pin of
the external Pch-FET. In the ON state, the PCFS level -12V (typ) is asserted,
PC_FET
15
O
I
while the PCFS level is asserted in the OFF state.
Reference voltage input for the PC_FET drive charge pump. Connected to
the source pin of the precharge/predischarge FET.
PCFS
CPLC
CPHC
16
17
18
Charge pump capacitor input for C_FET drive. Connect a capacitor with
approximately twice the gate capacitance of the charge FET between the
CPHC and CPLC pins.
O
O
Charge Nch-FET gate drive. Connected to the gate pin of the external
Nch-FET. In the ON state, the CFS level +12V (typ) is asserted, while the
C_FET
CFS
19
20
O
I
CFS level is asserted in the OFF state.
Reference voltage input for the C_FET drive charge pump. Connected to the
source pin of the charge FET.
4/13
FEDL5810A-06
ML5810A
■Absolute Maximum Ratings
GND=0V, Ta=25°C
Unit
Parameter
Symbol
VDD
Condition
Applied to VDD pin
Rating
Supply voltage
-0.3 to +86.5
V
Applied to CFS,DFS, and
PCFS pins
VIN1
-0.3 to +86.5
-0.3 to VDD+0.3
VDFS-0.5 to +86.5
V
Input voltage
Applied to CFETON,
DFETON,PCFETON,TEST1, and
TEST2,TEST_N pins
Applied to D_FET pin
VDFS=DFS pin voltage
Applied to C_FET pin
VCFS=CFS pin voltage
VIN2
V
V
VOUT1
Output voltage
VOUT2
VOUT3
IOS1
VCFS-0.5 to +86.5
-0.5 to +71.5
5
V
V
Applied to PC_FET pin
VDD=50V
Applied to VREG pin
VDD=50V
Applied to C_FET and D_FET pins
VDD=50V
Applied to PC_FET pin
mA
Short circuit
output current
IOS2
20
mA
IOS3
PD
2
mA
W
Power dissipation
Ta=25℃
2.3
33.7
Package thermal
resistance
θja
JEDEC double-side board mounted
℃/W
Storage
temperature
TSTG
—
-55 to +150
°C
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FEDL5810A-06
ML5810A
■Recommended Operating Conditions
(GND= 0 V)
Parameter
Symbol
VDD
Condition
Applied to VDD pin
No VREG output load
Range
6.5~64
Unit
V
Power supply voltage
Operating temperature
Ta
-40~+105
°C
■Electrical Characteristics
VDD=6.5~64V,GND=0V,Ta=-40 to +105°C, no VREG output load
Parameter
Digital ”H” input
voltage(*1)
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
VIL
―
2.15
—
VDD+0.3
V
Digital ”L” input
voltage(*1)
―
0
—
—
—
12
―
12
―
0.35
130
—
V
µA
µA
V
Digital ”H” input
current(*1)
IIH
VIH = VDD
VIL = GND
—
-2
Digital ”L” input
current(*1)
IIL
IOH=-1.5µA
(VDD*0.95)≧10V
VOH11
VOH12
VOL21
VOL22
10
15
C_FET / D_FET output
voltage( C_FET-CFS,
D_FET-DFS )
IOH=-1.5µA
(VDD*0.93)<10V
VDD*0.93
9
VDD
15
V
IOL=+1.5µA
(VDD*0.8)≧9V
V
PC_FET output voltage
( PCFS-PC_FET )
IOL=+1.5µA
(VDD*0.8)<9V
VDD*0.8
VDD
V
Ccp=80nF,
Rg=1k, Rfs=100,
FET gate capacitance=10nF
From FET-on to 80% of
output voltage VOH11, VOH12
Ccp=80nF,
Rg=1k, Rfs=100,
FET gate capacitance=10nF
From FET-off to 20% of
output voltage VOH11, VOH12
Ccp=80nF,
Rg=1k, Rfs=1k,
FET gate capacitance=1nF
From FET-on to 80% of
output voltage VOL21, VOL22
Ccp=80nF,
Rg=1k, Rfs=1k,
FET gate capacitance=1nF
From FET-off to 20% of
output voltage VOL21, VOL22
C_FET / D_FET
rise time
Tfetr1
Tfetf1
Tfetf2
Tfetr2
―
―
―
―
150
40
350
70
us
us
us
us
C_FET / D_FET
fall time
PC_FET
fall time
110
20
400
70
PC_FET
rise time
Current consumption in
operation
( charge and discharge )
(*2)
CFETON=1 & DFETON=1 &
PCFETON=0
VDD=CFS=DFS=PCFS
IDD1
IDD2
―
―
210
135
480
380
uA
uA
Current consumption in
operation
( precharge or
predischarge )(*2)
CFETON=0 & DFETON=0 &
PCFETON=1
VDD=CFS=DFS=PCFS
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FEDL5810A-06
ML5810A
VDD=6.5V~64V
Output load current<1mA
VREG output voltage
VREG1
FCPCD
FCPPC
3.0
3.3
3.6
9.4
1.2
V
C_FET / D_FET
charge pump frequency
PC_FET
―
―
6.25
0.78
7.8125
0.9766
kHz
kHz
charge pump frequency
*1:Applied to CFETON,DFETON,PCFETON,TEST1,TEST2 and TEST_N pins
*2:Current consumption are sum of VDD,CFS,DFS, and PCFS currents
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ML5810A
■Functional Description
Operating state of ML5810A in each input status of 3 control input(PCFETON, DFETON, CFETON) is
indicated in the following table.
“Charge pump ON, FET stand-by” is in which a charge pump powers up and each FET gate voltage output
enable. The wait time is required at transition from power-up, and please refer to the “■ Timing diagram”
mentioned later for details.
”FET ON state” is the state in which each FET gate voltage is asserted by a relevant pin actually. Please
refer to “■ electrical characteristic” about rise and fall time of gate voltage.
Input
ML5810A
Operating status
PCFETON DFETON
CFETON
0
0
0
Charge pump ON, FET stand-by
FET ON
More than one is ”1”
C_FET and D_FET can be turn on at the same time, but PC_FET is exclusively other FETs and can’t be
turn on at the same time. A truth table of FET ON/OFF is following. As it's shown on the table, CFETON,
DFETON is priority more than PCFETON .
Input
Output
D_FET
OFF
PCFETON DFETON CFETON
PC_FET
OFF
C_FET
OFF
ON
0
0
0
1
1
0
0
1
0
1
0
0 or 1
0 or 1
0 or 1
1
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
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FEDL5810A-06
ML5810A
■Timing diagram
C_FET / D_FET timing
VDD
6.5V
0V
0V
VREG
CFETON
or
DFETON
Twait(*)
0V
CFS+12V(typ) or DFS+12V(typ)
80%
C_FET
or
D_FET
20%
CFS
or
Tfetf1
Tfetr1
DFS
PC_FET timing
VDD
6.5V
0V
VREG
0V
Twait(*)
PCFETON
0V
PCFS
20%
PC_FET
80%
PCFS-12V(typ)
Tfetr2
Tfetf2
(*)Twait must be more than 50ms, when CFETON, DFETON, and PCFETON are set to H from L (0v).
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FEDL5810A-06
ML5810A
■Application Circuit Example
RPC(*3)
PACK(+)
RVDD
CPHC
CPLC
VDD
CVDD
CCP
TEST_N
VREG
CPLD
CPHD
CREG
CCP
RFS2
PCFS
PCFETON
RG2
RFS1
RG1
PC_FET
CFETON
DFETON
TEST1
CFS
C_FET
D_FET
DFS
RG1
TEST2
RFS1
GND
PACK(-)
Recommended Values for External Components
Recommended
Component
value
RVDD (*1)
CVDD
CREG
RG1
510 to 1.5k
2.2F to 10F
4.7F
1k
RFS1
RG2
100
1k
RFS2
RGS
1k
10M
CCP
82nF (*2)
(*1) Recommended RVDD=1.5k for CVDD=2.2F.
(*2) Set 80nF to 100nF, when gate capacitance of external Nch-FET is 10nF.
Set about 8-times of gate capacitance of external Nch-FET to CCP.
(*3) Set RPC according to current of Pch-FET.
Notice: Example of application circuit and the recommended values to parts list shall not guarantee
performance under all conditions. Full and detailed tests are suggested on your actual application.
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FEDL5810A-06
ML5810A
■ Package Dimensions
Causion regarding surface mount type packages
Surface mount type packages are susceptible to applied heat in solder reflow or moisture absorption during
storage. Please contact your local ROHM sales representative for the recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
11/13
FEDL5810A-06
ML5810A
■ Revision History
Page
Previous
Document No.
Issue date
Descriptions
New
―
Version-02
Version-03
Version-03
2019.07.18
2019.07.19
2019.07.25
―
3
English version first edition issued
Error in writing corrected
Error in writing corrected
Error in Pin Configuration corrected (pin
2,8,15,16)
3
5,10
5,10
Version-04
2020.06.05
3
3
■Application Circuit Example
Added TEST1, TEST2, TEST_N pin.
Version-04
2020.06.05
10
10
Version-05
Version-06
2020.10.30
2023.06.09
―
―
Changed Company name and “notes” page.
11
11
Changed "Package Dimensions".
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FEDL5810A-06
ML5810A
Notes
1) The information contained herein is subject to change without notice.
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Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
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