ML5206 [ROHM]
支持3～5节电池、具有电池电压和断线检测、主动电池均衡功能的电池监控保护LSI电池电压检测断线检测主动电池均衡功能省时测试模式;
| 型号： | ML5206 |
| 厂家： | 
ROHM |
| 描述： | 支持3～5节电池、具有电池电压和断线检测、主动电池均衡功能的电池监控保护LSI电池电压检测断线检测主动电池均衡功能省时测试模式 电池 监控 测试 |
| 文件： | 总16页 (文件大小：1115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5206-01
27. Norvember, 2020
ML5206
5 series Cell Li-ion Rechargeable Battery Protection IC with cell balancing function
■ General Description
The ML5206 is a protection IC with cell balancing funcion for the 3- to 5-cell Li-ion rechargeable battery
pack. It detects individual cell overvoltage and battery cell open-wire, and alerts by alarm output signal. And
cell balancing function is built in and it is automatically executed.
■ Features
• 3 to 5 cell high precision overvoltage detection function
Overvoltage detection threshold VOV : 4.0V to 4.4V (5mV step), error: ±25mV (0°C to 60°C)
Overvoltage release threshold VOVR : VOV - 0 to 200mV (10mV step)
error: ±25mV to 35mV (0°C to 60°C)
Overvoltage detection delay time
: 0sec to 5.6 sec(typ)
• Open-wire detection function
Open-wire detection threshold
Open-wire detection sink current
Open-wire detection delay time
: 0.6V(typ)
: 100nA(typ)
: 0sec to 5.6sec(typ)
• Cell balancing function
Cell balancing detection threshold VCB : 4.0V to 4.4V (5mV step), error: ±25mV (0°C to 60°C)
Cell balancing relase threshold VCBR : VCB - 0 to 200mV (10mV step),
error: ±25mV ot 35mV (0°C to 60°C)
Cell balancing current
: 40mA(typ)
Cell balancing detection delay time : 0sec to 5.6sec(typ)
• 3 types of alarm output
Selected from CMOS / Nch open drain / Pch open drain
• Setting number of connected battery cells : defined with part-number
5 cells = ML5206-001, 4 cells =ML5206-001A, 3 cells=ML5206-001B
• Low current consumption
1A(typ), 2A(max） (0°C to 60°C)
• Power supply voltage
: +5V to +25V
• Operating temperature
• Package
: -20°C to +85°C
: 8 pin VSSOP
FEDL5206-01
ML5206
■ Block Diagram
VDD
V5
OV
detector
V4
CBAL
detector
/ALARM
V3
V2
OW
detector
V1
GND
■ Pin Configuration (top view)
1
8
7
6
5
VDD
/ALARM
GND
V1
2
3
4
V5
V4
V3
V2
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FEDL5206-01
ML5206
■ Pin Description
Pin No.
Pin
I/O
Description
Power supply input pin.
1
2
3
4
VDD
V5
―
I
I
I
Battery cell 5 high voltage input pin
V4
Battery cell 5 low voltage input and Battery cell 4 high voltage input pin.
V3
Battery cell 4 low voltage input and Battery cell 3 high voltage input pin.
Battery cell 3 low voltage input and Battery cell 2 high voltage input pin.
Should be connected to GND for the 3 cell series connected battery pack application.
Battery cell 2 low voltage input and Battery cell 1 high voltage input pin.
Should be connected to GND for the 3 or 4 cell series connected battery pack application.
Ground pin.
5
V2
I
6
7
V1
I
GND
―
Alarm signal output pin.
・If CMOS output : Output level is ”L” level(GND level) if overvoltage/ open-wire is
detected, else ”H” level (VDD power supply level). Its reversed setting is possible.
・If Nch open drain output : Output level is ”L” level(GND level) if overvoltage/
open-wire is detected, else ”Hi-Z” level. Its reversed setting is possible.
・If Pch open drain output： Output level is ”H”level (VDD power supply level) if
overvoltage/open-wire is detected, else ”Hi-Z” level. Its reversed setting is possible.
8
/ALARM
O
■ Absolute Maximum Ratings
（GND= 0 V, Ta = 25 °C）
Item
Symbol
VDD
Condition
Applied to VDD pin
Rating
Unit
V
Supply Voltage
－0.3 to +33
Applied to V5 to V1 pins
Vn+1 –Vn pin voltage defference
(note1)
VIN
－0.3 to +6.5
V
V1 – GND pin voltage difference
Applied to between V2-V1 pins.
When cell balancing switch between
V2-V1 pins is OFF.
Input Voltage
VIN2
－0.3 to +7.5
V
VIN5
Applied to V5 pin
－0.3 to + VDD + 6.5
－0.3 to VDD+0.3
V
V
Applied to /ALARM pin (CMOS, Pch
open-drain)
VOUT1
Output Voltage
Applied to /ALARM pin (Nch
open-drain)
VOUT2
－0.3 to +32
V
Cell balancing
current
ICB
IOS
Per every cellbalancing switch
Applied to /ALARM pin
100
10
mA
mA
Short-circuit
output current
Mounted on the JEDEC 4-layer
board
Power dissipation
PD
730
mW
°C
Storage
temperature
TSTG
—
－55 to +150
(note 1) When connecting or disconnecting battery cells, the voltage difference between Vn+1 - Vn pins might
exceed this ratings and the LSI will be destructed.
■ Recommended Operating Conditions
（GND= 0 V）
Unit
Item
Supply Voltage
Operating temperature
Symbol
VDD
TOP
Condition
Range
5 to 25
-20 to +85
—
—
V
°C
3/16
FEDL5206-01
ML5206
■ Electrical Characteristics
● DC Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85°C
Item
Symbol
Condition
Each cell voltage =
3.6V
Min.
Typ.
Max.
Unit
V5 to V1 pins
Open-wire detection
sink current
IVCL
30
100
300
nA
Ta=0 to 60°C
/ALARM pin
“H” output voltage
/ALARM pin
“L” output voltage
/ALARM pin
IOHA
VOLA
IOLKA
IOH=-100A
IOL=100A
VDD-0.2
―
―
―
VDD
0.2
2
V
V
0
Output state is Hi-Z
-2
A
Output leakage current
Internal balance FET
Vn+1 – Vn = 0.3V
VDD – V2 ≧ 6V
VDD=9V to 25V
Internal balance FET
V1=2.1V
V5 to V2 pins
Cell balance
Switch ON resistance
RBL1
3
6
12
91
Ω
Ω
V1 pin
Cell balance
RBL2
38
57
Switch ON resistance
VDD=9V to 25V
● Supply Current Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85°C
Item
Symbol
IDD
Condition
Each cell voltage=3.6V
No output load
Min.
Typ.
Max.
Unit
―
1
2
µA
Ta=0 to 60°C
Current consumption
Each cell voltage=3.6V
No output load
IDDT
―
1
3
µA
Ta=‐20 to 85°C
(Note) VDD pin current consumption. V5 to V1 pin input current, /ALARM pin output current is not included.
4/16
FEDL5206-01
ML5206
● Detection Threshold Chracteristics（Ta=0 to 60°C）
VDD=18V，GND=0 V，Ta=0 to 60°C
Item
Overvoltage detection
threshold
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
―
VOV -25mV
VOV
VOV +25mV
V
VOV-VOVR≦50mV
VOV-VOVR＞50mV
VOVR -25m
VOVR -35m
VOVR
VOVR
VOVR +25m
VOVR +35m
V
V
Overvoltage release
threshold
VOVR
VCB
VCBR
VOW
Cell balancing detection
threshold
―
VCB -25mV
VCB
VCB +25mV
V
VCB-VCBR≦50mV
VB-VCBR＞50mV
VCBR -25m
VCBR -35m
VCBR
VCBR
VCBR +25m
VCBR +25m
V
V
Cell balancing release
threshold
Open-wire detection /
release threshold
Quick test mode
transition
VDD-V5 pin voltage
difference
―
0.5
0.6
0.7
V
VTSTT
Ta=25°C
10
―
―
V
Quick test mode
release
VDD-V5 pin voltage
difference
VTSTR
Ta=25°C
0
―
3
V
● Detection delay time characteristtics（Ta=0 to 60°C）
VDD=18V，GND=0 V，Ta=0 to 60°C
Item
Symbol
tDET
Condition
Min.
300
Typ.
Max.
Unit
Cell voltage monitoring
cycle
―
400
500
ms
Cell voltage monitoring
term
tMON
TBAL
tOV
―
37
262
0
50
350
―
63
438
14
ms
ms
Cell balancing term
Overvoltage detection
delay time setting range
Cell balancing detection
delay time setting range
Open-wire
detection/release delay
time setting range
Quick test mode
Cell voltage monitoring
cycle
―
Defined with
detection cycle
Defined with
detection cycle
cycle
tCB
0
0
―
―
14
14
cycle
cycle
Defined with
detection cycle
tOW
tDETT
Ta=25°C
Ta=25°C
75
37
100
50
125
63
ms
ms
Quick test mode
Cell balancing term
Quick test mode
Overvoltage detection
delay time,
tBALT
Cell balancing detection
delay time,
Defined with
detection cycle
tDLYT
―
―
1
cycle
open-wire
detection/release delay
time
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FEDL5206-01
ML5206
● Code-001: Setting Parameters
VDD=18V，GND=0 V，Ta=0 to 60°C
Item
Overvoltage detection
threshold
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
―
4.275
4.300
4.325
V
Overvoltage release
threshold
VOVR
VCB
VCBR
tOV
―
―
―
4.165
4.075
4.075
3
4.200
4.100
4.100
―
4.235
4.125
4.125
4
V
V
Cell balancing detection
threshold
Cell balancing release
threshold
V
Overvoltage detection
delay time
Defined with
detection cycle
Defined with
cycle
cycle
Cell balancing detection
delay time
tCB
1
―
2
detection cycle
Open-wire
detection/release delay
time
Defined with
detection cycle
tOW
1
―
2
cycle
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FEDL5206-01
ML5206
■ Functional Description
● Selecting the number of battery cells
Number of battery cells is determined by part number.
5-cells=ML5206-001, 4-cells=ML5206-001A, 3-cells=ML5206-001B
● /ALARM output pin
/ALARM pin output status for overvoltage/open-wire detected state.
/ALARM pin output status
Nch open drain
(Code 001)
CMOS
Pch open drain
Overvoltage/open-wire
“L” level
“H” level
“L” level
“H” level
detected state
Undetected state
“Hi-Z” level
“Hi-Z” level
(note 1) /ALARM pin output status for detected state and undetected state can be reversed.
● Handling VDD pin and V1 to V5 pins
Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD input
for stabilization. The resistor value of this noise filter should be adjusted so that the voltage drop across the
resistor is smaller than 0.3 V.
The V1 to V5 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter in
front of each battery cell to prevent false detection.
● Unused pin Treatment
The following table shows how to handle unused pins
Unused pins
Recommended treatment
V1 , V2
Connected to GND pin
● Power-on/Power-off sequence
Battery cells can be connected in any order, but it is recommend that the lowest voltage cell is connected
first, and then connection continues from lower to higher voltage cells, and the highest voltage cell is
connected last. There are no restrictions on the power supply voltage rise time at power-on, and power-off
sequence or power supply voltage fall time at power-off.
It may transition to the open-wire or overvoltage detection state if it takes long time to connect all cells.
7/16
FEDL5206-01
ML5206
● Overvoltage detection function (In case if the overvoltage detection delay time = 3
detection cycles)
After power-on, cell voltage monitoring is started with cell voltage monitoring cycle of tDET =400ms(typ).
When any one or more battery cell voltages reach or exceed the overvoltage detection threshold VOV for
series four times, it detects overvoltage state. And if /ALARM pin output type is CMOS output, /ALARM
pin output changes from “H” level to “L” level.
If the state in which cell voltage of all cell is lower than overvoltage detection threshold VOV is detected
once, detection delay time is not initialized. But if it is detected for series two times, detection delay time
counting is initialized.
After the overvoltage detection, if the cell voltage of all cell is lower than overvoltage release threshold
VOVR, and if /ALARM pin output type is CMOS output, /ALARM pin output changes from “L” level to “H”
level.
Cell monitor pin voltage
VOV
VOVR
difference (Vn+1-Vn)
tDET tDET tDET tDET
tDET
tDET tDET tDET tDET
tDET
tDET tDET
③
①
②
④
tOV
VDD
VDD
/ALARM
Status
0V
Overvoltage is
detected
Overvoltage is not
detected
Overvoltage is not
detected
Detection delay
counting
In case if the overvoltage detection delay counting is not initialized
Cell monitor pin voltage
VOV
VOVR
difference (Vn+1-Vn)
tDET tDET tDET
tDET tDET tDET
tDET tDET
tDET tDET tDET tDET
④
②
③
①
tOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is not
detected
Overvoltage is
detected
overvoltage is not
detected
In case if the overvoltage detection delay counting is initialized
Cell monitor pin voltage
VOV
VOVR
difference (Vn+1-Vn)
tDET tDET tDET
tDET tDET tDET tDET
tDET tDET
tDET tDET tDET tDET
④
①
②
③
①
tOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is not
detected
Overvoltage is
detected
Detection delay
counting
Initialize Detection
delay counting
overvoltage is not
detected
8/16
FEDL5206-01
ML5206
● Cell balancing function (In case if the cell balancing detection delay time = 1 detection
cycle)
After power-on, cell voltage monitoring is started with cell voltage monitoring cycle of tDET=400ms(typ).
When a cell voltage reach or exceed the cell balancing detection threshold VCB for series two times, the
cell balancing switch of the cell is turned on. Not more than one cell balancing switches are turned on in the
same time, but only one cell balancing switche is turned on in the order of V1 to V5.
When a cell voltage of the cell reach or below the cell balancing detection threshold VCB for one time,
the detection delay time counting is initialized.
For monitoring the cell voltage, in the cell monitoring term tMON=50ms(typ), cell balancing switch is
automatically turned-off. The cell balancing switch is turned on during the call balancing term
tBAL=350ms(typ).
If the cell voltage of which cell balancing switch is turned-on is decrease below cell balance release
voltage VCBR, cell balancing switch is turned off.
This cell balancing is operated independently each other.
If the connected cells is less then five, the cell balancing term is as much as the connected cells.
tDET
tBAL
tDET
tBAL
tDET
tBAL
tMON
tMON
tMON
Cell balancing
term
Cell balancing
term
Cell balancing
term
Cell monitoring
term
Cell monitoring
term
V4-V3
Cell monitor pin voltage
V
VCB
VCBR
difference (Vn+1-Vn)
V2-V1
tDET tDET tDET tDET
VOVR
tDET tDET tDET tDET
tDET tDET tDET tDET
①
②
①
②
tCB
tCB
V2
V4
V4
V4
V4
V4
V2
0V
V2
Cell balancing cell
VDD
/ALARM
Status
Charging state
Overcharge is detected
9/16
FEDL5206-01
ML5206
Cell balancing operation is shown below.
In case if the cell balancing release threshold VCBR > overvoltage release threshold VOVR
VOV
Cell balancing is effective
Cell monitor pin
voltage difference
(Vn+1-Vn)
VCB
VOVR
VCBR
VDD
/ALARM
Status
0V
Charging state
Overvoltage is detected
Cell balancing is executed at cells whose voltage is between over voltage detection threshold VOV and cell
balancing detection threshold VCB
.
In case if the overvoltage release threshold VOVR > cell balancing release threshold VCBR
VOV
Cell monitor pin
voltage difference
VCB
(Vn+1-Vn)
VOVR
VCBR
VDD
/ALARM
0V
Status
Overvoltage is detected
Overvoltage is
detected
Overvoltage is
detected
Charging
state
Chargi
state
Charging
state
Charger is connected
Charger is removed
When the charger is connected, charging and discharging by cell balancing is repeated. When the charger
is removed, the cell monitor voltage difference (Vn+1-Vn) will settle in cell balancing release threshold
VCBR
.
10/16
FEDL5206-01
ML5206
● Open-wire detection function (In case if the open-wire detection delay time = 3
detection cycles)
After power-on, cell voltage monitoring is started with cell voltage monitoring cycle of tDET=400ms(typ).
When any one or more battery cell voltages reach or below the open-wire detection threshold VOW for series
four times. It detects open-weire state. And if /ALARM output type is CMOS output, /ALARM pin output
changes from “H” level to “L” level.
If the state in which voltage of all cell is higher than open-wire detection threshold VOW is detected for
once, detection delay time counting is initialized.
After the open-wire detection, if the state in which cell voltage of all cell is higher than open-wire
detection threshold VOW is detected for series four times, and if /ALARM output type is CMOS output,
/ALARM pin output changes from “L” level to “H” level.
If the state in which cell voltage of one or more cell is lower than open-wire detection threshold VOW is
detected for once, detection delay time counting is initialized.
Cell monitor pin voltage
difference (Vn+1-Vn)
VOW
tDET tDET tDET tDET
tDET
tDET tDET tDET
tDET tDET tDET
tDET
②
①
③
④
③
④
②
①
tOW
tOW
VDD
VDD
/ALARM
Status
0V
Open-wire is detected
Open-wire is not detected
Open-wire is not detected
● Quick test mode
In the Quick test mode, cell voltage monitoring cycle is 100ms(typ), cell balancing term is 50ms(typ),
overvoltage/cell balancng detection delay time and open-wire detection/release delay time are set shorter
than one detection cycle..
If the voltage of VDD pin is more than 10V higher than V5 pin, the state changes into this quick test
mode.
For recovering from quick test mode to normal mode, set the difference voltage of V5 and VDD pin lower
than 3V”.
This test mode can decrease the test time after board mounting.
VDD
VTSTT
VDD
VTSTR
V5
V5
Status
Quick test mode
Monitoring state
Monitoring state
11/16
FEDL5206-01
ML5206
● Redefinition of overvoltage / release voltage, cell balancing detection / release voltage
Setting Range and Step
The threshold for Overvoltage detection, Overvoltage Release voltage, Cell Balancing Threshold, and
Cell Balancing Release voltage are ROM code selectable per this table. Since some combinations are
unavailable, contact us for details.
Detection voltage
Overvoltage detection
threshold VOV
Setting range
4.0V to 4.4V
Step voltage
5mV
Overvoltage release threshold
VOVR
V
OV－(0 to 200mV)
4.0V to 4.4V
10mV
5mV
Cell balancing detection
threshold VCB
Cell balancing release
threshold VCBR
VCB－(0 to 200mV)
10mV
● Redefinition of overvoltage / cell balancing Detection Delay time and open-wire
Detection/Relase Delay Time Range
The overvoltage detection delay time and open-wire detection/release delay time are ROM code
selectable per these tables.
Delay time
Settable time (detection cycle)
Unit
Overvoltage
detection delay
time
cell balancing
detection delay
time
Open-wire
detection/relea
se delay time
0
to
1
0
to
1
0
to
1
1
to
2
1
to
2
1
to
2
2
to
3
2
to
3
2
to
3
3
to
4
3
to
4
3
to
4
4
T0
5
4
T0
5
4
T0
5
5
to
6
5
to
6
5
to
6
6
to
7
6
to
7
6
to
7
7
to
8
7
to
8
7
to
8
8
to
9
8
to
9
8
to
9
9
to
10
9
to
10
9
10
to
11
10
to
11
10
to
12
to
13
12
to
13
12
to
13
to
14
13
to
14
13
to
14
to
15
14
to
15
14
to
cycle
cycle
cycle
to
10
11
13
14
15
Delay time
Settable time (monitoring cycle=400ms)
Unit
sec
Overvoltage
detection delay
time
cell balancing
detection delay
time
Open-wire
detection/relea
se delay time
0
to
0.4
0
to
0.4
0
to
0.4
0.4
to
0.8
0.4
to
0.8
0.4
to
0.8
to
1.2
0.8
to
1.2
0.8
to
1.2
to
1.6
1.2
to
1.6
1.2
to
1.6
to
2.0
to
2.4
to
2.8
to
3.2
to
3.6
to
4.0
to
4.4
4.0
to
4.4
4.0
to
4.4
to
4.8
4.4
to
4.8
4.4
to
4.8
to
5.2
4.8
to
5.2
4.8
to
5.2
to
5.6
5.2
to
5.6
5.2
to
2.0
1.6
to
2.4
2.0
to
2.8
2.4
to
3.0
2.8
to
3.6
3.2
to
4.0
3.6
to
sec
sec
2.0
1.6
to
2.4
2.0
to
2.8
2.4
to
3.0
2.8
to
3.6
3.2
to
4.0
3.6
to
0.8
1.2
1.6
2.0
2.4
2.8
3.0
3.6
4.0
4.4
4.8
5.2
5.6
12/16
FEDL5206-01
ML5206
■ Application Circuit Example (5-cell system)
PACK(+)
RVDD
VDD
CVDD
V5
RCELL
RCELL
RCELL
RCELL
RCELL
CCELL
CCELL
CCELL
V4
V3
To Controller
/ALARM
V2
V1
CCELL
CCELL
GND
PACK(-)
■ Recommended values for External Components
Recommended
Component
Value
RVDD
CVDD
RCELL
CCELL
1kΩ
4.7F
51Ω
0.1F
13/16
FEDL5206-01
ML5206
■ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during
storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
14/16
FEDL5206-01
ML5206
■ Revision History
Page
Before
Document No.
FEDL5206-01
Issue date
2020.11.27
Revision Description
After
rvision
―
revision
―
First edition
15/16
FEDL5206-01
ML5206
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within
such usage conditions specified ranges, semiconductors can break down and malfunction due to various
factors. Therefore, in order to prevent personal injury, fire or the other damage from break down or
malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying
with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups
and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems
manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate
the standard operation of semiconductor products and application examples. You are fully responsible for the
incorporation or any other use of the circuits, software, and information in the design of your product or
system. And the peripheral conditions must be taken into account when designing circuits for mass production.
LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties
arising from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of
LAPIS Technology or any third party with respect to LAPIS Technology Products or the information
contained in this document (including but not limited to, the Product data, drawings, charts, programs,
algorithms, and application examples、etc.). Therefore LAPIS Technology shall have no responsibility
whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such
technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication,
consumer systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For
use of our Products in applications requiring a high degree of reliability (as exemplified below), please be sure
to contact a LAPIS Technology representative and must obtain written agreement: transportation equipment
(cars, ships, trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety
equipment, medical systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology
disclaims any and all liability for any losses and damages incurred by you or third parties arising by using the
Product for purposes not intended by us. Do not use our Products in applications requiring extremely high
reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS
Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide
by the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this
document or LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
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