ML22Q626_技术文档

FEDL22Q62X-06

Issue date: Jun 29, 2022

ML22Q623 / ML22Q624 / ML22Q625 / ML22Q626

4-Channel Mixing Speech Synthesis LSI with Built-in Flash Memory

■ Overview

ML22Q623/ML22Q624/ML22Q625/ML22Q626 is a 4-channel mixing speech synthesis LSI with a flash memory for sound

data. It is equipped with a clock synchronous serial interface.

It adopts a HQ-ADPCM^*1, 16-bit D/A converter, and low-pass filter for high sound quality, and incorporates a 1.0W mono

speaker amplifier for driving speakers directly. It is also equipped with a function to detect failure.

The functions necessary for sound output are integrated into a single chip, so that sound functions can be realized simply by

adding this LSI.

● Memory capacity and maximum sound production time (HQ-ADPCM^*1algorithm, registered phrase 1024)

Product Name

Flash memory capacity

Maximum sound production time (sec)

f_s=8.0kHz

f_s=16.0kHz

f_s=32.0kHz

ML22Q623

ML22Q624

ML22Q625

ML22Q626

4Mbits

8Mbits

161

81

40

325

652

162

326

654

81

16Mbits

32Mbits

163

327

1308

Analog Signal

FLASH

MEMORY

16bit

DAC

Speaker

AMP

Filter

MIX

Decode

Volume

HOST

MCU

SPI

Application Circuit

*1

HQ-ADPCM is "Ky's" high-quality audio compression technique.

"Ky's" is a registered trademark of Kyushu Institute of Technology, a

national university corporation.

FEDL22Q62X-06

ML22Q62X

■ Feature

● Sound data

Speech synthesis algorithm:

Sampling frequency:

The algorithm can be specified for each phrase.

HQ-ADPCM/4bit ADPCM2/8bit non-linear PCM /

8bit Straight PCM/16bit Straight PCM

The sampling frequency can be specified for each phrase.

10.7/21.3kHz,

6.4/12.8/25.6kHz,

8.0/16.0/32.0kHz,

11.025/22.05/44.1kHz,

12.0/24.0/48.0kHz

Maximum number of phrases: 4096 Phrases

● Edit ROM function

● Playback function

Repeat function:

Mixing-function:

LOOP command

Up to 4-channel

Volume adjustment function: CVOL command 128 levels (including off-state)

AVOL command 16 levels (including off-state)

● Low-pass filter

● 16-bit D/A converter

● Speaker amplifier:

● Line amplifier output:

Class AB/D 1. 0W 8Ω (SPV_DD=5V, Ta=25 ^OC)

10kΩ driving (Exclusive operation from speaker amplifier output)

● External analog sound input (at the time Class AB speaker amplifier choice, with analog mixing function)

● MCU command interface:

Clock Synchronous Serial Interface

● Failure detection function

Speaker short detection: Speaker pin ground fault detection, speaker pin short detection

Speaker disconnection detection

Thermal detection

Clock error detection

Flash memory error detection

● Clock backup function

● Master clock frequency:

● Power-supply voltage

4.096MHz, 4.000MHz

2.7V to 5.5V ^*1

DV_DD，SPV_DDand IOV_DDcan be set independently. (SPV_DD≥DV_DD

-40 ^OC to +70 ^OC ^*2

)

● Operating temperature range:

● Package:

32-pin TQFP (7mm x 7mm, 0.8mm pitch)

32-pin WQFN (5mm x 5mm, 0.5mm pitch)

ML22Q62X-NNNTB，ML22Q62X-xxxTB (32-pin TQFP) ^*3

ML22Q62X-NNNGD，ML22Q62X-xxxGD (32-pin WQFN) ^*3

● Ordered Part Name:

*1 Handle V_DDRpin in two different ways depending on the voltage range 2.7-3.6V or 3.3-5.5V.

Refer to the "Application Circuit".

*2 The operating time of the speaker amplifier may be limited depending on the average ambient temperature (Ta) used.

*3 The NNN is blanked. xxx represents ROM code number.

2/123

FEDL22Q62X-06

ML22Q62X

■ Pin Configuration (TOP VIEW)

● ML22Q62X-NNNTB/ML22Q62X-xxxTB

25

XTB

V_DDR

16

15

14

13

12

11

(N.C.)

SPP

26

27

28

29

IOV_DD

IRON

IRSI

IRSO

IRSCK

IRCSB

SPM

(TOP VIEW)

TQFP32

RESETB

TEST0

30

31

32

STATUS1

STATUS2

CBUSYB

10

9

(N.C.) Unused pin

3/123

FEDL22Q62X-06

ML22Q62X

● ML22Q62X-NNNGD/ML22Q62X-xxxGD

(N.C.)

SPP 26

25

XTB

V_DDR

16

15

14

13

12

11

10

9

27

28

29

SPM

RESETB

TEST0

IOV_DD

IRON

IRSI

IRSO

IRSCK

IRCSB

(TOP VIEW)

WQFN 32

STATUS1

30

STATUS2 31

32

CBUSYB

(N.C.) Unused pin

4/123

FEDL22Q62X-06

ML22Q62X

■ Pin Description

Initial

value ^*1

—

1,18

3

Symbol

DGND

TEST1

I/O

G

Attribute

Description

-

Digital ground pin.

Output pin for testing.

Leave open.

O

Hi-Z

Synchronous serial interface chip select pin.

4

CSB

I

Negative The SCK and SI inputs are accepted only when this pin is at the "L"

level.

H

5

6

SCK

SI

I

-

Synchronous serial interface clock input pin.

Synchronous serial interface data input pin.

Data is fetched in synchronization with SCK.

Synchronous serial interface data output pin.

When the CSB pin is at an "L" level, data is output in synchronization

with SCK.

When the CSB pin is at an "H" level, this pin enters a high-impedance

state.

Flash memory interface chip select input pin.

L

-

7

9

SO

O

I

-

Hi-Z

H

IRCSB

Negative Input the "H" level during non-access and the "L" level during access.

Setting the IRON pin to "H" enables input.

Flash memory interface serial clock input pin.

Setting the IRON pin to "H" enables input.

Flash memory interface serial data output pin.

Setting the IRON pin to "H" enables output.

Flash memory interface serial data input pin.

Setting the IRON pin to "H" enables input.

10

11

12

IRSCK

IRSO

IRSI

I

O

I

-

H

Hi-Z^*2

L

-

Pin to enable the flash memory interface.

When this bit is set to "L", the flash memory interface pin is disabled. A

pull-down resistor is internally connected to the LSI.

Positive Set this bit to "L" during playback operation using flash memory.

Setting this bit to "H" allows rewriting of the flash memory using the

flash memory interface.

13

IRON

I

L

Set this bit to "H" for onboard rewriting.

*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.

*2 IRON pin "L" setting status

5/123

FEDL22Q62X-06

ML22Q62X

Initial

14

Symbol

IOV_DD

I/O

P

Attribute

-

Description

value ^*1

Flash memory interface power supply pin.

Connect to DV_DDpin even when not using flash memory interface.

Connect a bypass capacitor between this pin and the DGND pin.

3.0V regulator outputs. Used as a power supply for flash memory.

—

Connect a capacitor between this pin and DGND pin as close as

possible.

Connect this pin to the DV_DDpin when DV_DD= 2.7 to 3.6V

Crystal or ceramic resonator connection pin.

When an external clock is used, leave it open and capacitor is not

15

16

V_DDR

XTB

O

-

L

Negative required when a crystal or ceramic resonator is connected.

When using a resonator, connect it as close as possible.

Leave it open when not in use.

H

Crystal or ceramic resonator connection pin.

A feedback resistor of about 1MΩ is built in between the XT pin and

the XTB pin.

17

XT

I

Positive To use an external clock, input from this pin. Delete the capacitor

when a crystal or ceramic resonator is connected.

When using a resonator, connect it as close as possible.

Leave it open when not in use.

L

Digital power supply pin.

Connect a bypass capacitor between this pin and the DGND pin.

2.5V regulator output pin.

Used as internal power supply.

19

20

DV_DD

V_DDL

P

-

—

L

O

-

Connect a capacitor between this pin and DGND pin as close as

possible.

Reference voltage output pin for the built-in speaker amplifier.

Connect a capacitor between this pin and SPGND pin.

Speaker amplifier analog signal input pin.

Initially, input is disabled.

21

22

SG

O

I

-

L

AIN

-

Power supply pin for speaker amplifier.

Connect a bypass capacitor between this pin and the SPGND pin.

Speaker amplifier ground pin.

Positive output pin of the speaker amplifier.

Line amplifier outputs are also available with AMODE command.

Negative output pin of the speaker amplifier.

23

24

26

27

SPV_DD

SPGND

SPP

P

G

O

-

—

-

L

SPM

Hi-Z

*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.

6/123

FEDL22Q62X-06

ML22Q62X

Initial

28

Symbol

I/O

I

Attribute

Negative

Description

value ^*1

Reset input pin.

The LSI is initialized by the "L" level input. After a reset is input, all the

circuits stop operating and enter the power-down state.

At power-on, input an "L" level to this pin. After the power supply

voltage stabilizes, set this pin to an "H" level.

RESETB

(^*2)

A pull-up resistor is internally connected.

Input pin for testing.

29

30

TEST0

I

Positive A pull-down resistor is internally connected.

Fix to the DGND.

L

Status/error output pin 1.

Execute OUTSTAT command to select BUSYB^*3and NCR^*3in each

STATUS1

O

-

H

channel, or errors.

The initial value is BUSYB^*3of channel 0, and output data is "H" level.

Status/error output pin 2.

Execute OUTSTAT command to select BUSYB^*3and NCR^*3in each

31

STATUS2

O

-

H

channel, or errors.

The initial value is BUSYB^*3of channel 0, and output data is "H" level.

Command processing status signal output pin.

32

CBUSYB

N.C.

O

-

Negative An "L" level is output during command processing.

Be sure to input a command with this pin at an "H" level.

(^*2)

Unused pin.

Leave open.

2,8,25

-

Hi-Z

*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.

*2 "L" at reset, "H" at power-down

*3 For NCR, BUSYB, refer to the description of "RDSTAT command".

■ Termination of Unused Pins

This section explains how to terminate unused pins.

Symbol

IRON

IRCSB

IRSCK

IRSI

Recommended pin termination

Connect to the DGND.

Connect to the DV_DD

.

Connect to the DGND.

IRSO

XT

Leave open.

XTB

AIN

TEST0

N.C.

Connect to the SPGND.

Connect to the DGND.

SO

SPM

Leave open.

STATUS1

STATUS2

7/123

FEDL22Q62X-06

ML22Q62X

■ I/O Equivalent Circuit

Classifi

cation

A

Circuit

Overview

Attribute: Input

Power: DV_DD

Function: CMOS inputs with pull-down

Applicable pin: TEST0

B

Attribute: Input

Power: IOV_DD

Function: CMOS inputs with pull-down

Applicable pin: IRON

C

Attribute: Input

Power: DV_DD

Function: CMOS inputs with pull-up

Applicable pin: RESETB

D

Attribute: Input

Power: DV_DD

Function: CMOS inputs

Applicable pins: SI, SCK, CSB

E

Attribute: Input

Power: IOV_DD

Function: CMOS inputs

Applicable pins: IRCSB, IRSCK

8/123

FEDL22Q62X-06

ML22Q62X

Classifi

cation

F

Circuit

Overview

Attribute: output

Power: DV_DD

Function: CMOS outputs

Applicable pins: STATUS1, STATUS2, CBUSYB,SO

G

H

I

Attribute: Input/

Power: IOV_DD

Function: CMOS inputs

Applicable pin: IRSI

Attribute: output

Power: IOV_DD

Function: CMOS outputs

Applicable pin: IRSO

Attribute: Oscillator circuit

Power: DV_DD

Function: 4.096M, 4.000MHz oscillation

Applicable pins: XT, XTB

XTB

XT

9/123

FEDL22Q62X-06

ML22Q62X

Classifi

cation

J

Circuit

Overview

Attribute: Analog

Power: SPV_DD

Function: Sound output

Applicable pins: SPP, SPM

L

Attribute: Analog

Power: SPV_DD

Function: Sound input

Applicable pins: AIN

10/123

FEDL22Q62X-06

ML22Q62X

■ Electrical characteristics

● Absolute maximum rating

DGND=SPGND=0V, Ta=25°C

Parameter

Symbol

DV_DD

IOV_DD

SPV_DD

V_DDR

Condition

—

Rating

Unit

Power supply voltage 1

-0.3 to +6.0

V

Power supply voltage 2

Input voltage 1

—

-0.3 to +4.6

V

V_IN1

V_IN2

-0.3 to DV_DD+0.3

-0.3 to IOV_DD+0.3

Input voltage 2

—

When the LSI is mounted on

JEDEC 4-layer board.

SPV_DD= 5V

Allowable loss

P_D

1000

mW

Applies to pins other than

SPM,SPP,V_DDLand V_DDRpins.

Applies to SPM and SPP pins.

Applies to the V_DDL/ V_DDRpin.

—

Output short-circuit current

I_OS

10

mA

500

50

mA

°C

Storage temperature

T_STG

-55 to +150

● Recommended operating conditions

DGND=SPGND=0V

Unit

Parameter

Symbol

DV_DD

Condition

Range

DV_DD

,

IOV_DD

,

IOV_DD

SPV_DD

Top

—

2.7 to 3.6 / 3.3 to 5.5

-40 to +70

V

SPV_DD^*1,Power-supply voltage

Operating temperature

°C

Min.

Typ.

4.096

4.000

Max.

MHz

Master clock frequency

f_OSC

Typ

-5%

Typ

+5%

*1 SPV_DD≥DV_DD

● Flash memory condition

Parameter

Symbol

T_OP

Condition

At write/erase

At read

―

Range

0 to +70

-40 to +70

100

Unit

°C

Time

Year

Operating temperature

Number of rewrites

Data retention period

C_EP

Y_DR

―

10

11/123

FEDL22Q62X-06

ML22Q62X

● DC characteristics

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

Symbol

Condition

Applicable pin

CSB/SCK/SI/

XT/RESETB/TEST0

IRCSB/IRSCK/

IRSI/IRON

Min.

Typ.^*1

Max.

Unit

"H" input voltage 1

V_IH1

—

0.8×DV_DD

—

DV_DD

V

"H" input voltage 2

"L" input voltage 1

V_IH2

V_IL1

—

0.8×IOV_DD

0

—

IOV_DD

V

CSB/SCK/SI/

XT/RESETB/TEST0

IRCSB/IRSCK/IRSI/

IRON

0.2×DV_DD

"L" input voltage 2

"H" output voltage 1

"H" output voltage 2

V_IL2

V_OH1

V_OH2

—

0

—

0.2×IOV_DD

V

I_OH= -50µA

I_OH= -1mA

XTB

DV_DD-0.4

—

SO/CBUSYB/

STATUS1/STATUS2

IRSO

"H" output voltage 3

"L" output voltage 1

V_OH3

V_OL1

I_OH= -1mA

I_OL= 50µA

IOV_DD-0.4

—

V

XTB

0.4

SO/CBUSYB/

STATUS1/STATUS2

IRSO

"L" output voltage 2

V_OL2

V_OL3

I_OOH1

I_OL= 2mA

—

0.4

10

V

"L" output voltage 3

I_OL= 2mA

VOH=DV_DD

(in high-impedance state)

VOL=DGND

(in high-impedance state)

VOH=IOV_DD

(in high-impedance state)

VOL=DGND

Output leakage

current 1

SO

µA

I_OOL1

I_OOH2

I_OOL2

–10

—

10

—

µA

Output leakage

current 2

IRSO

–10

(in high-impedance state)

V_IH= DV_DD

"H" input current 1

"H" input current 2

"H" input current 3

"H" input current 4

"H" input current 5

"L" input current 1

I_IH1

I_IH2

I_IH3

I_IH4

I_IH5

I_IL1

XT

RESETB/CSB/SCK/SI

TEST0

0.8

—

5.0

—

20

10

µA

V_IH= DV_DD

20

500

—

1000

10

V_IH= IOV_DD

IRCSB/IRSCK/IRSI

IRON

—

V_IH= IOV_DD

20

500

–5.0

1000

–0.8

V_IL= DGND

XT

–20

CSB/SCK/SI/

IRCSB/IRSCK/IRSI/

IRON/TEST0

RESETB

"L" input current 2

"L" input current 3

I_IL2

I_IL3

V_IL= DGND

–10

—

µA

–400

–100

–2

f

_OSC=4.096MHz

During playback

Current

consumption

Fs=48kHz, f=1kHz,

During HQADPCM

playback

I_DDO

—

25^*3

45^*3

mA

SPP/SPM No output load

Ta=-40 to

—

1^*3

10.0^*3

30.0^*3

20.0^*3

80.0^*3

µA

DV_DD=IOV_DD

=

+55°C

Ta=-40 to

+70°C

SPV_DD

3.3~5.5V

=

Power-down

Current

I_DDS

Ta=-40 to

+55°C

6^*2*3

consumption

DV_DD=IO_DD

SPV_DD=V_DDR

2.7~3.6V

=

Ta=-40 to

+70°C

*1 Typ. : DV_DD=SPV_DD=IOV_DD=5.0V,DGND=SPGND=0 V,Ta=25°C

*2 Typ. : DV_DD=SPV_DD=IOV_DD=V_DDR=3.0V,DGND=SPGND=0 V,Ta=25°C

*3 Total values of the DV_DDpin, SPV_DDpin, and IOV_DDpin

12/123

FEDL22Q62X-06

ML22Q62X

● Analog Part Characteristics

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

Symbol

Frc

Condition

Min.

3.89

Typ.

Max.

4.31

Unit

RC4MHz clock frequency

Ta=-40 to +70°C

4.096

MHz

AIN pin input resistance

R_AIN

V_AIN

Input gain 0dB

—

10

—

20

—

30

kΩ

AIN pin input voltage range

SPV_DD×2/3

Vp-p

SPV_DD= 3.3 to 5.5V

When 1/2SPV_DD± 1 mA is

applied

Line amplifier output

resistance1^*1

R_LA1

—

100

300

Ω

SPV_DD= 2.7 to 3.6V

When 1/2SPV_DD± 1 mA is

applied

Line amplifier output

resistance2^*1

R_LA2

Line amplifier

output-load-resistance ^*1

Line amplifier Out put Voltage

Range ^*1

R_LA

V_AO

For SPGND

10

—

kΩ

No output load

SPV_DD/6

SPV_DD×5/6

V

0.95x

SPV_DD/2

57

1.05x

SPV_DD/2

135

SG pin output voltage

V_SG

R_SG

—

SPV_DD/2

V

kΩ

Ω

SG pin output resistance

SPP/SPM pins Output-Load

Resistance

96

8

R_LSP1

6

—

6

Class AB speaker amplifier

4.5V≤SP_VDD≤5.5V

Class D speaker amplifier

4.5V≤SP_VDD≤5.5V

SPV_DD=5.0V,

R_OCDAB

R_OCDD

0.1

—

Ω

To the SPP and SPM pins

Short circuit detection

3

Speaker amplifier output power

1

P_SPO1

f=1kHz R_SPO=8Ω,

THD=10%

0.8

1

—

W

SPV_DD=3.0V,

f=1kHz R_SPO=8Ω,

THD=10%

Speaker amplifier output power

2

P_SPO2

0.1

-50

0.3

—

W

During no-signal SPM-SPP

Output offset voltage

AVOL=0dB

8 Ω load

V_OF

50

mV

*1 Applies to the SPP when outputting LINE.

13/123

FEDL22Q62X-06

ML22Q62X

● AC characteristic

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

Master clock duty cycle

RESETB input pulse width

Symbol

f_duty

Condition

—

Min.

40

Typ.

50

Max.

60

Unit

%

t_RST

—

10

—

μs

Reset noise rejection pulse width t_NRST

RESETB pin

—

0.1

μs

f_OSC= 4.096MHz

After input the first command at

two-times command input mode

f_OSC= 4.096MHz

During continuous playback

at SLOOP input

Command input interval time

Command input enable time

t_INTC

0

—

μs

t_cm

—

10

8

ms

At PUP command input

CBUSYB "L" level output time

t_PUP

4.096MHz external clock input

POP="L"

At AMODE command input

CBUSYB "L" level output time

t_PUPA1

AEN0="L"→"H"

AEN1 = "L"

35

71

37

73

39

75

ms

AVOL = -4dB is selected

4.096MHz external clock input

DAMP="L",POP="H"

AEN1="L"→"H"

At AMODE command input

CBUSYB "L" level output time

t_PUPA2

4.096MHz external clock input

DAMP="L",POP="L"

AEN1="L"→"H"

At AMODE command input

CBUSYB "L" level output time

t_PUPA3

31

—

33

—

35

10

ms

μs

At PDWN command input

CBUSYB "L" level output time

t_PD

f_OSC= 4.096MHz

4.096MHz external clock input

POP="L"

AEN1="L",AEN0="H"→"L"

4.096MHz external clock input

DAMP="L",POP="H"

AEN1="H"→"L"

At AMODE command input

CBUSYB "L" level output time

t_PDA1

100

102

104

ms

At AMODE command input

CBUSYB "L" level output time

t_PDA2

142

102

144

104

146

106

ms

4.096MHz external clock input

DAMP="L",POP= "L"

AEN1="H"→"L"

At AMODE command input

CBUSYB "L" level output time

t_PDA3

CBUSYB "L" level output time 1^*1

CBUSYB "L" level output time 2^*2

t_CB1

t_CB2

f_OSC= 4.096MHz

—

10

3

μs

ms

μs

f_OSC= 4.096MHz

FAD="L" at f_OSC= 4.096MHz

FAD="H" at f_OSC= 4.096MHz

200

10

CBUSYB "L" level output time 3^*3

t_CB3

ms

*1 Applies when inputting commands except the timings after PUP, PDWN, PLAY, or START command is input.

*2 Applies when inputting PLAY, START, or MUON command.

*3 Applies when inputting STOP command.

14/123

FEDL22Q62X-06

ML22Q62X

● AC Characteristics (Clock Synchronous Serial Interface)

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

CSB input enable time from IRON falling edge

CSB hold time from IRON rising edge

SCK setup time from CSB falling edge

SCK input enable time from CSB falling edge

SCK hold time from CSB rising edge

Data floating time from CSB rising edge

Data setup time from SCK

Symbol

t_EIRON

t_IRONH

t_SCKS

t_ESCK

t_CSH

Condition

Min.

1000

100

—

Typ.

—

Max.

—

Unit

ns

—

t_DOZ

RL=3KΩ

—

100

—

t_DIS

50

Data hold time from SCK

t_DIH

—

50

—

Data output delay time from SCK

LSB data hold time from SCK

t_DOD

—

90

—

t_DOH

—

100

—

SCK "H" level pulse width

t_SCKH

t_SCKL

t_DBSY

—

SCK "L" level pulse width

—

CBUSYB output delay time from SCK

—

90

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-0 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

CSB input enable time from IRON falling edge

CSB hold time from IRON rising edge

SCK setup time from CSB falling edge

SCK input enable time from CSB falling edge

SCK hold time from CSB rising edge

Data floating time from CSB rising edge

Data setup time from SCK

Symbol

t_EIRON

t_IRONH

t_SCKS

t_ESCK

t_CSH

Condition

Min.

1000

125

—

Typ.

—

Max.

—

Unit

ns

—

t_DOZ

RL=3KΩ

—

125

—

t_DIS

50

Data hold time from SCK

t_DIH

—

50

—

Data output delay time from SCK

LSB data hold time from SCK

t_DOD

—

110

—

t_DOH

—

100

125

SCK "H" level pulse width

t_SCKH

t_SCKL

—

SCK "L" level pulse width

—

15/123

FEDL22Q62X-06

ML22Q62X

● AC Characteristics (Flash Memory Interface)

SPV_DD≥DV_DD=IOV_DD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +70°C, Load capacitance of output pin =15pF(max.)

Parameter

IRCSB enable time from IRON falling edge

IRCSB hold time from IRON rising edge

IRSCK enable time from IRCSB falling edge

IRSCK hold time from IRCSB rising edge

Data setup time from IRSCK rising edge

Data hold time from IRSCK rising edge

Data delay time from IRSCK falling edge

IRSCK frequency

Symbol

t_EIRON

t_IRONH

t_ICSS

Condition

Min.

1000

100

50

Typ.

—

Max.

—

80

5

Unit

ns

—

ns

t_ICSH

ns

t_IDIS

ns

t_IDIH

50

ns

t_IDOD

t_ISCKF

t_ISCKH

t_ISCKL

t_IFLH

—

ns

—

MHz

ns

IRSCK "H" level pulse width

100

—

1

IRSCK "L" level pulse width

ns

IRSO delay time from IRON rising edge

IRSO delay time from IRON falling edge

ms

t_IFHL

—

1

16/123

FEDL22Q62X-06

ML22Q62X

■ Block diagram

The block diagram is shown below.

XTB XT

CSB

SCK

SI

OSC4.096MHz

or 4.000MHz

Timing

Controller

PLL

RC4.096MHz

SO

MCU

Interface

IRCSB

IRSCK

IRSI

IRSO

IRON

IOV_DD

Flash Memory

Command

Analyzer

Address

Controller

CBUSYB

STATUS1

STATUS2

PCM Synthesizer

Digital Mixing

LPF

DV_DD

DGND

V_DDL

V_DDR

ΔΣ

16bit DAC

Line Amplifier

Analog Mixing

SG

PWM

RESETB

TEST0

TEST1

AIN

D Class

Amplifier

AB Class

Amplifier

SPV_DD

SPGND

SPP

SPM

17/123

FEDL22Q62X-06

ML22Q62X

■ Function description

● Clock Synchronous Serial Interface

The CSB, SCK, SI, and SO pins are used to input various command data and to read the status.

For command and data inputting, after "L" level is input to the CSB pin, data is input to the SI pin in MSB first in

synchronization with the input clock signal of the SCK pin. The SI pin data is loaded into the LSI in synchronization with the

SCK pin clock, and the command data is determined by the SCK pin clock of the eighth pulse.

When reading, after "L" level is input to the CSB pin, it is output from the SO pin in synchronization with the input clock

signal of the SCK pin.

The selection of the rising or falling edge of the SCK pin clock depends on the state of the SCK pin at the falling edge of the

CSB pin.

When the SCK pin is "H" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the rising edge of the

SCK pin clock, and the status signal is output from the SO pin on the falling edge of the SCK pin clock.

When the SCK pin is "L" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the falling edge of the

SCK pin clock, and the status signal is output from the SO pin on the rising edge of the SCK pin clock.

When the CSB pin is fixed to "L" level, the SI pin data is loaded into the LSI on the rising edge of the SCK pin clock, and the

status signal is output from the SO pin at the falling edge of the SCK pin clock.

However, if unexpected pulses are input to the SCK pin due to noise, etc., the count of the number of SCK pin clocks may be

shifted, and normal command input may not be performed.

The serial interface can be returned to the initial state by setting the CSB pin to "H" level.

When the CSB pin is "H" level, the SO pin becomes a high impedance state.

Command data input timing： SCK rising edge operation

(When the SCK is "H" at the falling edge of the CSB)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SI

Command data input timing： SCK falling edge operation

(When the SCK is "L" at the falling edge of the CSB)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SI

Command data output timing： SCK falling edge operation

(When the SCK is "H" at the falling edge of the CSB)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SO

Command data output timing： SCK rising edge operation

(When the SCK is "L" at the falling edge of the CSB)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SO

18/123

FEDL22Q62X-06

ML22Q62X

● Volume Settings (Differences Between AVOL and CVOL)

The volume can be set with 3 commands CVOL, AVOL and AMODE.

The CVOL can set the volume of each channel, the AVOL can set the volume after channel mixing, and the AMODE can set

the input gain to the amplifier. By using the fade function with FADE command, the volume can be adjusted stepwise when

the volume is changed with CVOL.

AIN

Setting AIG of

AMODE command

Speaker

GAIN

AMP

amplifier

Channel 0 (CH0)

Channel 1 (CH1)

Channel 2 (CH2)

Channel 3 (CH3)

SPP

SPM

[0]

[1]

[2]

[3]

GAIN

AMP

Setting DAG of

AMODE command

AVOL

command

[3:0]

CVOL command

FADE command

LINE

AMP

19/123

FEDL22Q62X-06

ML22Q62X

● Speech synthesis algorithm

This LSI contains five algorithm types to match the characteristic of playback sound: 4-bit ADPCM2 algorithm,

HQ-ADPCM algorithm, 8-bit non-linear PCM algorithm, 8-bit straight PCM algorithm, and 16-bit straight PCM algorithm.

Key feature of each algorithm is described in the table below.

Speech synthesis

algorithm

Compression

rate^*1

Feature

4bit ADPCM algorithm is improved. Adopting variable bit length

enables high sound quality and high data compression. Suitable for

sound effects with sharp changes in waveforms or for pulsed

waveforms.

HQ- ADPCM

1/5

LAPIS original 4bit ADPCM algorithm is improved. Better

followability to the waveform improves the sound quality. Suitable for

human voices, animal crying, and natural sounds.

This algorithm enables playing back a sound with 10-bit equivalent

quality in the center of the waveform. Suitable for low-amplitude

sounds that are easily distorted.

This algorithm has excellent followability to the waveform in all

sound areas. Suitable for sound effects with sharp changes in

waveforms or for pulsed waveforms.

This algorithm has excellent followability to the waveform in all

sound areas. Suitable for sound effects with sharp changes in

waveforms or for pulsed waveforms.

4-bit ADPCM2

8-bit non-linear PCM

8-bit straight PCM

16-bit straight PCM

1/4

1/2

1

*1: When using the same sampling frequency.

20/123

FEDL22Q62X-06

ML22Q62X

● Memory Allocation and Creating Sound Data

The flash memory is partitioned into four data areas: sound (i.e., phrase) control area, test area, sound area, and edit ROM

area.

The sound control area manages the sound data in the ROM. It contains data for 4,096 phrases.

The sound area contains actual waveform data.

The edit ROM area contains data for effective use of sound data. For the details, refer to the section of "Edit ROM

Function".

The edit ROM area is not available if the edit ROM is not used.

The Sound data is created using a dedicated tool (Speech LSI Utility).

Configuration of Flash Memory Data (4Mbit)

0x00000

Test area

0x0007F

0x00080

Sound control area (*)

(The number of phrases can be set

with the dedicated tools.)

0x0207F

0x02080

Sound area

Edit ROM area

Depends on creation of sound

data

0x7FFFF

(*) When the number of phrases is set to 1024

The number of phrases can be set from 1024 to 4096 in 1024 units

using the dedicated tools.

● Playback time and memory capacity

The playback time depends on the number of phrases, memory capacity, sampling frequency, and playback algorithm. The

relationship is shown below. However, this is the playback time when the edit ROM function is not used.

1.024 × (Memory Capacity (kbit)-(0.0625 × Number of Phrases)-0.625)

(sec)

Playback Time =

Sampling frequency (kHz) × bit length

When the number of phrases is 1024, the sampling frequency is 16kHz, and the HQ-ADPCM algorithm is selected, the

playback time will be approximately 81 seconds.

1.024 × (4096(kbit)- (0.0625×1024) - 0.625)

Playback Time =

≒ 81 (sec)

16 (kHz) × 3.2 (bit) (average)

21/123

FEDL22Q62X-06

ML22Q62X

● Edit ROM Function

With the edit ROM function, multiple phrases can be played in succession. The following functions can be configured using

the edit ROM function:

• Continuous playback: There is no limit to the continuous playback count that can be specified. It depends on the

memory capacity only.

• Silence insertion: 20 to 1024 ms

Using the edit ROM function enables an effective use of the flash memory capacity.

Below is an example of the ROM configuration in the case of using the edit ROM function.

Examples of phrases using the edit ROM function

A

E

A

B

C

D

Phrase 1

Phrase 2

Phrase 3

Phrase 4

Phrase 5

B

C

D

B

D

Silence

E

C

D

Example of sound data where the contents above are stored in ROM

Address control

area

A

B

D

C

E

Editing area

22/123

FEDL22Q62X-06

ML22Q62X

● Mixing function

Up to 4 channels mixing playback is possible at the same time. Commands with channel designation can set channels

independently.



Waveform clamp precautions for mixing

When mixing, the clamp may be generated as shown in the figure below due to the calculation of the synthesis. If the clamp

is known to be generated in advance, adjust the volume of each channel by CVOL command.

SPV_DD

5/6SPV_DD

Channel 0

1/6SPV_DD

SPGND

SPV_DD

5/6SPV_DD

Channel 1

1/6SPV_DD

SPGND

SPV_DD

5/6SPV_DD

For channels 0 and 1

Mixing waveform

1/6SPV_DD

SPGND

If the result of mixing channels 0 and 1 exceeds from the 1/6SPV_DDto 5/6SPVDD level

(as indicated by the broken line), the sound quality may be reduced by clamping.

Waveforms when AVOL is set to 0.0dB.

23/123

FEDL22Q62X-06

ML22Q62X



Class D amplifier precaution on mixing

When mixing with a class d amplifier, use the CVOL command to adjust the volume so that the waveform after mixing

does not exceed the full amplitude.

An example of adjusting the volume of the CVOL command during mixing playback is shown below.

Example1)

When performing 2-channels mixing playback of channel 0 and channel 1.

CVOL command setting value

(CV1,CV0,CV6-CV2)

Description

Channel 0

Channel 1

Set both channel 0 and channel 1 amplitude to

0.5x.

4Fh(-6.02dB)

Set channel 0 amplitude to 0.75x and channel 1

amplitude to 0.25x.

67h(-2.50dB) 37h(-12.04dB)

Example2)

When performing 3-channels mixing playback of channel 0, channel 1 and channel 2.

CVOL command setting value

(CV1,CV0,CV6-CV2)

Channel 1

Description

Channel 0

Channel 2

Set channel 0, channel 1 and channel 2 amplitude

to 0.33x.

15h(-9.83dB)

Set channel 0 amplitude to 0.5x and channel 1 and

channel 2 amplitude to 0.25x.

4Fh(-6.02dB) 37h(-12.04dB) 37h(-12.04dB)

Example3)

When performing all channels mixing playback.

CVOL command setting value

(CV1,CV0,CV6-CV2)

Description

Channel 3

Channel 0

Channel 1

Channel 2

37h(-12.04dB) 37h(-12.04dB) 37h(-12.04dB) 37h(-12.04dB) Set all channels amplitude to 0.25x.

Short detection of SPP pin and SPM pin always operates while using the class D amplifier. If the volume of CVOL

command is adjusted incorrectly and it it is played back in the clamped state, the short detection circuit is determaine that a

short has occurred.

When using class D amplifier, enable short detection of SPP pin and SPM pin by SAFE command and check the short

detection error (SPDERR). Refer to SAFE command for setting.

24/123

FEDL22Q62X-06

ML22Q62X



Different sampling frequency mixing algorithm

It is not possible to perform channel mixing by a different sampling frequency group.

Note that when channel synthesis is performed on a sampling frequency group other than the selected sampling frequency

group, playback will be faster or slower.

The following table lists the frequency group that can be used when mixing different sampling frequency groups.

6.4kHz, 12.8kHz, 25.6kHz

8.0kHz, 16.0kHz, 32.0kHz

11.025kHz, 22.05kHz, 44.1kHz

12.0kHz, 24.0kHz, 48.0kHz

10.7kHz, 21.3kHz

... (Group 1)

... (Group 2)

... (Group 3)

... (Group 4)

... (Group 5)

The figure below shows the operation image when a sampling frequency group with different sampling frequency group is

played back.

Playback at

Switch to playback at fs=12.8kHz.

fs=16.0kHz

Channel 1

Channel 2

Playback at fs = 25.6kHz

Figure 1) Case where a phrase is played at a sampling frequency belonging to a different

sampling frequency group during playback on channels 1 and 2

Playback at

fs=16.0kHz

Channel 1

Channel 2

Playback at fs = 25.6kHz

Figure 2) Case where a phrase is played at a sampling frequency belonging to a different

sampling frequency group after playback is finished at the other channel

25/123

FEDL22Q62X-06

ML22Q62X

● Misoperation detection and failure detection functions

Misoperation detection and failure detection functions can be set with SAFE command. The error detection status can be read

by the RDERR command, and the error bit indicating the error detection status can be cleared by the ERRCL command. In

addition, OUTSTAT command can be used to send whether an error is detected or not to the STATUS1 pin or STATUS2 pin.

For SAFE, RDERR, ERRCL and OUTSTAT commands, refer to the "Command" section.

Misoperation detection and failure detection are shown below.

• Command error detection

• Speaker disconnection detection

• LSI temperature error detection

• SPP pin and SPM pin short detection

• Flash memory error detection

• Watchdog timer overflow detection

• RST counter overflow detection

• Detects the stop of clock input from a crystal resonator or ceramic resonator.

26/123

FEDL22Q62X-06

ML22Q62X



Command error detection

This LSI detects two command errors: phrase number error and command error. Use the WCMEN bit of the SAFE

command to set command error detection.

① Phrase number error.

Set the number of phrases (1024, 2048, 3072 or 4096) to use when creating sound data in the Speech LSI Utility. If you

specify a phrase that exceeds the number of phrases specified by the Speech LSI Utility with the PLAY2 or FADR2

command, an error in the command is detected and the error bit (WCMERR) is set to "1".

② Command error.

This LSI has a function to input various commands and data two-times to prevent malfunction due to noise at the serial

interface pin. The setting of the two-times input mode is made at power-up. Refer to the "PUP command" for the setting

method.

In the two-times input mode, the command data is input two-times in succession, and it is valid only when the input data

matches. If a mismatch occurs during the second data input after the first data input, an error in the command is detected and

the error bit (WCMERR) is set to "1", and the command entered is ignored.

Error bit (WCMERR) can be read with RDERR command. Also, error bit (WCMERR) can be cleared by ERRCL command.

Command

1st

Command

2nd

ERRCL Command ERRCLCommand

1st 2nd

Command

STATUSn pin^*1

(n：1 or 2)

WCMERR

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

27/123

FEDL22Q62X-06

ML22Q62X



Speaker disconnection detection

Set the speaker disconnection detection with the DCDEN bit of the SAFE command.

The speaker connection status of the SPP and SPM pins is checked when the analog power-up is activated in speaker

amplifier output mode by AMODE command. When the disconnection of the speaker is detected, the error bit (DCDERR) is

set to "1".

Error bit (DCDERR) can be read with RDERR command. Also, error bit (DCDERR) can be cleared by ERRCL command.

AMODE^*2

RDERR

ERRCL

Command PUP

DCDEN

SAFE^*1

SPV_DD

SPP

SPGND

SPV_DD

SPM

HiZ

SPGND

STATUSn^*3

(n：1 or 2)

“H”: Disconnected “L”: Not disconnected

DCDERR

Status

analog power-up

speaker power-up

analog power-down

speaker power-down

Speaker disconnection detection

*1 Set DCDEN = "1"

*2 Analog power-up in speaker amplifier output mode

*3 Misoperation detection and failure detection outputs are selected by OUTSTAT command.



LSI temperature error detection

Set the LSI temperature error detection with the TSDEN bit of the SAFE command.

When the TSDEN bit is set to "1" by the SAFE command, LSI temperature error detection starts. When the TSDEN bit is set

to "0", LSI temperature error detection ends.

When the LSI becomes 130^OC or more, the error bit (TSDERR) becomes "1".

Error bit (TSDERR) can be read with RDERR command. Also, error bit (TSDERR) can be cleared by ERRCL command.

Command

PUP

SAFE^*1

SAFE^*2

RDERR

ERRCL

TSDEN

LSI temperature is over 130 degrees

STATUSn^*3

(n：1 or 2)

TSDERR

Error-temperature detection of LSI is operating

*1 Set TSDEN = "1"

*2 Set TSDEN = "0"

*3 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

28/123

FEDL22Q62X-06

ML22Q62X



SPP pin and SPM pin short detection

Set the SPP pin and SPM pin short detection with the SPDEN bit of the SAFE command.

Detects short circuit between SPP pin and SPM pin, or SPP pin and GND (ground fault), or SPM pin and GND (ground

fault). Can be used when SPV_DD≥ 4.5V. Operation is started by analog power-up in the speaker amplifier output mode by

the AMODE command, and operation is terminated by power-down in the speaker amplifier output mode by the AMODE

command.

After inputting SAFE command, start the analog power-up operation by AMODE command within 10ms.

When a short-circuit is detected, the error bit (SPDERR) is set to "1". When using a class D amplifier with the DAMP bit of

AMODE command set to "1", if the PWM output is fixed to "H" level for 62.5μs or longer, the error bit (SPDERR) is set to

"1". At the same time, the speaker amplifier output pin (SPP/SPM) is forcibly turned off. Read the error bit (SPDERR) with

the RDERR command, end playback, and perform analog power-down with the AMODE command. Then, use ERRCL

command to clear the error bit (SPDERR).

To restart playback, use the AMODE command to analog power-up the speaker amplifier output mode and enter the PLAY

command. However, if shorting to ground continues, the error bit (SPDERR) is set to "1" and the speaker amplifier output pin

(SPP/SPM) is forcibly turned off simultaneously.

Short detection prevents damage to LSI. However, the detection circuit is effective in preventing damage due to

unexpected accidents. It does not support continuous short operation or transient use.

AMODE^*2

RDERR

AMODE^*3

ERRCL

AMODE^*2

Command

PUP

SAFE^*1

10ms

SPDEN

SPP

SPV_DD

SPGND

SPV_DD

SPM

HiZ

Short detection

HiZ

SPGND

STATUSn^*4

(n：1 or 2)

SPDERR

Status

analog power-up，speaker power-up

analog power-down

speaker power-down

analog power-up

speaker power-up

analog power-down

speaker power-down

SPP pin and SPM pin short detection

is operating

SPP pin and SPM pin short detection

is operating

*1 Set 1 SPDEN = "1"

*2 Analog power-up in speaker amplifier output mode

*3 Analog power-down in speaker amplifier output mode

*4 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

29/123

FEDL22Q62X-06

ML22Q62X



Flash memory error detection

Set the Flash memory error detection with the ROMEN bit of the SAFE command. It is possible to detect two kinds of

errors.

① Flash memory read data error

When an error is detected in the read data from the flash memory, the error bit (ROMERR) is set to "1". At the same time,

playback of the corresponding channel is stopped.

If the error bit (ROMERR) is set to "1" after the PUP command and before the PLAY command or START command starts

playback, this LSI may have error at the time of start. In such cases, initialize this LSI by moving the LSI to the power-down

mode by resetting the LSI by the RESETB pin or by using PDWN command.

② Access outside the flash memory address range

If the flash memory is accessed outside the flash memory address range, an error is detected and the error bit (ROMERR) is

set to "1".

At the same time, playback of the corresponding channel is stopped.

Error bit (ROMERR) can be read with RDERR command. Error bit (ROMERR) can be cleared by ERRCL command.

30/123

FEDL22Q62X-06

ML22Q62X



Watchdog timer overflow detection

A communication error between the HOST MCU and this LSI (disconnection or short-circuit of the MCU command

interface, etc.) can be detected.

Set the watchdog timer overflow detection with WDTEN bit of the SAFE command.

When the detection operation is started, the detection does not stop even if the WDTEN bit is set to "0".

After the detection operation starts, clear the WDT counter with the WDTCL command before the WDT counter

overflows.

When the WDT counter overflows (for the first time), the error bit (WDTERR) is set to "1".

Error bit (WDTERR) can be read with RDERR command. In addition, the error bit (WDTERR) can be cleared by the

ERRCL command after the WDTCL command.

The count time of the WDT counter is 2s the initial value. The counting time can be set to 125ms, 500ms, 2s, 4s. In addition,

it is possible to shift to the command wait state after power-up by the second overflow of the WDT counter.

The count time and the second overflow operation can be set with the dedicated tools (Speech LSI Utility).

SAFE

WDTCL

Command

WDTEN

Count-up

0h Count-up

WDT counter

WDT overflow

WDTERR

RSTERR

STATUSn pin ^*1n:1 or 2

Signal to shift command

standby state after power-up

Stop WDT

WDT operation

Status

Set WDTEN = "1"

Clears the WDT counter by WDTCL commands.

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

Recommended Operation Flow of Watchdog Timer

31/123

FEDL22Q62X-06

ML22Q62X

The operation when no WDTCL command is entered is as follows.

SAFE

WDTCL

Command

WDTEN

0h

Count-up

WDT counter

WDT overflow

WDTERR^*2

RSTERR^*2

STATUSn pin ^*1n:1 or 2

Signal to shift command

standby state after power-up

Stop WDT

Status

WDT operation

Stop WDT

Set WDTEN = "1"

Change to RSTERR = "1" on the second overflow of the

WDT counter.

Change to WDTERR = "1"on the

first overflow of the WDT counter.

Shifts to the command standby state after power-up.

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

*2 Even if transferring to the command standby state after power-up by the second overflow of the the WDT counter, the

state of WDTERR bit and RSTERR bit remain. The state configured by OUTSTAT command also remains.

<When "Transition to the command standby state after power-up" is not selected by the second overflow of the WDT

counter>

SAFE

WDTCL

Command

WDTEN

0h

Count-up

0h

Count-up

WDT counter

WDT overflow

WDTERR

RSTERR

STATUSn pin ^*1n:1 or 2

Signal to shift command

standby state after power-up

Stop WDT

WDT operation

Status

Set WDTEN = "1"

Change to RSTERR = "1" on the second overflow of the

WDT counter.

Change to WDTERR = "1"on the

first overflow of the WDT counter.

No shifting to command standby state after power-up

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

32/123

FEDL22Q62X-06

ML22Q62X



RST counter overflow detection

By using the RST counter overflow detection, it is possible to shift the LSI to the command standby state after power-up

after misoperation detection and failure detection occurs.

When the overflow detection of RST counter is set by RSTEN bit of SAFE command, the detection operation will start.

When the detection operation is started, the detection does not stop even if the RSTEN bit is set to "0".

The RST counter starts counting up after misoperation detection and failure detection occurs.

If the RST counter is cleared with the ERRCL command before it overflows, it stops until the next error occurs.

When the RST counter overflows, the error bit (RSTERR) is set to "1".

Error bit (RSTERR) can be read with RDERR command. Also, error bit (RSTERR) can be cleared by ERRCL command.

The count time of the RST-counter is 2s, the initial-value. The counting time can be set to 125ms, 500ms, 2s, or 4s.

Set the counting time and overflow operation (shift to the command standby state after power-up) with the dedicated tools

(Speech LSI Utility).

The operation when RSTEN is set to "1" is as follows.

RDERR

SAFE

ERRCL

Command

RSTEN

Error detection

Count-up

0h

RST counter

Overflow

RSTERR

STATUSn pin ^*1n:1 or 2

Signal to shift command

standby state after power-up

Set RSTEN = "1"

Clears the RST-counter with ERRCL commands.

The RST counter stops operating.

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

33/123

FEDL22Q62X-06

ML22Q62X

The operation when no ERRCL command is entered is as follows.

RDERR

ERRCL

SAFE

Command

RSTEN^*2

Error detection

RST counter

Overflow

0h

Count-up

0h

RSTERR^*3

STATUSn pin ^*1*3n:1 or 2

Signal to shift command

standby state after power-up

Set RSTEN = "1"

The RSTERR bit is set to "1" when the RST-counter overflows.

Shifts to the command standby state after power-up.

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

*2 If transferring to the command standby state after power-up is executed by the overflow of the RST counter, each bit of

SAFE command is cleared. Also, error bits readable by RDERR command are cleared by ERRCL command.

*3 Even if transferring to the command standby state after power-up is executed by the overflow of the RST counter,

error bits readable by RDERR command and the state configured by OUTSTAT command remain.

< When "Transition to command standby state after power-up " is not selected by the overflow of the RST counter >

SAFE

RDERR

ERRCL

Command

RSTEN

Error detection

RST counter

0h

Count-up

0h

Overflow

RSTERR

STATUSn pin ^*1n:1 or 2

Signal to shift command

standby state after power-up

Set RSTEN = "1"

The RSTERR bit is set to "1" when the RST-counter overflows.

No shifting to command wait state after power-up

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

34/123

FEDL22Q62X-06

ML22Q62X



Detects the stop of clock input from a crystal resonator or ceramic resonator

Set the "Detects the stop of clock input from a crystal resonator or ceramic resonator" with the OSCEN bit of the SAFE

command.

When the clock input from the crystal resonator or the ceramic resonator is stopped, the error bit (OSCERR) is set to "1".

At the same time, the clock backup function is activated and the clock is automatically switched to the RC oscillator circuit

(4.096MHz).

Error bit (OSCERR) can be read with RDERR command. However, if the RDERR command (first byte) is inputted before

the crystal or ceramic resonator stops and switches to RC oscillation (about 500μs), the CBUSYB pin will remain "L".

Therefore, read the command after the CBUSYB pin becomes "H". Also, error bit (OSCERR) can be cleared by ERRCL

command. However, if the clock input from the crystal resonator or the ceramic resonator continues to be stopped while the

OSCEN bit of the SAFE command is "1", the error bit (OSCERR) is set to "1".

When the crystal resonator or the ceramic resonator stops and switches to RC oscillation, playback may become abnormal.

Therefore, after confirming that the error bit (OSCERR) is "1", enter STOP command to stop playback.

If the clock input from the crystal resonator or the ceramic resonator is stopped while the OSCEN bit is "0", the error bit

(OSCERR) does not change to "1", but the clock backup function is activated and the clock backup circuit is automatically

switched to the RC oscillator circuit (4.096MHz).

Command

OSCEN

PUP

SAFE^*1

SAFE^*2

RDERR

ERRCL

OSC0 pin

OSC1 pin

Normal oscillation state

Oscillation stopped state

Normal oscillation state

Oscillation stopped state

Normal oscillation state

X’tal or

RC oscillation

X’tal or

RC oscillation

X’tal or

Internal clock

Ceramic resonator

（Clock backup state）

Ceramic resonator

（Clock backup state）

Ceramic resonator

STATUSn pin^*3

(n：1 or 2)

OSCERR

Error bit (OSCERR) is operating

*1 Set OSCEN = "1"

*2 Set OSCEN = "0"

*3 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

SAFE^*1

RDERR

ERRCL

Command

OSCEN

PUP

OSC0 pin

OSC1 pin

Normal oscillation state

Oscillation stopped state

Normal oscillation state

Oscillation stopped state

Normal oscillation state

X’tal or

RC oscillation

X’tal or

RC oscillation

X’tal or

Internal clock

Ceramic resonator

（Clock backup state）

Ceramic resonator

（Clock backup state）

Ceramic resonator

STATUSn pin^*2

(n：1 or 2)

OSCERR

Error bit (OSCERR) is operating

*1 Set OSCEN = "1"

*2 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

35/123

FEDL22Q62X-06

ML22Q62X

● Flash memory rewrite function

The flash memory can be rewritten in the following two ways.

SOUND LSI

IRON

①

MCU command

interface

②Flash・memory

interface

CSB

SCK

SI

IRCSB

IRSCK

IRSI

SO

IRSO

①

Rewrite using the clock synchronous serial interface of the MCU command interface

By using the CSB, SCK, SI and SO pins, which are clock synchronous serial interfaces of the MCU command interface

the flash memory can be rewritten. When the PUP command and FDIRECT command are entered with the IRON pin set to

"L", direct access to the flash memory is enabled from the CSB, SCK, SI and SO pins.

When returning to the normal mode, insert a reset to initialize (RESETB pin is “L” level.) or shut off the power.

PUP command

FDIRECT command

1^stbyte

FDIRECT command

2^ndbyte

Direct access to the flash memory

is enabled

IRON

CSB

SCK

SI

“L”

t_PUP

t_CB1

CBUSYB

Status

Normal mode

Flash memory access mode

For the PUP command, refer to the "PUP command" in the "Command" section. For the FDIRECT command, refer to the

"FDIRECT command" in the "Command" section.

②

Rewrite using flash memory interface

The flash memory can be rewritten using the IRON, IRCSB, IRSCK, IRSI and IRSO pins that is the flash memory interface.

When the PUP command and FDIRECT command are entered with the IRON pin set to "H", direct access to the flash

memory is enabled from the IRCSB, IRSCK, IRSI and IRSO pins.

When returning to the normal mode, insert a reset to initialize (RESETB pin is “L” level.) or shut off the power.

PUP command

FDIRECT command FDIRECT command

1^stbyte 2^ndbyte

Direct access to the flash memory

is enabled

IRON

IRCSB

IRSCK

IRSI

t_PUP

t_CB1

CBUSYB

Status

Normal mode

Flash memory access mode

For the PUP command, refer to the "PUP command" in the "Command" section. For the FDIRECT command, refer to the

"FDIRECTcommand" in the "Command" section.

36/123

FEDL22Q62X-06

ML22Q62X

The Chip Erase, Status Read, Program and Read of the flash memory are described on the next page.

● Chip Erase

06h

C7h

CSB/

IRCSB

SCK/

IRSCK

SI/

IRSI

Confirm that BUSY is "0" by Status Read after Chip Erase.

● Status Read

05h

CSB/

IRCSB

SCK/

IRSCK

SI/

IRSI

BUSY

1:erase/program executing

0:erase/program completed

SO/

IRSO

● Program

06h

02h

24-bit Address

CSB/

IRCSB

SCK/

IRSCK

2 2 2 2 1 1 1 1

3 2 1 0 9 8 7 6

SI/

7 6 5 4 3 2 1 0

IRSI

Data Byte 1

Data Byte 2

Data Byte 255 Data Byte 256

CSB/

IRCSB

SCK/

IRSCK

SI/

7 6 5 4 3 2 1 0

IRSI

Confirm that BUSY is "0" by Status Read after Program.

● Read

03h

24-bit Address

Data Out 1

Data Out 2

CSB/

IRCSB

SCK/

IRSCK

2 2 2 2 1 1 1 1

3 2 1 0 9 8 7 6

SI/

7 6 5 4 3 2 1 0

IRSI

SO/

7 6 5 4 3 2 1 0

IRSO

37/123

FEDL22Q62X-06

ML22Q62X

■ Timing chart

● Power-on timing

DV_DD

SPV_DD

IOV_DD

90%

RESETB^VIH

t_RST

VIL

Status

Power-down

After the power is turned on, the device enters the power-down state.

Start up in the order of DV_DD, SPV_DDand IOV_DDor DV_DD, IOV_DDand SPV_DD

.

It is possible that the DV_DDand SPV_DDstart up at the same time and then the IOV_DDstarts up, or the DV_DD

and IOV_DDstart up at the same time and then the SPV_DDstarts up.

The DV_DD, SPV_DDand IOV_DDcan also start up at the same time.

t_RSTis specified based on the last power-on pin.

Be sure to input "L" to the RESETB pin before inputting the first command after power-on.

Be sure to enter "L" at the RESETB pin when the DV_DDis below the (recommended) operating voltage range.

● Power-off timing

90%

DV_DD

SPV_DD

IOV_DD

Status

Power-down

Shut down in the order of IOV_DD, SPV_DD, and DV_DDor SPV_DD, IOV_DD, and DV_DD

.

It is possible that the IOV_DDshuts down and then the SPV_DDand DV_DDshut down at the same time,

or the SPV_DDshuts down and then the IOV_DDand DV_DDshut down at the same time.

The DV_DD, SPV_DDand IOV_DDcan also shut down at the same time.

Shut down each power supply after changing to the power down status with PDWN commands.

38/123

FEDL22Q62X-06

ML22Q62X

● Reset input timing

RESETB

VIH

VIL

t_RST

XT/XTB

Oscillating

Oscillation stopped

V

_DDL/V_DDR

GND

SG

SPM

SPP

Hi-Z

GND

Reset

Power-down

During playback

Status

The same timing is applied when a reset is input during command standby.

39/123

FEDL22Q62X-06

ML22Q62X

● Flash memory interface timing

VIH

IRON

VIL

t_EIRON

t_IRONH

VIH

IRCSB

VIL

t_ISCKF

t_ISCKL

t_ICSH

t_ICSS

VIH

IRSCK

VIL

t_IDISt_IDIH

t_ISCKH

VIH

VIL

IRSI

t_IFHL

t_IFLH

t_IDOD

VOH

VOL

IRSO

40/123

FEDL22Q62X-06

ML22Q62X

● Clock synchronous serial

 Clock Synchronous Serial Interface Timing (SCK Initial Value = "H" Level)

VIH

VIL

t_EIRON

t_IRONH

IRON

CSB

VIH

VIL

t_CSH

t_SCKSt_ESCK

t_SCKH

VIH

VIL

SCK

t_DIS

t_DIH

t_SCKL

VIH

VIL

SI

t_DOH

t_DOD

t_DOZ

VIH

VIL

SO

t_DBSY

CBUSYB ^VOH

VOL



Clock Synchronous Serial Interface Timing (SCK Initial Value = "L" Level)

VIH

t_EIRON

t_IRONS

IRON

VIL

VIH

CSB

VIL

t_CSH

t_SCKSt_ESCK

t_SCKL

VIH

VIL

SCK

t_DIS

t_DIH

t_SCKH

VIH

VIL

SI

t_DOH

t_DOD

t_DOZ

VIH

VIL

SO

t_DBSY

CBUSYB ^VOH

VOL

41/123

FEDL22Q62X-06

ML22Q62X

● Power-up timing

CSB

SCK

SI

t_PUP

CBUSYB ^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

RC

oscillation

(internal)

XT・XTB^*1

Oscillation stopped

Oscillating

Power up

Oscillating

V_DDL

V_DDR

DGND

Power down

Oscillation stabilized

Awaiting command

Status

*1 When using a crystal or ceramic resonator

● Power-down timing

CSB

SCK

SI

t_PD

CBUSYB^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

Oscillation

stopped

RC oscillation

(internal)

Oscillating

Oscillation

stopped

XT・XTB^*1

Oscillating

Power up

V_DDL

V_DDR

DGND

Command is being

processed

Awaiting command

Power down

Status

*1 When using a crystal or ceramic resonator

42/123

FEDL22Q62X-06

ML22Q62X

● Speaker amplifier power-up timing (DAMP bit = "0", AEN1 bit = "0", AEN0 bit = "0" → "1")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PUPA1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

LINE output

(internal)

GND

Hi-Z

SPM

GND

SPP

Command standby

Awaiting command

Status

Command is being processed

● Speaker amplifier power-up timing (DAMP bit = "1", AEN1 bit = "0", AEN0 bit = "0" → "1")

AMODE command

1^stbyte

AMODE command

2^ndbyte

CSB

SCK

SI

t_CB1

t_PUPA1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

Hi-Z

SPM

GND

SPP

Command standby

Awaiting command

Status

Command is being processed

43/123

FEDL22Q62X-06

ML22Q62X

● Line amplifier power-up timing (DAMP bit = "0", POP bit = "1", AEN1 bit = "0" → "1", AEN0 bit = "0")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PUPA2

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

SPP

GND

Awaiting command

POP noise suppressed

Awaiting command

Status

Command is being processed

● Line amplifier power-up timing (DAMP bit = "0", POP bit = "0", AEN1 bit = "0" → "1", AEN0 bit = "0")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PUPA3

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

GND

SPP

Awaiting command

Command is being processed

Status

Command is being processed

44/123

FEDL22Q62X-06

ML22Q62X

● Speaker amplifier power-down timing (DAMP bit = "0", AEN1 bit = "0", AEN0 bit = "1" → "0")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PDA1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

LINE output

(internal)

GND

1/2SPVDD

Hi-Z

SPM

SPP

GND

Awaiting command

Status

Command is being processed

● Speaker amplifier power-down timing (DAMP bit = "1", AEN1 bit = "0", AEN0 bit = "1" → "0")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PDA1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

Hi-Z

SPM

SPP

GND

Awaiting command

Status

Command is being processed

45/123

FEDL22Q62X-06

ML22Q62X

● Line amplifier power-down timing (DAMP bit = "0", POP bit = "1", AEN1 bit = "1" → "0", AEN0 bit = "0")

AMODE command AMODE command

1^stbyte 2^ndbyte

CSB

SCK

SI

t_CB1

t_PDA2

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

SPP

GND

Awaiting command

POP noise suppressed

Awaiting command

Status

Command is being processed

● Line amplifier power-down timing (DAMP bit = "0", POP bit = "0", AEN1 bit = "1" → "0", AEN0 bit = "0")

AMODE command AMODE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

t_PDA3

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2SPVDD

SPP

GND

Command is being processed

Awaiting command

Status

Command is being processed

46/123

FEDL22Q62X-06

ML22Q62X

● FDIRECT command timing

FDIRECT command

1^stbyte

FDIRECT command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

Normal mode

（Awaiting command）

Normal mode

Flash memory access

Status

（Awaiting command）

Command is being processed

● WDTCL command timing

WDTCL command

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

Normal mode

Status

（Awaiting command）

Command is being processed

47/123

FEDL22Q62X-06

ML22Q62X

● Change volume timing by AVOL command

AVOL command

1^stbyte

AVOL command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB ^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

Awaiting command

Status

Command is being processed

Speaker amplifier volume setting by AVOL commands is valid only when Class AB speaker amplifier is used.

When a Class D speaker amplifier is used, the setting value is ignored and +0.0dB is selected.

● FADE command timing

FADE command

1^stbyte

FADE command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB ^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

Awaiting command

Status

Command is being processed

48/123

FEDL22Q62X-06

ML22Q62X

● Setting playback phrases using FADR command

FADR command

1^stbyte

FADR command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

Awaiting command

Status

Command is being processed

49/123

FEDL22Q62X-06

ML22Q62X

● Playback start timing by PLAY command

PLAY command

1^stbyte

PLAY command

2^ndbyte

CSB

SCK

SI

t_CB1

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

*1

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

Command is being processed

When the first byte of the PLAY command is input, the device waits for the input of the second byte after the command

processing time (t_CB1). When the second byte is entered, the address data of the phrase to be played after the command

processing time (t_CB2) is read from the flash memory.

When the phrase address data is read, the specified phrase starts playback, and when playback is completed, the BUSYB

signal of the playback channel becomes "H" level.

The NCR signal goes to the "L" level during playback preparation, and goes to the "H" level when playback preparation is

completed and playback starts. When the NCR signal of the playback channel becomes "H" level, the PLAY command of the

next phrase to be played can be accepted.

*1 The length of the "L" interval in the BUSYBn is (tCB2+ sound production time).

50/123

FEDL22Q62X-06

ML22Q62X

● Continuous playback timing by PLAY command

PLAY command

2^ndbyte

PLAY command PLAY command

1^stbyte 2^ndbyte

CSB

SCK

SI

t_cm

t_CB1

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Awaiting command

Playing phrase 1

Playing phrase 2

Status

Address is being controlled

When making continuous playbacks, input the PLAY command for the next phrases within the specified time period (tcm)

after the NCR of the corresponding channel changes to "H" level, so that the LSI plays back the next phrases without silence

sounds after the current phrase playback ends.

When the playback is not continuous, input the PLAY command for the next phrases after confirming the playback is

completed by RDSTAT command, etc.

51/123

FEDL22Q62X-06

ML22Q62X

● Playback start timing by START command

START command

CSB

SCK

SI

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

*1

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

When the START command is input, the address data of the phrase to be played after the command processing time (t_CB2) is

read from the flash memory. When the phrase address data is read, the specified phrase starts playback, and when playback is

completed, the BUSYB signal of the playback channel becomes "H" level.

The NCR signal goes to the "L" level during playback preparation, and goes to the "H" level when playback preparation is

completed and playback starts. When the NCR signal of the playback channel becomes "H" level, the START command of

the next phrase to be played can be accepted.

*1 The length of the "L" interval in the BUSYBn is (tCB2+ sound production time).

52/123

FEDL22Q62X-06

ML22Q62X

● Continuous playback timing by START command

FADR command

1^stbyte 2^ndbyte

START command

CSB

SCK

SI

t_cm

t_CB1

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Awaiting command

Playing phrase 1

Playing phrase 2

Status

Address is being controlled

When making continuous playbacks, input the START command for the next phrases within the specified time period (tcm)

after the NCR of the corresponding channel changes to "H" level, so that the LSI plays back the next phrases without silence

sounds after the current phrase playback ends.

When the playback is not continuous, input the START command for the next phrases after confirming the playback is

completed by RDSTAT command, etc.

53/123

FEDL22Q62X-06

ML22Q62X

● STOP command (when the FAD bit is "L")

STOP command

CSB

SCK

SI

t_CB3

VOH

CBUSYB

VOL

NCRn

(internal)

fs×1cycle

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Playing

Awaiting command

Status

Command is being processed

● STOP command (when the FAD bit is "H")

STOP command

CSB

SCK

SI

t_CB3

VOH

CBUSYB

VOL

NCRn

(internal)

Changed by sampling

frequency^*1

BUSYBn

(internal)

1/2SPVDD

SPM

SPP

Playing

Awaiting command

Status

Command is being processed

*1 The duration of the BUSYBn varies depending on the sampling frequency groups.

At 10.7/21.3kHz

: Approx. 3ms

: Approx. 5ms

: Approx. 4ms

: Approx. 2.9ms

: Approx. 2.7ms

At 6.4/12.8/25.6kHz

At 8.0/16.0/32.0kHz

At 11.025/22.05/44.1kHz

At 12.0/24.0/48.0kHz

54/123

FEDL22Q62X-06

ML22Q62X

● Playback start timing by MUON command

MUON command

1^stbyte

MUON command

2^ndbyte

CSB

SCK

SI

t_CB1

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

*1

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

Command is being processed

When the first byte of the MUON command is input, the device waits for the input of the second byte after the command

processing time (t_CB1). When the second byte is entered, the silence time is calculated after the command processing time

(t_CB2). When the calculation of the silence duration is completed, the calculated silence is played back, and when the

playback is completed, the BUSYB signals of the playback channels become "H" level.

The NCR signal becomes "L" level during playback preparation, and becomes "H" level when playback preparation is

completed and playback starts. When the NCR signal of the playback channel becomes "H" level, the PLAY command of the

next phrase to be played can be accepted.

*1 The length of the "L" interval of the BUSYBn is (tCB2+ silence playback time).

55/123

FEDL22Q62X-06

ML22Q62X

● Continuous playback timing by MUON command

PLAY command

2^ndbyte

MUON command

1^stbyte 2^ndbyte

PLAY command

1^stbyte 2^ndbyte

CSB

SCK

SI

t_cm

t_CB1

t_cm

t_CB1

t_CB2

CBUSYB ^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

1/2SPVDD

SPM

1/2SPVDD

SPP

Awaiting command

Playing

Silence is being inserted

Playing

Status

Address is being controlled

Waiting for silence insertion to be finished

After the PLAY command is input, the CBUSYB signal and NCR signal change to "H" level when the address management

of phrase 1 is completed and start playing back. Input the MUON command after the CBUSYB signal changed to "H" level.

After the MUON command is received, the LSI is in a state waiting for the end of playback of phrase 1 and the NCR signal

remains "L" level until the end of playback.

When the playback of phrase 1 ends, playback of the silence sound starts and the NCR signal changes to "H" level. After the

NCR signal of the corresponding channel changes to "H" level, send the PLAY command again to playback the phrase 1.

The NCR signal changes to "L" level again after the PLAY command is received and the LSI is in a state waiting for the end

of the playback of silence sound.

After ending the playback of silence sound and starting the playback of phrase 1, the NCR signal changes to "H" level and

LSI is in state that accepts the next PLAY or MUON command.

The BUSYB signal remains "L" level until the sequence of playback is completed.

When making continuous playbacks, input the MUON/PLAY/START command for the next phrases within 10ms (tcm)

after the NCR of the corresponding channel changes to "H" level.

When the playback is not continuous, input the MUON/PLAY/START command for the next phrases after confirming the

playback is completed by RDSTAT command, etc.

56/123

FEDL22Q62X-06

ML22Q62X

● Repeat playback setting/release timing by SLOOP/CLOOP command

SLOOP command

CLOOP command

PLAY command

^ndbyte

2

CSB

SCK

SI

t_cm

t_CB1

t_CB2

VOH

VOL

CBUSYB

NCRn

(internal)

BUSYBn

(internal)

1/2SPVDD

SPM

SPP

Awaiting command

1st Repeat playing

2nd Repeat playing

Awaiting command

Status

Address is being controlled

Command is being processed

The SLOOP command is valid only during playback. After the PLAY command is input, input the SLOOP command within

the specified period (t_cm) after the NCR of the corresponding channel becomes "H" level. This enables the SLOOP command

and repeats playback. While the repeat playback mode is set, the NCR signal is "L" level.

57/123

FEDL22Q62X-06

ML22Q62X

● Change volume timing by CVOL command

CVOL command

1^stbyte

CVOL command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB ^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

*1

Volume transition time

SPM

SPP

Awaiting command

Status

Command is being processed

*1 Refer to the "FADE command" for more information on volume-transition time.

● RDSTAT command timing

RDSTAT command

1^stbyte

2^ndbyte

CSB

SCK

SI

Hi-Z

t_CB1

SO

CBUSYB ^VOH

VOL

NCR

(internal)

BUSYB

(internal)

Under

reading

Awaiting command

Status

Command is being processed

58/123

FEDL22Q62X-06

ML22Q62X

● RDVER command timing

RDVER command

1^stbyte

2^ndbyte

CSB

SCK

SI

Hi-Z

t_CB1

SO

CBUSYB ^VOH

VOL

NCR

(internal)

BUSYB

(internal)

Under

reading

Awaiting command

Status

Command is being processed

● RDERR command timing

RDERR command

1^stbyte

2^ndbyte

CSB

SCK

SI

Hi-Z

t_CB1

SO

CBUSYB ^VOH

VOL

NCR

(internal)

BUSYB

(internal)

Under

reading

Awaiting command

Status

Command is being processed

59/123

FEDL22Q62X-06

ML22Q62X

● OUTSTAT command timing

OUTSTAT command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

ERR

(internal)

STATUS1

STATUS2

ch0 NCR output

ch1 BUSYB output

output status

● SAFE command timing

SAFE command

1^stbyte

2^ndbyte

CSB

SCK

SI

t_CB1

VOH

VOL

CBUSYB

NCR

(internal)

BUSYB

(internal)

Awaiting

command

Awaiting

command

Awaiting command

Status

Command is being processed

● ERRCL command timing

ERRCL command

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

RDERR

00h

ERR register

(internal)

20h

00h

60/123

FEDL22Q62X-06

ML22Q62X

● Setting timing of playback phrases by FADR2 command

FADR2 command

1^stbyte

FADR2 command FADR2 command

2^ndbyte

3^rdbyte

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

Awaiting command

Status

Command is being processed

● Playback start timing by PLAY2 command

PLAY2 command PLAY2 command PLAY2 command

1^stbyte

2^ndbyte

3^rdbyte

CSB

SCK

SI

t_CB1

t_CB2

CBUSYB^VOH

VOL

NCRn

(internal)

*1

BUSYBn

(internal)

1/2VDD

SPM

1/2VDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

Command is being processed

When the first byte of the PLAY command is input, the 2nd byte waits for input after the command processing time (t_CB1),

and when the 2nd byte is input, the 3rd byte waits for input after the command processing time (t_CB1). When the third byte is

entered, the address data of the phrase to be played after the command processing time (t_CB2) is read from the flash memory.

When the phrase address data is read, the specified phrase is played back, and when playback is completed, the BUSYB

signal of the playback channel becomes "H" level.

The NCR signal goes to the "L" level during playback preparation, and goes to the "H" level when playback preparation is

completed and playback starts. When the NCR signal of the playback channel becomes "H" level, the PLAY command of the

next phrase to be played can be accepted.

*1 The length of the "L" interval in the BUSYBn is (tCB2+ sound production time).

61/123

FEDL22Q62X-06

ML22Q62X

■ Command

● Command list

Each command is configured in 1-byte (8-bit) units. The PUP, WDTCL, PDWN, START, STOP, SLOOP, CLOOP and

ERRCL commands are configured by one byte, the FADR2 and PLAY2 command are configured by three bytes, and the

other commands are configured by two bytes.

Do not enter command that is not described in this manual. Enter the command with the CBUSYB "H".

Command

name

PUP

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

DAMP

AEN0

0

WCM

HPF

POP

0

AMODE

AVOL

FAD

DAG1

DAG0

AIG1

AIG0

1

AEN1

0

AV5

AV4

AV3

1

AV2

1

0

FADE

FCON2

0

FCON1

0

FCON0

0

FADE

0

1

FDIRECT

PRT7

PRT6

PRT5

PRT4

PRT3

0

PRT2

1

PRT1

0

PRT0

0

WDTCL

PDWN

0

1

0

1

0

1

F9

F8

C1

C0

FADR

PLAY

F7

F6

F5

F4

F3

F2

F1

F0

0

1

0

F9

F8

C1

C0

F7

F6

F5

F4

F3

F2

F1

F0

START

STOP

0

1

0

1

CH3

M3

CH3

CV5

0

CH2

M2

CH2

CV4

0

CH1

M1

CH0

M0

CH0

CV2

0

1

0

1

MUON

M7

M6

M5

M4

SLOOP

CLOOP

1

0

CH1

CV3

0

1

0

1

0

1

0

CVOL

0

CV1

CV0

CV6

1

0

1

RDSTAT

RDVER

NCR3

0

NCR2

1

NCR1

0

NCR0

0

BUSYB3

BUSYB2

BUSYB1

BUSYB0

1

VER7

1

0

VER6

0

1

VER5

1

VER4

1

VER3

1

VER2

0

VER1

0

VER0

0

RDERR

OUTSTAT

FADR2

WCMER

R

OSCERR

RSTERR

WDTERR

ROMERR

SPDERR TSDERR DCDERR

1

0

CH3

0

CH2

1

0

PORT

STA1

STA0

CH1

CH0

0

1

0

C1

C0

F11

F3

F10

F2

F9

F8

F7

F6

F5

F4

F1

F0

1

0

1

0

PLAY2

0

C1

C0

F11

F3

F10

F2

F9

F8

F7

F6

F5

F4

F1

F0

1

OSCEN

1

RSTEN

1

0

WDTEN

1

ROMEN

1

0

DCDEN

1

0

SAFE

SPDEN

1

TSDEN

1

WCMEN

1

ERRCL

62/123

FEDL22Q62X-06

ML22Q62X

● Description of Command Functions



PUP command

・ Command

0

WCM

The PUP command shifts from the power-down state to the command standby state.

Since only the PUP command is accepted when the LSI is in the power-down state, the command is ignored if another

command is input.

To return to the power-down mode, enter the PDWN command.

The WCM bit is used to set the mode for inputting command and data two-times. When this bit is set to "1", the subsequent

command and data inputs are set to the two-times input mode, and the command is accepted only when they match.

If they do not match, the accepted command is discarded. Refer to the "RDSTAT command", "OUTSTAT command", and

"SAFE command" for handling when a mismatch occurs.

WCM

Description

0

1

Do not use input mode two-times. (Initial value)

Use the two-times input mode

For the power-up timing by the PUP command, refer to the "Power-up timing" in the timing chart.

63/123

FEDL22Q62X-06

ML22Q62X



AMODE command

・ Command

0

1

DAMP

HPF

POP

1st byte

2nd byte

FAD DAG1 DAG0 AIG1 AIG0 AEN1 AEN0

The AMODE command sets the analog part.

The AMODE command is ignored during power-down, power-up transition, power-down transition and playback sound.

When the PDWN command is input while powering up the analog parts, the LSI power downs without pop noise

suppression. When power down with POP noise suppression, to set the PDWN command after powering down with

AMODE command.

To perform power-down under a setting condition that differs from the power-up condition of the analog unit, set the

AMODE command to set the power-down condition again.

To power up the analog part, set the CVOL command to 00h (initial value) and then enter the AMODE command.

The settings are initialized when the reset is released or when the PDWN command is inputted.

Each setting is as follows.

DAMP

Description

0

1

Use Class AB amplifier for speaker amplifier output.

Use Class D amplifier for speaker amplifier output.

When using line amplifier and using analog mixing from the AIN pin, set DAMP = "0" (Class AB amplifier is used).

HPF

Description

0

1

No high-pass filter is used.

Use a high-pass filter with a cut-off frequency of 200Hz

FAD

Description

0

1

Fade-out is not processed when inputting STOP command.

Fade out when inputting STOP command

The fade-out processing BUSYB signal becomes "L" and becomes "H" after processing is completed.

DAG1 DAG0

Description

Internal DAC signal input OFF

0

1

0

1

0

1

Internal DAC signal input ON (-6 dB)

Internal DAC signal input ON (0dB)

Internal DAC signal input ON (0dB) (setting prohibited)

The setting is enabled in the speaker amplifier output mode when using Class AB amplifier.

Refer to the "Volume Settings" in the "Function description".

AIG1

AIG0

Description

0

1

0

1

0

1

Analog input from the AIN pin OFF

Analog input from AIN pin ON (-6 dB)

Analog input from AIN pin ON (0dB)

Analog input from AIN pin ON (0dB) (setting prohibited)

Input the sound signals to the AIN pin after CBUSYB pin becomes "H" by the AMODE command.

The setting is enabled in the speaker amplifier output mode only when using Class AB amplifier.

Refer to the "Volume Settings" in the "Function description".

64/123

FEDL22Q62X-06

ML22Q62X

POP

Description

Without pop noise suppression

With pop noise suppression

0

1

This bit is valid when line amplifier output is selected.

When power up with pop noise suppression, the line amplifier output rises from the DGND level to the SG level at

the specified time (tPUPA2).When power down with pop noise suppression, the line amplifier output falls from the

SG level to the DGND level at the specified time (tPDA2).

When power up without pop noise suppression, the line amplifier output rises from the DGND level to the SG level

at the specified time (tPUPA3).When power down without pop noise suppression, the line amplifier output falls

from the SG level to the DGND level at the specified time (tPDA3).

The settings of the AEN1/AEN0/POP bits for power-down and power-up of the analog section when the speaker amplifier

output and line amplifier output are as follows.

Mode

AEN1 AEN0

POP

Description

In the power-down state or

changeover to the power-down state.

In the power-up state or

changeover to the power-up state

In the power-down state or

changeover to the power-down state without Pop Noise Suppression

In the power-up state or

changeover to the power-up state without Pop Noise Suppression

In the power-down state or

*1

0

1

0

1

0

1

0

Speaker amplifier

output^*2

(class AB/class D)

*1

0

1

Line amplifier output

(When using SPP pin)

changeover to the power-down state with pop noise suppression

In the power-up state or

changeover to the power-up state with pop noise suppression

*1 Settings can be enabled for both 0 and 1.

*2 Do not set AEN1=”1” when using class D amplifier with speaker amplifier output (DAMP=”1”).

65/123

FEDL22Q62X-06

ML22Q62X

Pin states at AMODE power-down are as follows.

Analog output pin

Condition

2.5V(typ)

3.0V(typ)

DGND

V_DDL

V_DDR

SG

SPM

SPP

HiZ

SPGND

The timing of AMODE command is shown in the timing chart.

"Speaker amplifier power-up timing (DAMP bit "0", AEN1 bit "0", AEN0 bit "0"→ "1")"

"Speaker amplifier power-up timing (DAMP bit "1", AEN1 bit "0", AEN0 bit "0"→ "1")"

"Line amplifier power-up timing (DAMP bit = "0", POP bit = "1", AEN1 bit = "0" → "1", AEN0 bit = "0") "

"Line amplifier power-up timing (DAMP bit = "0", POP bit = "0", AEN1 bit = "0" → "1", AEN0 bit = "0")"

"Speaker amplifier power-down timing (DAMP bit "0", AEN1 bit "0", AEN0 bit "1"→"0")"

"Speaker amplifier power-down timing (DAMP bit "1", AEN1 bit "0", AEN0 bit "1"→"0")"

"Line amplifier power-down timing (DAMP bit = "0", POP bit = "1", AEN1 bit = "1" → "0", AEN0 bit = "0")"

"Line amplifier power-down timing (DAMP bit = "0", POP bit = "0", AEN1 bit = "1" → "0", AEN0 bit = "0")"

66/123

FEDL22Q62X-06

ML22Q62X



AVOL command

・ Command

0

1

0

1st byte

2nd byte

AV5 AV4 AV3 AV2

The AVOL command sets the volume of the speaker amplifier. This command can be input regardless of the NCR signal

status.

The initial value after reset release is set to-4.0dB. Also, the setting values of the AVOL command are retained when the

STOP command is inputted, but they are initialized when the power is down.

AV5-AV2

Description

+12.0dB

+10.0dB

AV5-AV2

Description

-8.0dB

F

E

D

C

B

A

9

7

6

5

4

3

2

1

0

-12.0dB

-18.0dB

-26.0dB

-34.0dB

Prohibited

OFF

+8.0dB

+6.0dB

+4.0dB

+2.0dB

+0.0dB

8

-4.0dB (initial value)

For timing of the AVOL command, refer to the "Change volume timing by AVOL command" in the timing chart.

67/123

FEDL22Q62X-06

ML22Q62X



FADE command

・ Command

0

1

0

1st byte

2nd byte

FCON2

FCON1

FCON0

FADE

The FADE command sets the Fade function. This command can be input regardless of the NCR signal status.

By using the fade function, the volume changes stepwise when the volume is changed by the CVOL command.

FADE

Description

Fade function disabled (initial value)

Fade function enabled

0

1

FCON2 to FCON0 set the volume that changes at every unit-time (sampling group period ^*1) when the volume is changed to

the volume set by the CVOL command or the PAN command.

FCON2 FCON1

FCON0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Volume change in 0 dB × 128/32768 steps

Volume change in 0 dB × 64/32768 steps

Volume change in 0 dB × 32/32768 steps

Volume change in 0 dB × 16/32768 steps

Volume change in 0 dB × 8/32768 steps

Volume change in 0 dB × 4/32768 steps

Volume change in 0 dB × 2/32768 steps

Volume change in 0 dB × 1/32768 steps

The smaller the voltage step that changes for each sampling frequency group, the less the pop noise, but the longer the

transition time until the set volume is reached. The transition time is expressed by the following equation.

Volume-transition time for CVOL command

=|[Current CVOL setting]-[New CVOL setting]|

× [Sampling-frequency group ^*1

]

× {264 ÷ (256 ÷ 2^[FCON2-FCON0 setting])}^*2

*1 Sampling frequency group

At 10.7/21.3kHz:

At 6.4/12.8/25.6kHz:

At 8.0/16.0/32.0kHz:

At 11.025/22.05/44.1kHz:

At 12.0/24.0/48.0kHz:

23.44μs

39.06μs

31.25μs

22.68μs

20.83μs

*2 Rounding up after the decimal point

For the timing of the FADE command, refer to the "FADE command timing" in the timing chart.

68/123

FEDL22Q62X-06

ML22Q62X

 FDIRECT command

・ Command

0

1

0

1st byte

2nd byte

PRT7

PRT6

PRT5

PRT4

PRT3

PRT2

PRT1

PRT0

The FDIRECT command controls accesses to the flash memory using the clock-synchronous serial interface.

Input the command after inputting the PUP command.

If the protection code of the flash memory area is not 0x69 and the protection codes (PRT7 to PRT0) entered in the second

byte match the protection code set when creating sound data, the flash memory access mode is entered. After that, the flash

memory can be accessed using the clock synchronous serial interface.

If the protection code set when creating sound data is 0x69, the flash memory does not change to flash memory access mode

even if the code matches.

To cancel the serial memory access mode, insert a reset (RESETB = "L") and conduct initialization or turn off the power

supply.

For the protection codes of the flash memory area, refer to the "Speech LSI Utility Setting Items".

For the timing of the FDIRECT command, refer to the "FDIRECT command timing" in the timing chart.

69/123

FEDL22Q62X-06

ML22Q62X



WDTCL command

・ Command

0

1

0

1

0

The WDTCL command clears the watchdog timer counter (WDT counter). This command can be input regardless of the

NCR signal status.

For information about the operation of the watchdog timer, refer to the "Misoperation detection and failure detection

functions (Watchdog timer overflow detection)" in the "Function description".

For the timing of WDTCL command, refer to the "WDTCL command timing" in the timing chart.

70/123

FEDL22Q62X-06

ML22Q62X



PDWN command

・ Command

0

1

0

The PDWN command is used to shift from the command standby state to the power-down state. The various settings are

initialized, so the initial settings are required after power-up. It is invalid when the BUSYB signals of any channels are "L".

After inputting the PDWN command, oscillation stops following the elapse of the command processing time (t_PD) .

The states of the analog output pins during power-down are shown below.

Analog output pin

Condition

DGND

HiZ

V_DDL

V_DDR

SG

SPM

SPP

SPGND

For the power-down timing by PDWN command, refer to the "Power-Down timing" in the timing chart.

71/123

FEDL22Q62X-06

ML22Q62X



FADR command

・ Command

0

1

F9

F3

F8

F2

C1

F1

C0

F0

1st byte

2nd byte

F7

F6

F5

F4

The FADR command sets the channels and phrases to be played. This command can be input when the NCR signal of the

corresponding channel is "H" level.

Playback is started by the START command after the playback phrases of each channel are specified.

The phrases (F9-F0) to be played back are specified when creating sound data. Set the phrase specified when creating.

This command can only set up to 0 to 1023 phrases. To specify 1024 phrases or more, use FADR2 command.

The channel settings are as follows:

C1

C0

Description

0

1

0

1

0

1

Channel 0

Channel 1

Channel 2

Channel 3

For the timing of the FADR command, refer to the "Setting playback phrases using FADR command" in the timing chart.

72/123

FEDL22Q62X-06

ML22Q62X



PLAY command

・ Command

0

1

0

F9

F3

F8

F2

C1

F1

C0

F0

1st byte

2nd byte

F7

F6

F5

F4

The PLAY command is played by specifying channels and phrases. This command can be input when the NCR signal of the

corresponding channel is "H" level.

The phrases (F9-F0) to be played back are specified when creating sound data. Set the phrase specified when creating.

This command can only set up to 0 to 1023 phrases. To specify 1024 phrases or more, use PLAY2 command.

The channel settings are as follows:

C1

C0

Description

0

1

0

1

0

1

Channel 0

Channel 1

Channel 2

Channel 3

For the playback start timing by the PLAY command, refer to the "Playback start timing by PLAY command" in the timing

chart.

For the timing of continuous playback, refer to the "Continuous playback timing by PLAY command" in the timing chart.

73/123

FEDL22Q62X-06

ML22Q62X



START command

・ Command

0

1

0

1

CH3

CH2

CH1

CH0

1st byte

The START command starts playing back the specified channels. Specify the phrase to be played by the FADR command

prior to entering the START command. Setting the CH0 to CH3 bit to 1 plays back the corresponding channel. This

command can be input when the NCR signal of the corresponding channel is "H" level.

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

When this bit is set to 1, channel 0 is played back.

When this bit is set to 1, channel 1 is played back.

When this bit is set to 1, channel 2 is played back.

When this bit is set to 1, channel 3 is played back.

Be sure to specify one of the channels for the channel setting (CH0-CH3).

Do not input it to "0" (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For the playback start timing by the START command, refer to the "Playback start timing by START command" in the

timing chart.

For the timing of continuous playback, refer to the "Continuous playback timing by START command" in the timing chart.

74/123

FEDL22Q62X-06

ML22Q62X



STOP command

・ Command

0

1

0

CH3

CH2

CH1

CH0

1st byte

The STOP command stops playing back the specified channel. Setting the CH0 to CH3 bit to "1" stops playback of the

corresponding channel. When the corresponding channel stops playing back, the NCR and BUSYB signals become "H".

The STOP command can be input regardless of the status of the NCR during playback operation. However, following the

elapse of CBUSYB "L" level output time 3 (tCB3), input the next command after confirming that the BUSYB signal

becomes "H".

If the BUSYB signal does not become "H", enter the STOP command again.

Refer to the "Playback stop flow" in the command flowchart for more information.

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 stops channel 0.

Setting this bit to 1 stops channel 1.

Setting this bit to 1 stops channel 2.

Setting this bit to 1 stops channel 3.

Be sure to specify one of the channels for the channel setting (CH0-CH3).

Do not input it to "0" (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For the timing of the STOP command, refer to the "STOP command (when the FAD bit is "L")" and "STOP command (when

the FAD bit is "H")" in the timing chart.

75/123

FEDL22Q62X-06

ML22Q62X



MUON command

・ Command

0

1

CH3 CH2 CH1 CH0

M3 M2 M1 M0

1st byte

2nd byte

M7

M6

M5

M4

The MUON command inserts silence between two phrases to be played. This command can be inputted when the NCR

signal of the corresponding channel is "H" level.

Repeated playing back (the SLOOP command) of the MUON command is not possible.

The silence duration (t_mu) is specified by the M7-M0 bits and can be set from 20ms to 1,024ms in 252 steps at 4ms intervals.

The equation for setting the silence duration (t_mu) is as follows.

However, set the silence setting (M7-M0) to 04h or more (t_mu≥20ms).

t_mu=(2⁷×(M7)+2⁶×(M6)+2⁵×(M5)+2⁴×(M4)+2³×(M3)+2²×(M2)+2¹×(M1)+2⁰×(M0)+1)×4ms

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 inserts silence into channel 0.

Setting this bit to 1 inserts silence into channel 1.

Setting this bit to 1 inserts silence into channel 2.

Setting this bit to 1 inserts silence into channel 3.

Be sure to specify one of the channels for the channel setting (CH0-CH3).

Do not input it to "0" (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For the timing of the MUON command, refer to the "Playback start timing by MUON command" in the timing chart.

For the timing of continuous playback, refer to the "Continuous playback timing by MUON command" in the timing chart.

76/123

FEDL22Q62X-06

ML22Q62X



SLOOP command

・ Command

1

0

CH3

CH2

CH1

CH0

1st byte

The SLOOP command sets the repeat playback of the specified channel. Setting the CH0 to CH3 bit to 1 repeatedly plays

back the corresponding channel. This command can be input when the NCR signal of the corresponding channel is "H" level.

When repeat playback is set, playback is repeatedly performed until the repeat playback setting is canceled by the CLOOP

command or playback is stopped by the STOP command. Also, if the phrase has been edited, the edited phrase is played

repeatedly.

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 repeats playback on channel 0.

Setting this bit to 1 repeats playback on channel 1.

Setting this bit to 1 repeats playback on channel 2.

Setting this bit to 1 repeats playback on channel 3.

Be sure to specify one of the channels for the channel setting (CH0-CH3).

Do not input it to "0" (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For the timing of the SLOOP command, refer to the "Repeat playback setting/release timing by SLOOP/CLOOP command"

in the timing chart.

77/123

FEDL22Q62X-06

ML22Q62X



CLOOP command

・ Command

1

0

1

CH3

CH2

CH1

CH0

1st byte

The CLOOP command releases repeat playback of the specified channel. This command can be input regardless of the NCR

signal status.

Setting the CH0 to CH3 bit to "1" cancels repeat playback of the corresponding channel. When repeat playback is released,

the NCR signal becomes "H" level.

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 cancels repeat playback on channel 0.

Setting this bit to 1 cancels repeat playback on channel 1.

Setting this bit to 1 cancels repeat playback on channel 2.

Setting this bit to 1 cancels repeat playback on channel 3.

Be sure to specify one of the channels for the channel setting (CH0-CH3).

Do not input it to (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For the timing of the CLOOP command, refer to the "Repeat playback setting/release timing by SLOOP/CLOOP command"

in the timing chart.

78/123

FEDL22Q62X-06

ML22Q62X



CVOL command

・ Command

1

0

1

0

CH3 CH2 CH1 CH0

1st byte

2nd byte

CV1 CV0 CV6 CV5 CV4 CV3 CV2

The CVOL command sets the playback volume of the specified channel. This command can be input regardless of the NCR

signal status.

Setting the CH0 to CH3 bit to 1 sets the volume of the corresponding channel.

The volume can be set at 128 levels.

The setting values are initialized when a reset is inserted (RESETB = "L") and PDWN command is input.

The CV1 and CV0 of the second bytes of the CVOL command are located at the top of the CV6 to CV2.

CV1,CV0,

CV6-CV2

CV1,CV0,

CV6-CV2

CV1,CV0,

CV6-CV2

CV1,CV0,

CV6-CV2

Description

-2.59dB

Description

-6.31dB

Description

-12.93dB

0.00dB

(initial value)

00

08

10

18

20

40

60

01

21

41

61

02

22

42

62

03

23

43

63

04

24

44

64

05

25

45

65

06

26

46

66

07

27

47

67

28

48

68

09

29

49

69

0A

2A

4A

6A

0B

2B

4B

6B

0C

2C

4C

6C

0D

2D

4D

6D

0E

2E

4E

6E

0F

2F

4F

6F

30

50

70

11

31

51

71

12

32

52

72

13

33

53

73

14

34

54

74

15

35

55

75

16

36

56

76

17

37

57

77

38

58

78

19

39

59

79

1A

3A

5A

7A

1B

3B

5B

7B

1C

3C

5C

7C

1D

3D

5D

7D

1E

3E

5E

7E

1F

3F

5F

7F

-0.07dB

-0.14dB

-0.21dB

-0.28dB

-0.36dB

-0.43dB

-0.50dB

-0.58dB

-0.65dB

-0.73dB

-0.81dB

-0.88dB

-0.96dB

-1.04dB

-1.12dB

-1.20dB

-1.28dB

-1.36dB

-1.44dB

-1.53dB

-1.61dB

-1.70dB

-1.78dB

-1.87dB

-1.96dB

-2.04dB

-2.13dB

-2.22dB

-2.31dB

-2.41dB

-2.50dB

-2.69dB

-2.78dB

-2.88dB

-2.98dB

-3.08dB

-3.18dB

-3.28dB

-3.38dB

-3.49dB

-3.59dB

-3.70dB

-3.81dB

-3.92dB

-4.03dB

-4.14dB

-4.25dB

-4.37dB

-4.48dB

-4.60dB

-4.72dB

-4.84dB

-4.97dB

-5.09dB

-5.22dB

-5.35dB

-5.48dB

-5.61dB

-5.74dB

-5.88dB

-6.02dB

-6.16dB

-6.45dB

-6.60dB

-6.75dB

-6.90dB

-7.06dB

-7.22dB

-7.38dB

-7.55dB

-7.72dB

-7.89dB

-8.06dB

-8.24dB

-8.43dB

-8.61dB

-8.80dB

-9.00dB

-9.20dB

-9.40dB

-9.61dB

-9.83dB

-10.05dB

-10.27dB

-10.50dB

-10.74dB

-10.99dB

-11.24dB

-11.50dB

-11.77dB

-12.04dB

-12.33dB

-12.62dB

-13.24dB

-13.57dB

-13.91dB

-14.26dB

-14.63dB

-15.02dB

-15.42dB

-15.85dB

-16.29dB

-16.76dB

-17.26dB

-17.79dB

-18.35dB

-18.95dB

-19.59dB

-20.28dB

-21.04dB

-21.87dB

-22.78dB

-23.81dB

-24.97dB

-26.31dB

-27.89dB

-29.83dB

-32.33dB

-35.85dB

-41.87dB

-44.37dB

-47.89dB

-53.91dB

OFF

79/123

FEDL22Q62X-06

ML22Q62X

The volume can also be set at 32 levels by fixing the CV1 and CV0 bits to "0".

CV6-CV2

00

Description

CV6-CV2

10

Description

0.00dB (initial value)

-0.28dB

-0.58dB

-0.88dB

-1.20dB

-1.53dB

-1.87dB

-2.22dB

-2.59dB

-2.98dB

-3.38dB

-3.81dB

-4.25dB

-4.72dB

-5.22dB

-5.74dB

-6.31dB

-6.90dB

-7.55dB

-8.24dB

-9.00dB

01

02

03

04

05

06

07

08

11

12

13

14

15

16

17

18

-9.83dB

-10.74dB

-11.77dB

-12.93dB

-14.26dB

-15.85dB

-17.79dB

-20.28dB

-23.81dB

-29.83dB

-44.37dB

09

19

0A

0B

0C

0D

0E

0F

1A

1B

1C

1D

1E

1F

The channel settings are as follows:

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 set the volume of channel 0.

Setting this bit to 1 set the volume of channel 1.

Setting this bit to 1 set the volume of channel 2.

Setting this bit to 1 set the volume of channel 3.

Be sure to specify one of the channels for the channel setting (CH0-CH3). When multiple channels are specified, the volume

of the specified channels is set.

Do not input it to "0" (all “0”) with specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

For timing of the CVOL command, refer to the "Change volume timing by CVOL command" in the timing chart.

80/123

FEDL22Q62X-06

ML22Q62X



RDSTAT command

・ Command

1

0

1

0

1st byte

The RDSTAT command reads the internal operating states. This command can be input regardless of the NCR signal status.

When reading the status of the second byte after command input, set the SI pin to "L".

The internal operating states read in the second byte are as follows:

2nd byte

D7

D6

D5

D4

D3

D2

D1

D0

Output data

BUSYB3

BUSYB2

BUSYB1

BUSYB0

NCR3

NCR2

NCR1

NCR0

The NCR signal outputs "L" during command processing and playback standby, and outputs "H" in other states.

The BUSYB signal outputs "L" during command processing and playback sound, and outputs "H" in other states.

D7 to D0

BUSYB3

BUSYB2

BUSYB1

BUSYB0

NCR3

Description

BUSYB outputs of channel 3

BUSYB outputs of channel 2

BUSYB outputs of channel 1

BUSYB outputs of channel 0

NCR output of channel 3

NCR output of channel 2

NCR output of channel 1

NCR output of channel 0

NCR2

NCR1

NCR0

For the timing of the RDSTAT command, refer to the "RDSTAT command timing" in the timing chart.

81/123

FEDL22Q62X-06

ML22Q62X



RDVER command

・ Command

1

0

1

0

1

0

1st byte

The RDVER command read sound ROM information. This command can be input regardless of the NCR signal status.

When reading the sound ROM information in the second byte after command input, set the SI pin to "L".

The sound ROM information read in the second byte is as follows:

2nd byte

D7

D6

D5

D4

D3

D2

D1

D0

Output data

VER7

VER6

VER5

VER4

VER3

VER2

VER1

VER0

Sound ROM information can be set by using dedicated tool (Speech LSI Utility) when creating sound data.

For the timing of the RDVER command, refer to the "RDVER command timing" in the timing chart.

82/123

FEDL22Q62X-06

ML22Q62X



RDERR command

・ Command

1

0

1

0

ERSEL

1st byte

The RDERR command read misoperation detection and failure detection status. This command can be input regardless of

the NCR signal status. When reading error information in the second byte after command input, set the SI pin to "L".

If the outputs of misoperation detection and failure detection are selected by OUTSTAT command, and the read data is all

"L" even though STATUS1 or STATUS2 pin is "H", the read data cannot be read normally. Be sure to read it again.

The internal operating states read in the second byte are as follows:

2nd byte

D7

D6

D5

D4

D3

D2

D1

D0

Output data

OSCERR

RSTERR

WDTERR

ROMERR

SPDERR

TSDERR

DCDERR

WCMERR

Misoperation detection and failure detection status are as follows.

Error signal

WCMERR

Description

This bit is set to "1" when an error of the command is detected.

This bit is set to "1" when the disconnection of the speaker connected to the SPP and SPM pins is

detected.

DCDERR

TSDERR

SPDERR

This bit is set to "1" when the LSI temperature becomes 130°C or higher.

This bit is set to "1" when the SPP pin and the SPM pin are short-circuited, or when the SPP pin or

the SPM pin is short-circuited to GND.

ROMERR

WDTERR

This bit is set to 1 when an error is detected in the flash memory.

This bit is set to "1" when the first overflow of the watchdog timer counter occurs.

This bit is set to "1" when the second overflow of the watchdog timer counter occurs.

Alternatively, this bit is set to "1" when the RST counter, which starts operation by any of the error

detections, overflows.

RSTERR

OSCERR

This bit is set to "1" when the clock input from the crystal resonator or ceramic resonator is stopped.

For details on misoperation detection and failure detection, refer to the "Misoperation detection and failure detection

functions" in the "Function description".

For the timing of the RDERR command, refer to the "RDERR command timing" in the timing chart.

83/123

FEDL22Q62X-06

ML22Q62X



OUTSTAT command

・ Command

1

0

1

0

1st byte

2nd byte

PORT STA1 STA0

CH3

CH2

CH1

CH0

The OUTSTAT command selects the internal operating states output to the STATUS1 pin and STATUS2 pin.

This command can be input regardless of the NCR signal status.

PORT

Description

STATUS1 Pin setting

STATUS2 Pin setting

0

1

If the STATUS2 pin is set after the STATUS1 pin is set, the STATUS1 pin setting is retained.

In the initial setting, the NCR of channel 0 is selected for the STATUS1 pin, and the BUSYB of channel 0 is selected for the

STATUS2 pin.

STA1

STA0

Description

0

1

0

1

0

1

BUSYB

NCR

Misoperation detection and Failure Detection

Channeled

Description

CH0

CH1

CH2

CH3

Setting this bit to 1 selects channel 0.

Setting this bit to 1 selects channel 1.

Setting this bit to 1 selects channel 2.

Setting this bit to 1 selects channel 3.

Channel settings are enabled when BUSYB or NCR is specified in the STA1/STA0. Multiple channels can also be set.

The relations between the STATUS1 pin and the STA1/STA0/CH3/CH2/CH1/CH0 are shown below.

CH3 / CH2 / CH1 / CH0

STA1/STA0

BUSYB0

BUSYB1

BUSYB2

00

01

10/11

STATUS1 pin

BUSYB3

NCR0

NCR1

NCR2

NCR3

WCMERR

DCDERR

TSDERR

SPDERR

ROMERR

WDTERR

RSTERR

OSCERR

For the timing of the OUTSTAT command, refer to the "OUTSTAT command timing" in the timing chart.

84/123

FEDL22Q62X-06

ML22Q62X



FADR2 command

・ Command

1

0

1

0

1

0

1st byte

2nd byte

3rd byte

C1

F5

C0

F4

F11 F10

F3 F2

F9

F1

F8

F0

F7

F6

The FADR2 command sets the channels and phrases to be played. This command can be input when the NCR signal of the

corresponding channel is "H" level.

Playback is started by the START command after the playback phrases of the channels are specified.

The phrases (F11-F0) to be played back are specified when creating sound data. Set the phrase specified when creating.

The channel settings are as follows:

C1

C0

Description

0

1

0

1

0

1

Channel 0

Channel 1

Channel 2

Channel 3

When the number of phrases to be played is 1024 or less, the channels and phrases can be specified by FADR command.

For the timing of the FADR2 command, refer to the "Setting timing of playback phrases by FADR2 command" in the timing

chart.

85/123

FEDL22Q62X-06

ML22Q62X



PLAY2 command

・ Command

1

0

1

0

1

0

1st byte

2nd byte

3rd byte

C1

F5

C0

F4

F11 F10

F3 F2

F9

F1

F8

F0

F7

F6

The PLAY2 command is played by specifying channels and phrases. This command can be input when the NCR signal of the

corresponding channel is "H" level.

The phrases (F11-F0) to be played back are specified when creating sound data. Set the phrase specified when creating.

The channel settings are as follows:

C1

C0

Description

0

1

0

1

0

1

Channel 0

Channel 1

Channel 2

Channel 3

When the number of phrases to be played is 1024 or less, the channels and phrases can be specified by PLAY command.

For the playback start timing by the PLAY2 command, refer to the "Playback start timing by PLAY2 command" in the

timing chart.

86/123

FEDL22Q62X-06

ML22Q62X



SAFE command

・ Command

1

0

1

0

1st byte

2nd byte

OSCEN

RSTEN

WDTEN

ROMEN

SPDEN

TSDEN

DCDEN

WCMEN

The SAFE command is used to set the operation of the misoperation detection function and the failure detection function.

The initial value is the operation stop state ("0"). When this bit is set to "1", operation starts.

Error setting

WCMEN

DCDEN

Description

Set the command error detection.

Set the disconnection detection of the speakers connected to the SPP and SPM pins.

TSDEN

Set the LSI temperature error detection.

SPDEN^*2

ROMEN

WDTEN^*1

RSTEN^*1

Set the detection of short circuit between the SPP pin and the SPM pin.

Set error detection of flash memory.

Operate the watchdog timer and set overflow detection.

Operate the RST counter and set overflow detection, when any error is detected.

Enable the error output for the stop detection of clock input from a crystal resonator or ceramic

resonator.

OSCEN

*1 Do not set WDTEN and RSTEN to "1" at the same time. If these bits are set to "1" at the same time, only the RSTEN bit

is set to "1".

*2 Set SPDEN to “1” when mixing and playing using class D speaker amplifier. Refer to “Class D amplifier precaution on

mixing” in the “Function description”.

For details on misoperation detection and failure detection, refer to the "Misoperation detection and failure detection

functions" in the function description.

For the timing of the SAFE command, refer to the "SAFE command timing" in the timing chart.

87/123

FEDL22Q62X-06

ML22Q62X



ERRCL command

・ Command

1

The ERRCL command is a command that clears error bits that can be read by the RDERR command. This command can be

input regardless of the NCR signal status.

However, if the error continues, the error bit remains in the error status even if the ERRCL command is entered.

For the timing of the ERRCL command, refer to the "ERRCL command timing" in the timing chart.

88/123

FEDL22Q62X-06

ML22Q62X

■ Command Flowchart

● 1-byte command input flow (Applies to PUP, WDTCL, PDWN, START, STOP, SLOOP, CLOOP, and ERRCL

commands.)

Start

CBUSYB

"H"?

No

Yes

Command input

CBUSYB

"H"?

Yes

End

89/123

FEDL22Q62X-06

ML22Q62X

● 2-byte command input flow (Applies to AMODE, AVOL, FADE, FDIRECT, FADR, PLAY, MUON, CVOL, OUTSTAT,

and SAFE commands.)

Start

CBUSYB

No

"H"?

Yes

1st byte command input

CBUSYB

"H"?

Yes

2nd byte command input

CBUSYB

"H"?

No

Yes

End

90/123

FEDL22Q62X-06

ML22Q62X

● 3-byte command input flow (Applies to FADR2 and PLAY2 commands.)

Start

CBUSYB

No

"H"?

Yes

1st byte command input

CBUSYB

"H"?

Yes

2nd byte command input

CBUSYB

"H"?

No

Yes

3rd byte command input

CBUSYB

"H"?

No

Yes

End

91/123

FEDL22Q62X-06

ML22Q62X

● Read flow (Applies to RDSTAT, RDVER, RDERR commands)

Start

1st byte command input

CBUSYB

"H"?

No

Yes

Read status (SI="L")

End

92/123

FEDL22Q62X-06

ML22Q62X

● Power-on flow

Power on, RESETB "L"

Wait 10us

No

Yes

RESETB "H"

Power-down state

● MCU command interface flash memory access migration/cancel

Power-down state

PUP command

FDIRECT command

ChipErase

Wait 5s(typ)^*

StatusRead

Program 256byte units

Wait 0.4ms(typ)^*

StatusRead

Flash memory

access

No

Write end?

*:Wait times are checked by StautsRead

Yes

RESETB “L”

Power-down state

93/123

FEDL22Q62X-06

ML22Q62X

● Analog power-up flow

Power-down state

PUP command

※ When enabling the detection of

speaker disconnection and short

circuit

SAFE Command

Within 10 ms

AMODE Command

Analog power-up state

● Playback start flow

Analog power-up state

No

Playback end

Yes

※ Check that the BUSYB of all channels is 1.

(Check with RDSTAT commands or STATUS1/2 pins.)

Single-channel playback

Multi-channel playback

PLAY Command

FADR Command

START Command

Playback start

94/123

FEDL22Q62X-06

ML22Q62X

● Playback stop flow

During playback

STOP Command

t_CB3Wait

RDSTAT Command

CBUSYB

"H"?

No

Yes

Read status (SI="L")

BUSYB

"H"?

Yes

End

● Continuous playback flow

PLAY/START/MUON

Command

During playback

Within 10 ms

PLAY/START/MUON Commands

Start continuous playback

95/123

FEDL22Q62X-06

ML22Q62X

● Loop playback start flow

PLAY/START Command

During playback

Within 10 ms

SLOOP command

Start loop playback

● Loop playback stop flow

During loop playback

Stop after phrase ends

Forced stop

STOP Command

CLOOP command

Loop stop

● Power-down flow

Power-up state

PDWN Command

Power-down state

96/123

FEDL22Q62X-06

ML22Q62X

● Detailed flow of "Power-up → Playback → Power-down"

Power-down state

CBUSYB

A

No

"H"?

Yes

2nd byte of PLAY

Command

PUP command

CBUSYB

"H"?

No

CBUSYB

"H"?

Yes

RDSTAT Command

1st byte of SAFE command

CBUSYB

"H"?

CBUSYB

"H"?

No

Yes

Read status (SI="L")

2nd byte of SAFE

Command

BUSYB

"H"?

CBUSYB

"H"?

No

Yes

1st byte of AMODE

command

1st byte of AMODE

command

CBUSYB

"H"?

CBUSYB

"H"?

No

Yes

2nd byte of AMODE

Command

2nd byte of AMODE

Command

CBUSYB

"H"?

No

CBUSYB

"H"?

Yes

PDWN Command

1st byte of PLAY command

CBUSYB

"H"?

No

CBUSYB

"H"?

Yes

Power-down state

A

97/123

FEDL22Q62X-06

ML22Q62X

● Processing flow for speaker short detection

SPDERR occur

Check STATUS1, 2 pins "H"

RDERR Command

CBUSYB

"H"?

No

Yes

Read status (SI="L")

※ Confirm that the SPDERR bit is "H".

Playback end

Yes

STOP Command

No

1st byte of AMODE

command

CBUSYB

"H"?

No

Yes

CBUSYB

"H"?

RDSTAT Command

No

Yes

2nd byte of AMODE

Command

CBUSYB

"H"?

※ Speaker Mode Power-Down Setting

No

Yes

CBUSYB

"H"?

Read status (SI="L")

No

Yes

ERRCL Command

※ Clearing the ERR bit/ STATUS1,2 pins

BUSYB

"H"?

Yes

CBUSYB

"H"?

Yes

No

Command wait state

98/123

FEDL22Q62X-06

ML22Q62X

● 1-byte command input flow in two-times input mode

Start

Selects the output of misoperation detection and failure detection

to the STATUS1 or STATUS2 pin by OUTSTAT command.

First command input

Second command input

First ERRCL command input

Second ERRCL command

input

STATUS1, 2 pins

"L"?

No

Yes

STATUS1, 2 pins

No

"L"?

Yes

CBUSYB

"H"?

CBUSYB

"H"?

Yes

End

Yes

First command input

(inputting again)

Second command input

(inputting again)

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

Yes

End

99/123

FEDL22Q62X-06

ML22Q62X

● 2-byte command input flow in two-times input mode

Start

Selects the output of misoperation detection and failure detection

to the STATUS1 or STATUS2 pin by OUTSTAT command.

First command input

(1Byte)

First ERRCL command input

Second command input

(1Byte)

Second ERRCL command input

STATUS1, 2 pins

"L"?

No

Yes

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

CBUSYB

"H"?

Yes

First command input

(inputting again)

Second command input

(inputting again)

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

Yes

First command input

(2Byte)

First ERRCL command input

Second command input

(2Byte)

Second ERRCL command input

STATUS1, 2 pins

"L"?

No

STATUS1, 2 pins

"L"?

Yes

No

Yes

CBUSYB

"H"?

CBUSYB

"H"?

Yes

End

100/123

FEDL22Q62X-06

ML22Q62X

● 3-byte command input flow in two-times input mode

Start

Selects the output of misoperation detection and failure detection

to the STATUS1 or STATUS2 pin by OUTSTAT command.

First command input

(1Byte)

First ERRCL command input

Second command input

(1Byte)

Second ERRCL command input

STATUS1, 2 pins

"L"?

No

"L"?

Yes

CBUSYB

"H"?

CBUSYB

"H"?

Yes

First command input

(inputting again)

Second command input

(inputting again)

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

Yes

First command input

(2Byte)

Second command input

(2Byte)

First ERRCL command input

STATUS1, 2 pins

"L"?

Second ERRCL command input

No

Yes

STATUS1, 2 pins

"L"?

No

CBUSYB

"H"?

Yes

First command input

(3Byte)

CBUSYB

"H"?

Second command input

(3Byte)

Yes

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

Yes

End

101/123

FEDL22Q62X-06

ML22Q62X

● Read flowchart in two-times input mode (Applies to RDSTAT, RDVER commands)

Start

Selects the output of misoperation detection and failure detection

to the STATUS1 or STATUS2 pin by OUTSTAT command.

First command input

First ERRCL command input

Second command input

Second ERRCL command input

STATUS1, 2 pins

"L"?

No

Yes

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

CBUSYB

"H"?

Yes

First read

First command input

(inputting again)

Second read

Second command input

(inputting again)

End

STATUS1, 2 pins

"L"?

No

Yes

CBUSYB

"H"?

Yes

First read

Second read

End

102/123

FEDL22Q62X-06

ML22Q62X

● Read flowchart in two-times input mode (Applies to RDERR command)

Start

First command input

Second command input

CBUSYB

"H"?

No

Yes

First read

Second read

Read data

All "L"?

Yes

No

End

When the OUTSTAT command is used to select the misoperation detection and failure detection outputs and the STATUS1 or

STATUS2 pin is "H", if all the read data is "L", the data cannot be read normally. Read the data again.

103/123

FEDL22Q62X-06

ML22Q62X

■ Peripheral circuit

● Handling of SG Pin

The SG pin is the signal ground for the built-in speaker amplifier. Connect a capacitor between this pin and the SPGND to

prevent noises.

SG

Symbol

C9

Recommended Constant

0.1μF±20%

● Handling of V_DDLPin

The V_DDLpin is a power supply for the internal circuits. Connect a capacitor across the DGND to prevent noises and power

supply fluctuations. Please place it near the LSI on the user board.

Symbol

C8

Recommended Constant

1μF±20%

V_DDL

● Handling of V_DDRPin

The V_DDRpin is a power supply for the internal circuits. Connect a capacitor across the DGND to prevent noises and power

supply fluctuations. Please place it near the LSI on the user board.

When using the DV_DDpower supply voltage of 2.7V to 3.6V, connect to the DV_DDpower supply.

Symbol

C11

Recommended Constant

1μF±20%

V_DDR

● Power wiring

The power supply of this LSI is divided into the following three power supplies.

・ Digital power supply (DV_DD), digital GND (DGND)

・ Speaker amplifier power supply (SPV_DD), Speaker amplifier GND (SPGND)

・ Power supply for flash memory interface (IOV_DD

)

These power supplies can be used independently. However, use it in the condition of SPV_DD≥DV_DD

.

When using the same power supply, branch it from the root of the power supply for wiring.

● Bypass capacitor

To improve noise-resistance, place the bypass capacitor close to the LSI on the user board, and shorten the wiring as short as

possible without passing through the via.

Symbol

C3

Recommended Constant

3.3μF±20%

SPV_DD

DV_DD

IOV_DD

C4

0.1μF±20%

C5

3.3μF±20%

C6

0.1μF±20%

C7

1μF±20%

● Coupling capacitor

Insert when analog input from AIN pin.

Insert when using SPP pin as line amplifier output.

Symbol

Recommended Constant

AIN

SPP

C10

C11

0.1μF±20%

104/123

FEDL22Q62X-06

ML22Q62X

■ Application Circuit

● synchronous serial interfaces (DV_DD=2.7V to 3.6V)

The V_DDRhandling differs from the case where DV_DD=3.3V to 5.5V.

The power supply for the IRCSB, IRSCK, IRSO, IRSI and IRON pins is IOV_DD

.

If the crystal unit has a built-in capacitor, C1 and C2 are not needed.

105/123

FEDL22Q62X-06

ML22Q62X

● synchronous serial interfaces (DV_DD=3.3V to 5.5V)

The V_DDRhandling differs from the case where DV_DD=2.7V to 3.6V.

The power supply for the IRCSB, IRSCK, IRSO, IRSI and IRON pins is IOV_DD

.

If the crystal unit has a built-in capacitor, C1 and C2 are not needed.

106/123

FEDL22Q62X-06

ML22Q62X

■ Recommended ceramic resonator

Recommended ceramic resonators are shown below.

● MURATA Corporation

Frequency [Hz]

Product Name

Built-in load capacity [pF]

39

4M

CSTCR4M00G55B-R0

CSTCR4M09G55B-R0

4.096M

■ RC4MHz characteristic

RC4MHz characteristic is as follows.

4.31(+5%)

max

4.22(+3%)

4.096

min

3.97 (-3%)

3.89 (-5%)

-40

0

40

70

105

Operating temperature [^OC]

This graph is for reference only and does not guarantee the electrical characteristic.

107/123

FEDL22Q62X-06

ML22Q62X

■ Limitation on the operation time (Playback operating time)

This LSI operating temperature is 70^OC (max). But the average ambient temperature at 1W playback (8ohm drive) for 10

years in the reliability design is Ta=60^OC. (max (the package heat resistance θja=31.58[^OC/W]))

When this LSI operates 1W playback (8ohm drive) consecutively, the product life changes by the package temperature rise

by the consumption. This limitation does not matter in the state that a speaker amplifier does not play.

The factors to decide the operation time (playback operating time) are the average ambient temperature (Ta), playback Watts

(at the speaker drive mode), the soldering area ratio, and so on. In addition, the limitation on the operation time changes by

the heat designs of the board.

■ Package Heat Resistance Value (Reference Value) (θja)

The following table is the package heat resistance value θja (reference value).

This value changes the condition of the board (size, layer number, and so on).

< 32-pin TQFP>

Board

θja

Ψjc

Ψjb

Condition

JEDEC 4layers^*1

（W/L/t＝76.2/114.5/1.6（mm））

Air cooling condition: No wind

(0m/s)

31.58[^OC/W] 0.57[^OC/W] 11.64[^OC/W]

JEDEC 2layers^*2

（W/L/t＝76.2/114.5/1.6（mm））

37.77[^OC/W] 0.61[^OC/W] 12.43[^OC/W] the soldering area ratio^*3：100%

< 32-pin WQFN>

Board

θja

Ψjc

Ψjb

Condition

JEDEC 4layers^*1

（W/L/t＝76.2/114.5/1.6（mm））

JEDEC 2layers^*2

（W/L/t＝76.2/114.5/1.6（mm））

Air cooling condition: No wind

(0m/s)

34.30[^OC/W] 0.21[^OC/W]

45.17[^OC/W] 0.21[^OC/W]

9.28[^OC/W]

9.72[^OC/W]

the soldering area ratio^*3：100%

*1 : The wiring density : 1st layer(Top) 60% / 2nd layer 100% / 3rd layer 100% / 4th layer(Bottom) 60%.

*2 : The wiring density : 1st layer(Top) 60% / 2nd layer(Bottom) 100%.

*3 : The soldering area ratio is the ratio that the heat sink area of this LSI and a land pattern on the board are soldered. 100%

mean that the heat sink area of this LSI is completely soldered to the land pattern on the board. About the land pattern on the

board, be sure to refer to the next clause (Package Dimensions).

Ta

Tc

The definition of each temperature is shown below.

Tj

Tb

Mounting board

Take measures to dissipate heat on the mounting board so that the maximum junction temperature does not exceed 85 ^OC.

1mm

108/123

FEDL22Q62X-06

ML22Q62X

■ Package Dimensions

● ML22Q62X-NNNTB / ML22Q62X-xxxTB

Notes for heat sink type Package

This LSI adopts a heat sink type package to raise a radiation of heat characteristic. Be sure to design the land pattern corresponding

to the heat sink area of the LSI on a board, and solder each other. The heat sink area of the LSI solder open or GND on the board.

109/123

FEDL22Q62X-06

ML22Q62X

110/123

FEDL22Q62X-06

ML22Q62X

● ML22Q62X-NNNGD / ML22Q62X-xxxGD

Notes for heat sink type Package

This LSI adopts a heat sink type package to raise a radiation of heat characteristic. Be sure to design the land pattern corresponding

to the heat sink area of the LSI on a board, and solder each other. The heat sink area of the LSI solder open or GND on the board.

111/123

FEDL22Q62X-06

ML22Q62X

112/123

FEDL22Q62X-06

ML22Q62X

■ Differences from Existing Speech Synthesis LSIs (ML2282X)

Parameter

MCU command interface

ML2282X

ML22Q62X

←

Clock synchronous serial

4.096MHz

(Built-in crystal oscillation

circuit)

4.096MHz

(Crystal oscillation circuit/built-in

RC oscillation)

Clock frequency

823：4Mbits(P2ROM)

824：8Mbits(P2ROM)

825：16Mbits(P2ROM)

623：4Mbits (flash memory)

624：8Mbits (flash memory)

625：16Mbits (flash memory)

626：32Mbits (flash memory)

Memory capacity

Built

Flash memory interface

MCU command interface (clock

synchronous serial)

Flash memory rewrite function

-

HQ-ADPCM

4bit ADPCM2

8-bit non-linear PCM

8bit straight PCM

16-bit straight PCM

6.4/12.8/25.6

4bit ADPCM2

8-bit non-linear PCM

8bit PCM

Speech synthesis

algorithm

16-bit PCM

6.4/12.8/25.6

4.0/8.0/16.0/32.0

5.3/10.7/21.3

8.0/16.0/32.0

10.7/21.3

11.025/22.05/44.1

12.0/24.0/48.0

Sampling frequency

(kHz)

12.0/24.0/48.0

2 channels

Sound function

Simultaneous

sounding function

(Mixing-function)

Maximum number of

phrases

4 channels

1024@1BANK

4096

BANK

4

-

Edit ROM function

Silence insertion

function

Yes

←

20ms to 1024ms

←

(4ms step)

Repeat function

Yes

←

Low-pass filter

D/A converter

FIR type interpolation filter

←

Voltage type 16-bit

Class AB 0.7W@8Ω

Class AB/D 1.0W@8Ω

Speaker amplifier

(SPV_DD=5V)

32 levels

50 levels

(SPV_DD=5V)

128 levels

16 levels

Yes

Volume

Adjustment

Function

Digital

Analog

Fade function

-

External analog input

Yes

←

Clock error detection

Thermal detection

Speaker pin ground

fault detection ^*1

-

Yes

Failure

detection

function

-

Yes

Speaker pin short

detection ^*1

Speaker disconnection

detection

DV_DD=2.7 to 5.5V

SPV_DD≥DV_DD

IOV_DD=2.7V to 5.5V

-40 to 70^OC

32-pin TQFP

32-pin WQFN

DV_DD=SPV_DD=4.5～5.5V

DV_DD=SPV_DD=2.7～3.6V

Power-supply voltage

Operating temperature

Package

-40 to 85^OC

30-pin SSOP

*1 The ground fault detection and short-circuit detection functions can be used when the SPV_DDis 4.5V or higher.

113/123

FEDL22Q62X-06

ML22Q62X

It becomes command-compatible with ML2282x/83x by using the following command setting.

Command name

PUP

Bit name

WCM

Bit value

0

AMODE

FADR

HPF

C1

0

PLAY

C1

0

START

STOP

MUON

SLOOP

CLOOP

CVOL

CH2/CH3

0/0

114/123

FEDL22Q62X-06

ML22Q62X

■ Speech LSI Utility Setting Items

Set the following items on the Speech LSI Utility.

Item

Description

Set any 8-bit data.

・0x69: Flash memory cannot be accessed by the

FDIRECT command.

・Other than 0x69: Accessing the flash memory is

enabled when the protection unlock data entered by the

FDIRECT command matches the data.

Protection code for flash memory

access

Select master clock (Source clock oscillation).

・RC (RC oscillation)

・Xtal (Crystal or ceramic resonator)

Master clock selection

Master clock frequency

Set the master clock frequency to F_OSC

.

・4.096 : 4.096MHz setting

・4.000 : 4.000MHz setting

Select the number of phrases from the following.

・4096

・3072

・2048

・1024

Number of phrases used

Set any 8-bit data.

Read by RDVER command.

Sound ROM information

Output format selection.

Class D amplifier output format

・Half-wave mode

Full wave mode is not supported.

Select the processing to be performed when an overflow

occurs.

・Hold current state

・Transition to the state after PUP command input

WDT counter, RST counter

WDTERR or RSTERR

processing at overflow

Select the overflow time from the following.

・125ms

・500ms

・2s

WDT counter, RST counter

WDTERR or RSTERR

overflow time

・4s

Refer to the Speech LSI Utility User's Manual for more information.

115/123

FEDL22Q62X-06

ML22Q62X

■ Check lists

This check list has notes to frequently overlooked or misunderstood hardware features of the LSI. Check each note listed up

chapter by chapter while coding the program or evaluating it using the LSI.

■Feature

[ ] *1 Handle V_DDRpin in two different ways depending on the voltage range 2.7-3.6V or 3.3-5.5V. Refer to the

"Application Circuit".

[ ] *2 The operating time of the speaker amplifier may be limited depending on the average ambient temperature (Ta)

used.

■Pin Description

[ ] (TEST1 pin) Leave open.

[ ] (IRON pin) Set this bit to "L" during playback operation using flash memory.

[ ] (IRON pin) Set this bit to "H" for onboard rewriting.

[ ] (IOV_DDpin) Connect to DV_DDpin even when not using flash memory interface.

[ ] (IOV_DDpin) Connect a bypass capacitor between this pin and the DGND pin.

[ ] (V_DDRpin) Connect a capacitor between this pin and DGND pin as close as possible.

[ ] (V_DDRpin) Connect this pin to the DV_DDpin when DV_DD= 2.7 to 3.6V.

[ ] (XTB pin) When using a resonator, connect it as close as possible.

[ ] (XTB pin) Leave it open when not in use.

[ ] (XT pin) To use an external clock, input from this pin. Delete the capacitor when a crystal or ceramic resonator is

connected.

[ ] (XT pin) When using a resonator, connect it as close as possible.

[ ] (XT pin) Leave it open when not in use.

[ ] (DV_DDpin) Connect a bypass capacitor between this pin and the DGND pin.

[ ] (V_DDLpin) Connect a capacitor between this pin and DGND pin as close as possible.

[ ] (SG pin) Connect a capacitor between this pin and SPGND pin.

[ ] (SPV_DDpin) Connect a bypass capacitor between this pin and the SPGND pin.

[ ] (RESETB pin) At power-on, input an "L" level to this pin. After the power supply voltage stabilizes, set this pin to an

"H" level.

[ ] (TEST0 pin) Fix to the DGND.

[ ] (CBUSYB pin) Be sure to input a command with this pin at an "H" level.

[ ] (N.C. pin) Unused pin. Leave open.

■Termination of Unused Pins

[ ] Confirm the recommended termination of unused pins in this chapter.

■Electrical characteristics

●Recommended operating conditions

[ ] *1 Be sure to SPV_DD>=DV_DD

.

116/123

FEDL22Q62X-06

ML22Q62X

■Function description

●Mixing function

◆ Waveform clamp precautions for mixing

[ ] If the clamp is known to be generated in advance, adjust the volume of each channel by CVOL command.

◆ Class D amplifier precaution on mixing

[ ] Short detection of SPP pin and SPM pin always operates while using the class D amplifier. If the volume of CVOL

command is adjusted incorrectly and it it is played back in the clamped state, the short detection circuit is determaine

that a short has occurred.When using class D amplifier, enable short detection of SPP pin and SPM pin by SAFE

command and check the short detection error (SPDERR).

◆ Different sampling frequency mixing algorithm

[ ] It is not possible to perform channel mixing by a different sampling frequency group.Note that when channel synthesis

is performed on a sampling frequency group other than the selected sampling frequency group, playback will be faster

or slower.

●Misoperation detection and failure detection functions

◆ SPP pin and SPM pin short detection

[ ] After inputting SAFE command, start the analog power-up operation by AMODE command within 10ms.

◆ Flash memory error detection

[ ] If the error bit (ROMERR) is set to "1" after the PUP command and before the PLAY command or START command

starts playback, this LSI may have error at the time of start. In such cases, initialize this LSI by moving the LSI to the

power-down mode by resetting the LSI by the RESETB pin or by using PDWN command.

◆ Detects the stop of clock input from a crystal resonator or ceramic resonator

[ ] If the RDERR command (first byte) is inputted before the crystal or ceramic resonator stops and switches to RC

oscillation (about 500μs), the CBUSYB pin will remain "L". Therefore, read the command after the CBUSYB pin

becomes "H".

[ ] When the crystal resonator or the ceramic resonator stops and switches to RC oscillation, playback may become

abnormal. Therefore, after confirming that the error bit (OSCERR) is "1", enter STOP command to stop playback.

■Timing chart

●Power-on timing

[ ] Start up in the order of DV_DD, SPV_DDand IOV_DDor DV_DD, IOV_DDand SPV_DD

.

[ ] Be sure to input "L" to the RESETB pin before inputting the first command after power-on.

[ ] Be sure to enter "L" at the RESETB pin when the DV_DDis below the (recommended) operating voltage range.

●Power-off timing

[ ] Shut down in the order of IOV_DD, SPV_DD, and DV_DDor SPV_DD, IOV_DD, and DV_DD

.

[ ] Shut down each power supply after changing to the power down status with PDWN commands.

●Change volume timing by AVOL command

[ ] Speaker amplifier volume setting by AVOL commands is valid only when Class AB speaker amplifier is used.

When a Class D speaker amplifier is used, the setting value is ignored and +0.0dB is selected.

●Continuous playback timing by PLAY command

[ ] When making continuous playbacks, input the PLAY command for the next phrases within the specified time period

(tcm) after the NCR of the corresponding channel changes to "H" level.

[ ] When the playback is not continuous, input the PLAY command for the next phrases after confirming the playback is

completed by RDSTAT command, etc.

●Continuous playback timing by START command

[ ] When making continuous playbacks, send the START command for the next phrases within the specified time period

(tcm) after the NCR of the corresponding channel changes to "H" level.

[ ] When the playback is not continuous, input the START command for the next phrases after confirming the playback is

completed by RDSTAT command, etc.

117/123

FEDL22Q62X-06

ML22Q62X

●Continuous playback timing by MUON command

[ ] When making continuous playbacks, input the MUON/PLAY/START command for the next phrases within 10ms

(tcm) after the NCR of the corresponding channel changes to "H" level.When the playback is not continuous, input

the MUON/PLAY/START command for the next phrases after confirming the playback is completed by RDSTAT

command, etc.

●Repeat playback setting/release timing by SLOOP/CLOOP command

[ ] The SLOOP command is valid only during playback. After the PLAY command is input, input the SLOOP command

within the specified period (tcm) after the NCR of the corresponding channel becomes "H" level.

■Command

●Command list

[ ] Do not enter command that is not described in this manual. Enter the command with the CBUSYB "H".

●Description of Command Functions

◆ AMODE command

[ ] To perform power-down under a setting condition that differs from the power-up condition of the analog unit, set the

AMODE command to set the power-down condition again.

[ ] To power up the analog part, set the CVOL command to 00h (initial value) and then enter the AMODE command.

[ ] When using analog mixing from the AIN pin, set DAMP = "0" (Class AB amplifier is used).

[ ] Input the sound signals to the AIN pin after CBUSYB pin becomes "H" by the AMODE command.

[ ] When using a Class D amplifier with speaker amplifier outputs, set it to the power-up state (AEN1/AEN0= "01") or the

power-down state (AEN1/AEN0= "00"). If DAMP = "1" is selected, do not set AEN1= "1".

◆ AVOL command

[ ] AV5-AV2=1h and 2h are prohibited.

◆ FDIRECT command

[ ] The FDIRECT command controls accesses to the flash memory using the clock-synchronous serial interface.Input the

command after inputting the PUP command.

[ ] To cancel the flash memory access mode, insert a reset (RESETB = "L") and conduct initialization or turn off the

power supply.

◆ START command

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3). Do not input it to "0" (all “0”) with

specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

◆ STOP command

[ ] The STOP command can be input regardless of the status of the NCR during playback operation. However, following

the elapse of CBUSYB "L" level output time 3 (tCB3), input the next command after confirming that the BUSYB

signal becomes "H". If the BUSYB signal does not become "H", enter the STOP command again.

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3). Do not input it to "0" (all “0”) with

specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

◆ MUON command

[ ] Set the silence setting (M7-M0) to 04h or more (tmu>=20ms).

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3). Do not input it to "0" (all “0”) with

specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

◆ SLOOP command

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3). Do not input it to "0" (all “0”) with

specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

◆ CLOOP command

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3).Do not input it to "0" (all “0”) with

specifying nothing. If it is input with specifying nothing (all "0"), the command is ignored.

◆ CVOL command

[ ] Be sure to specify one of the channels for the channel setting (CH0-CH3). When multiple channels are specified, the

volume of the specified channels is set. Do not input it to "0" (all “0”) with specifying nothing. If it is input with

specifying nothing (all "0"), the command is ignored.

◆ RDSTAT commnad

[ ] When reading the status of the second byte after command input, set the SI pin to "L".

118/123

FEDL22Q62X-06

ML22Q62X

◆ RDVER command

[ ] When reading the status of the second byte after command input, set the SI pin to "L".

◆ RDERR command

[ ] When reading the status of the second byte after command input, set the SI pin to "L".

[ ] If the outputs of misoperation detection and failure detection are selected by OUTSTAT command, and the read data is

all "L" even though STATUS1 or STATUS2 pin is "H", the read data cannot be read normally. Be sure to read it

again.

◆ SAFE command

[ ] The initial value is the operation stop state ("0"). When this bit is set to "1", operation starts.

[ ] *1 Do not set WDTEN and RSTEN to "1" at the same time. If these bits are set to "1" at the same time, only the RSTEN

bit is set to "1".

■Peripheral circuit

●Handling of SG Pin／●Handling of V_DDLPin／●Handling of V_DDRPin／●Power wiring／●Bypass capacitor／●Coupling

capacitor

[ ] Confirm the recommended values and precautions in this chapter.

■Package Dimensions

[ ] Confirm “Notes for heat sink type Package” and “Notes for Mounting the Surface Mount Type Package” in this

chapter.

■Speech LSI Utility Setting Items

[ ] Confirm setting items of “Speech LSI Utility” in this chapter.

119/123

FEDL22Q62X-06

ML22Q62X

■ Revision history

Page

Document No.

Date

Description

Current

edition

FEDL22Q62X-01

FEDL22Q62X-02

Apr 24, 2020

Jul 17, 2020

―

Formal 1st edition.

Added "DV_DD，SPV_DDand IOV_DDcan be set independently.

(SPV_DD≥DV_DD)" to the description of power-supply voltage.

2

Added "*3" to the standard value of I_DDOand I_DDSof DC

characteristics.

11

19

11

19

Added definition of compression rate.

―

23

86

Added class D amplifier precaution on mixing.

85

Changed description of command error detection.

(Not a change in product specifications.)

25

29

31

34

62

63

26

30

32

35

63

64

Changed description of watchdog timer overflow detection.

(Not a change in product specifications.)

Changed description of RST counter overflow detection.

(Not a change in product specifications.)

Added a method to return from flash memory access mode

to normal mode.

Changed description of DAMP bit of AMODE command.

(Not a change in product specifications.)

Changed description of POP bit of AMODE command.

(Not a change in product specifications.)

Changed description of table of AEN1, AEN0 and POP bit,

of AMODE command.

63

64

(Not a change in product specifications.)

Changed description of OSCEN bit of SAFE command.

(Not a change in product specifications.)

85

86

Separated Handling of V_DDLpin and V_DDRpin.

Added definithion of handling of V_DDRpin.

102

103

Added attention of voltage setting of SPV_DDand DV_DDfor

power wiring.

102

105

103

106

Added C11 to the coupling capacitor.

Changed notation of recommended ceramic resonator.

(Not a recommended product change.)

Added class D amplifier precaution on mixing in thecheck

lists.

―

114

11

FEDL22Q62X-03

Oct 1, 2020

Change current consumption I_DDOvalue during playback

operation

11

(Before change)

(After change)

Max 55mA

Typ 25mA,Max 45mA

When AMODE command is input CBUSYB "L" level output

time t_PUPA2value change

13

(Before change)

(After change)

min 72ms,typ 74ms,max 76ms

min 71ms,typ 73ms,max 75ms

120/123

FEDL22Q62X-06

ML22Q62X

Page

Document No.

Date

Description

Current

edition

FEDL22Q62X-03

Oct 1, 2020

When AMODE command is input CBUSYB "L" level output

time t_PUPA3value change

13

(Before change)

(After change)

min 32ms,typ 34ms,max 36ms

min 31ms,typ 33ms,max 35ms

When AMODE command is input CBUSYB "L" level output

time t_PDA1value change

13

(Before change)

(After change)

min 106ms,typ 108ms,max 110ms

min 100ms,typ 102ms,max 104ms

When AMODE command is input CBUSYB "L" level output

time t_PDA2value change

(Before change)

(After change)

min 143ms,typ 145ms,max 147ms

min 142ms,typ 144ms,max 146ms

When AMODE command is input CBUSYB "L" level output

time t_PDA3value change

(Before change)

(After change)

min 103ms,typ 105ms,max 107ms

min 102ms,typ 104ms,max 106ms

6

Added IRSO to the Termination of Unused Pins

Added LSB data hold time from SCK t_DOHto the AC

Characteristics (Clock Synchronous Serial Interface).

14

Changed Clock Synchronous Serial Interface timing wave

form.

17

40

17

40

Changed Clock Synchronous Serial Interface timing wave

form.

FEDL22Q62X-04

Jan 7, 2021

Changed description of power down timming with POP noise

noise suppression.

63

(Not a change in product specifications.)

104

105

104

105

Changed Application Circuit.

Added " 32-pin WQFN (5mm x 5mm, 0.5mm pitch)" to

Package

2

Added " ML22Q62X-NNNGD，ML22Q62X-xxxGD (32-pin

WQFN)" to Ordered Part Name

Added " ML22Q62X-NNNGD，ML22Q62X-xxxGD (32-pin

WQFN)" to Pin Configuration

-

4

9

Classification F I/O Equivalent Circuit change

8

(Before change)

(After change)

Input/Output

Output

FEDL22Q62X-05

Jan 14, 2022

Classification G I/O Equivalent Circuit change

8

9

(Before change)

(After change)

Input/Output

Input

Classification H I/O Equivalent Circuit change

(Before change)

(After change)

Input/Output

Outputt

121/123

FEDL22Q62X-06

ML22Q62X

Page

Document No.

Date

Description

Current

edition

Change the timing chart when the OSCEN bit of the SAFE

command continues to be "1"

(Before change)

stopped, the STATUSn pin and OSCERR maintain "L".

(After change) After ERRCL, when oscillation is

stopped, the STATUSn pin and OSCERR become "H".

105,106 Added explanation about capacitors for crystal oscillators

After ERRCL, when oscillation is

34

35

FEDL22Q62X-05

Jan 14, 2022

104,105

105

106

108

Corrected an error in MCU I/F.

107

32-pin WQFN added to package thermal resistance

Added "ML22Q62X-NNNGD / ML22Q62X-xxxGD" to

Package Dimensions

-

111,112

113

110

Added " 32-pin WQFN " to Package

IRSCK terminal processing has been changed.

(Before change)

(After change)

Open

GND

105,106

109

105,106 IRSO terminal processing has been changed.

(Before change)

(After change)

GND

FEDL22Q62X-06

Jun 29, 2022

Open

(Not a change in product specifications.)

Modified package dimensions from QSL-69517 to

QSL-69516.

109

122/123

FEDL22Q62X-06

ML22Q62X

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within

the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of

or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without

observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and

malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down or

malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.

You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology

or any third party with respect to LAPIS Technology Products or the information contained in this document (including but

not limited to, the Product data, drawings, charts, programs, algorithms, and application examples, etc.). Therefore LAPIS

Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out

of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications

requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and

must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic

lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc.

LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by using

the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability, such

as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws

or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export

Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS

Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www. lapis-tech.com /en/

123/123


型号：	ML22Q626
厂家：	ROHM
描述：	ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。语音合成放大器 PC 驱动控制器微控制器存储转换器
文件：	总123页 (文件大小：3592K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML22Q626 [ROHM]

相关型号：

ML22Q663

ML22Q664

ML22Q665

ML22Q666

ML2302

ML2302TB

ML2302TS

ML2308GP

ML2330

ML2330ES-2

ML2330ES-3

ML2330ES-5