ML22594_技术文档

Dear customer

LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1^stday of October,

2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which

LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS

Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.

Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"

and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."

Furthermore, there are no changes to the documents relating to our products other than

the company name, the company trademark, logo, etc.

Thank you for your understanding.

LAPIS Technology Co., Ltd.

October 1, 2020

FEDL22594-08

Issue Date: Apr. 17. 2020

ML22594-xxxMB

4-Channel Mixing Speech Synthesis LSI with Built-in MASK ROM for Automotive

GENERAL DESCRIPTION

The ML22594-xxx is 4-channel mixing speech synthesis LSIs with built-in MASK ROM for voice data. These

LSIs incorporate into them an HQ-ADPCM decoder that enables high sound quality, 16-bit D/A converter,

low-pass filter, 1.0 W monaural speaker amplifier for driving speakers , and over-current detectible function for

Speaker Pins. And the high quality and a long time sound regeneration is possible by using the voice

regeneration which the outside ROM was used for.

Since functions necessary for voice output are all integrated into a single chip, a system can be upgraded with

audio features by only using one of these LSIs.

• Capacity of internal memory and the maximum voice production time (when HQ-ADPCM^※¹method used)

Maximum voice production time (sec)

Product name

ROM capacity

f_sam= 8.0 kHz

243

f_sam= 16.0 kHz

121

f_sam= 32.0 kHz

6 Mbits(Internal)

60

ML22594- xxx

128 Mbits(Exteranal)

5240

2620

1310

FEATURES

• ROM capacity:

• Speech synthesis method:

Internal 6Mbits, External 128Mbits (Max)

Can be specified for each phrase.

HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM

Can be specified for each phrase.

• Sampling frequency:

12.0/24.0/48.0 kHz, 8.0/16.0/32.0 kHz, 6.4/12.8/25.6 kHz

• Built-in low-pass filter and 16-bit D/A converter

• Built-in speaker driver amplifier: 1.0 W, 8Ω (at DV_DD= 5 V)

(with over-current detectible function for Speaker pins)

• External analog voice input (built-in analog mixing function)

• CPU command interface:

• Maximum number of phrases:

• Edit ROM

Clock synchronous serial interface

1024 phrases, from 000h to 3FFh

• Volume control:

CVOL command: Adjustable through 32 levels (including OFF)

AVOL command: Adjustable through 50 levels (including OFF)

• Repeat function:

• Channeｌ mixing function:

LOOP command

4 channels

• Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the

OFF setting)

• Source oscillation frequency:

• Power supply voltage:

• Operating temperature range:

• Package:

4.096 MHz

4.5 to 5.5 V

2

–40°C to +105°C^※

heat sink type 30-pin plastic SSOP(P-SSOP30-56-0.65-Z6K6)

•Product name:

ML22594-xxxMB (“xxx” denotes ROM code number)

HQ-ADPCM is a high sound quality audio compression technology of "Ky's".

“Ｋｙ’ｓ” is a Registered trademark of National Universities corporate Kyushu

Institute of Technology

※1

The limitation on the operation time changes by the using condition.

(Refer to "LIMITATION ON THE OPERATION TIME (PLAY-BACK TIME)")

※2

1/77

FEDL22594-08

ML22594-XXX

The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225XG and

ML22Q573) and the ML22594.

Item

CPU interface

ROM type

ROM capacity

External ROM

interface

ML22Q573

Serial

FLASH

4 Mbits

ML2257X

Serial

MASK

ML22Q553

←

FLASH

4 Mbits

ML22594

←

MASK

6 Mbits

2/4 Mbits

No

←

Serial

HQ-ADPCM

8-bit straight PCM

8-bit non-linear PCM

16-bit straight PCM

Playback method

←

1024

(Internal512 /

External512)

Maximum number of

phrases

1024

←

6.4/8.0/12.0/

12.8/16.0/24.0/

25.6/32.0/48.0

4.096 MHz (has a

crystal oscillator

circuit built-in)

16-bit voltage-type

FIR interpolation

filter

Sampling frequency

(kHz)

←

Clock frequency

D/A converter

←

Low-pass filter

←

(High-pass

interpolation)

Built-in

1.0 W

(8Ω, DV_DD= 5 V)

Speaker driving

amplifier

←

Yes

←

Over-current

detectible function

for Speaker Pins

Simultaneous sound

production function

(mixing function)

Edit ROM

No

4-channel

Yes

32 levels

20 to 1024 ms

(4 ms steps)

Yes

←

Volume control

Silence insertion

←

Repeat function

External analog

input

External speech

data input

Interval at which a

seam is silent during

continuous playback

(*1)

Power supply

voltage

Yes

No

←

No

2.7 V to 5.5 V

4.5 V to 5.5 V

Ambient

temperature

Package

-40゜C to 105゜C

←

30-pin SSOP

FEDL22594-08

ML22594-XXX

*1: Continuous playback as shown below is possible.

(Playback method: 8-bit straight PCM, 8-bit non-linear PCM, 16-bit straight PCM)

1 phrase

No silence interval

3/77

FEDL22594-08

ML22594-XXX

BLOCK DIAGRAM

The block diagrams of the ML22594-xxx are shown below.

Serial ROM Interface

DV_DD

DGND

V_DDL

Address Controller

Cmd Analyzer

6Mbits MASKROM

PCM Synthesizer

LPF(CVOL)

RESETB

CSB

Timing

Controller

SCK

SI

I/O

SO

16bit DAC

Interface

PLL

CBUSYB

STATUS

ERR

SP-AMP

(AVOL)

OSC

DIPH

SPV_DD

SPGND

XT XTB

SPM SPP

AIN SG

Block Diagram of ML22594-xxx

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PIN CONFIGURATION (TOP VIEW)

● ML22594-xxx

1

2

3

30 SPV_DD

29 SPGND

28 SPP

AIN

SG

NC

4

5

6

27 SPM

26 ESI

25 ESO

DV_DD

DGND

V_DDL

7

8

9

10

11

12

13

14

15

24 ESCK

23 ECSB

22 TESTI1

21 FLW

20 RESETB

19 IOVDD

18 DV_DD

17 XT

DIPH

STATUS

ERR

CSB

SCK

SI

SO

CBUSYB

DGND

16 XTB

NC：Unused pin

30-Pin Plastic SSOP

5/77

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ML22594-XXX

PIN DESCRIPTION (1)

Initial

Symbol

AIN

Attribute

value

1

I/O

I

Description

Attribute

analog

(*1)

—

0

Speaker amplifier input pin.

Built-in speaker amplifier’s reference voltage output pin.

Connect a capacitor of 0.1 µF or more between this pin and analog

2

SG

O

DGND.

3

NC

—

NC(Unused) pin

analog

0

Digital power supply pin.

4,18

5,15

6

DV_DD

DGND

V_DDL

—

O

—

Connect a bypass capacitor of 10µF or more between this power

pin and DGND.

—

0

gnd

Digital ground pin

2.5 V regulator output pin.

Acts as an internal power supply (for logic). Connect a power

capacitor of 10 µF or more between this pin and DGND.

Serial interface switching pin.

Pin for choosing between rising edges and falling edges as

to the edges of the SCK pulses used for shifting serial data

input to the SI pin into the inside of the LSI.

When this pin is at a “L” level, SI input data is shifted into the

LSI on the rising edges of the SCK clock pulses and a status

signal is output from the SO pin on the falling edges of the

7

DIPH

I

Positive

digital

0

SCK clock pulses.

When this pin is at a “H” level, SI input data is shifted into the

LSI on the falling edges of the SCK clock pulses and a status

signal is output from the SO pin on the rising edges of the

SCK clock pulses.

Channel status output pin.

8

9

STATUS

ERR

O

Positive

digital

1

0

Outputs the BUSYB or NCR signal for each channel by

inputting the OUTSTAT command.

Error output pin.

Outputs a “H” level if an error occurs.

Chip select pin.

A “L” level on this pin accepts the SCK or SI inputs. When

this pin is at a “H” level, neither the SCK nor SI signal is input

to the LSI.

10

11

CSB

SCK

I

Negative

Positive

digital

clk

1

0

Synchronous serial clock input pin.

Synchronous serial data input pin.

When the DIPH pin is at a “L” level, data is shifted in on the

rising edges of the SCK clock pulses.

12

SI

I

—

digital

0

When the DIPH pin is at a “H” level, data is shifted in on the

falling edges of the SCK clock pulses.

Channel status serial output pin.

Outputs a status signal on the falling edges of the SCK clock

pulses when the DIPH pin is at a ”L” level; outputs a status

signal on the rising edges of the SCK clock pulses when the

DIPH pin is at a ”H” level.

13

SO

O

Positive

digital

Hi-Z

When the CSB pin is at a ”L” level, the status of each channel

is output serially in sync with the SCK clock. When the CSB

pin is at a ”H” level, this pin goes into a high impedance state.

6/77

FEDL22594-08

ML22594-XXX

PIN DESCRIPTION (2)

Initial

Attribute

Symbol I/O Attribute

Description

value^(*1)

Command processing status signal output pin.

This pin outputs a “L” level during command processing.

Be sure to enter commands with the CBUSYB pin driven

at a “H” level.

Connects to a crystal or a ceramic resonator.

When using an external clock, leave this pin open.

If a crystal or a ceramic resonator is used, connect it as

close to the LSI as possible.

Connects to a crystal or a ceramic resonator.

A feedback resistor of around 1 MΩ is built in between this

XT pin and the XTB pin. When using an external clock,

input the clock from this pin.

If a crystal or a ceramic resonator is used, connect it as

close to the LSI as possible.

(*2)

14 CBUSYB

O

Negative

digital

16

17

XTB

XT

clk

1

0

I

Positive

External ROM interface power supply pin.

Use the power supply which is the same as the external

ROM.

19

IO_VDD

—

analog

0

Connect a bypass capacitor of 0.1µF or more between

this pin and DGND.

Reset input pin.

At “L” level input, the LSI enters the initial state. After a

reset input, the entire circuit is stopped and enters a

power down state. Upon power-on, input a “L” level to

this pin. After the power supply voltage is stabilized,

drive this pin at a “H” level.

20 RESETB

I

Negative

Positive

digital

0

This pin has a pull-up resistor built in.

External ROM interface disenable pin.

When a “H” level is inputted, the external ROM interface is

disenable. “L” level is inputted, the external ROM interface

is enable. Has a pull-down resistor built in.

Used as either an input pin for testing or a reset input pin

for Flash rewriting. Has a pull-down resistor built in.

21

FLW

22

23

TESTI1

ECSB

I

Negative

digital

0

1

External ROM interface chip select pin.

A “L” level is external ROM access.

O

External ROM interface serial clock output pin.

External ROM interface serial data output pin.

24

25

ESCK

ESO

O

Positive

digital

1

External ROM interface serial data input pin.

Has a pull-down resistor built in.

26

27

ESI

I

Positive

—

digital

0

SPM

O

Output pin of the built-in speaker amplifier.

analog

Hi-Z

28

29

30

SPP

O

—

Can be configured as an AOUT amplifier output by analog

command setting.

0

SPGND

SPV_DD

gnd

—

Speaker amplifier ground pin.

Speaker amplifier power supply pin.

Connect a bypass capacitor of 10µF or more between this power

pin and SPGND.

*1: Indicates the initial value at reset input or during power down.

*2: When ML22594 is reset, this pin is "L" level, when ML22594 is power-down, this pin is "H" level.

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ML22594-XXX

ABSOLUTE MAXIMUM RATINGS

DGND = SPGND = 0 V, Ta = 25°C

Parameter

Power supply voltage

Input voltage

Symbol

DV_DD

SPV_DD

Condition

Rating

Unit

—

−0.3 to +7.0

V

V_IN

P_D

—

−0.3 to DV_DD+0.3

V

When the LSI is mounted on

JEDEC 4-layer board.

When SPV_DD= 5V

1000

mW

Power dissipation

Applies to all pins except

SPM, SPP, V_DDL,and V_DDR

10

mA

.

I_OS

Output short-circuit current

Storage temperature

Applies to SPM and SPP pins.

Applies to V_DDLand V_DDRpins.

—

500

50

−55 to +150

mA

°C

T_STG

RECOMMENDED OPERATING CONDITIONS

DGND = SPGND = 0 V

Parameter

DV_DD, SPV_DD

Power supply voltage

Symbol

Condition

—

Range

Unit

DV_DD

SPV_DD

4.5 to 5.5

V

IO_VDD

Power supply voltage

IO_VDD

—

2.7 to 5.5 ^*1

V

Operating temperature

Top

f_OSC

—

−40 to +105

Typ.

°C

Min.

3.5

Max.

4.5

Master clock frequency

MHz

4.096

*1 : When External ROM interface does not be used, IO_VDDcan be set in 0V.

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ML22594-XXX

ELECTRICAL CHARACTERISTICS

DC Characteristics

DV_DD= SPV_DD= 4.5 to 5.5 V, IOV_DD= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C

Parameter

Symbol

V_IH1

V_IH2

V_IL1

V_IL2

V_OH1

V_OH2

V_OH3

V_OL1

V_OL2

V_OL3

I_OOH

Condition

Min.

0.8×DV_DD

0.8×IOV_DD

Typ.

—

Max.

DV_DD

IOV_DD

0.2×DV_DD

0.2×IOV_DD

—

Unit

V

“H” input voltage1(*1)

“H” input voltage2(*2)

“L” input voltage1(*1)

“L” input voltage2(*2)

“H” output voltage 1 (*3)

“H” output voltage 2 (*4)

“H” output voltage 3 (*5)

“L” output voltage 1 (*3)

“L” output voltage 2 (*4)

“L” output voltage 3 (*5)

—

0

—

0

DV_DD−0.4

IOV_DD−0.4

—

I_OH= −1 mA

I_OH= −50 µA

I_OH= −1 mA

I_OL= 2 mA

I_OL= 50 µA

I_OL= 2 mA

VOH = DV_DD(CSB=“H”)

—

0.4

—

V

0.4

—

10

µA

Output leakage current1

(*6)

I_OOL

I_OOH

VOL = DGND (CSB=“H”)

VOH = IOV_DD(FLW=“H”)

VOL = DGND (FLW=“H”)

−10

—

µA

—

10

Output leakage current2

(*7)

I_OOL

I_IH1

I_IH2

I_IH3

I_IH4

I_IL1

I_IL2

I_IL3

−10

—

0.8

20

—

5.0

100

—

−5.0

–100

—

10

20

400

—

−0.8

–20

µA

“H” input current 1 (*8)

“H” input current 2 (*9)

“H” input current 3 (*10)

“H” input current 4 (*11)

“L” input current 1 (*12)

“L” input current 2 (*9)

“L” input current 3 (*13)

V_IH= DV_DD

V_IH= IOV_DD

V_IL= DGND

2

–10

–20

–400

V_IL= DGND

f_OSC= 4.096 MHz

fs=48kHz, f=1kHz,

When 16bitPCM Playback

No output load

—

54(*15)

1(*16)

Supply current during

playback 1

I_DD1

mA

f_OSC= 4.096 MHz

fs=48kHz, f=1kHz,

When 16bitPCM Playback

using External ROM

No output load

f_OSC= 4.096 MHz

During silence playback

No output load

—

50(*15)

5(*16)

Supply current during

playback 2 (*14)

I_DD2

mA

—

47(*15)

1(*16)

Supply current during

playback 3

I_DD3

Ta = −40 to +55°C

Ta = −40 to +105°C

—

10(*17)

20(*17)

µA

Power-down supply

current

I_DDS1

(*1) Applies to the DIPH, CSB, SCK, SI, RESETB, TESTI1 and XT pins.

(*2) Applies to the FLW, ESI pins.

(*3) Applies to the STATUS, ERR, SO and CBUSYB pins.

(*4) Applies to the XTB pin.

(*10) Applies to the TESTI1 pin.

(*11) Applies to the FLW and ESI pins. (Typ. Is 5.0V condition)

(*12) Applies to the DIPH, CSB, SCK, SI, TESTI1, FLW and ESI pins.

(*13) Applies to the RESETB pin.

(*5) Applies to the ECSB, ESCK and ESO pins.

(*6) Applies to the SO pin.

(*7) Applies to the ECSB, ESCK and ESO pins

(*8) Applies to the DIPH, CSB, SCK, SI and RESETB pins.

(*9) Applies to the XT pin.

(*14) ECSB, ESCK and ESO pins load capacitance = 45pF(max)

(*15) Supply current which added DV_DDand SPV_DD

(*16) Supply current which applies IOV_DD

(*17) Supply current which added DV_DD, SPV_DDand IOV_DD.

.

9/77

FEDL22594-08

ML22594-XXX

Analog Section Characteristics

DVDD = SPVDD = 4.5 to 5.5 V, IOVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

AIN input resistance

R_AIN

Input gain: 0 dB

10

20

30

kΩ

SPV_DD

×

AIN input voltage range

V_AIN

R_LA

—

10

—

Vp-p

Ω

2/3

Line output resistance

LINE output load

resistance

At 1/2SPV_DDoutput

100

At SPGND10kΩ load

—

kΩ

LINE output voltage range

SPV_DD

×

At SPGND10kΩ load

V_AO

SPV_DD/6

—

V

5/6

SG output voltage

0.95x

SPV_DD/2

57

1.05x

SPV_DD/2

135

V_SG

R_SG

R_LSP

—

SPV_DD/2

V

kΩ

Ω

SG output resistance

—

96

8

SPM, SPP output load

resistance

Speaker amplifier output

power

6

—

SPV_DD= 5.0V, f = 1 kHz

R_SPO= 8Ω, THD≦ 10%

P_SPO

800

1000

—

mW

mV

V

Output offset voltage

between SPM and SPP

with no signal present

Regulator output voltage

SPIN–SPM gain = 0 dB

V_OF

−50

+50

With a load of 8Ω

V_DDL

V_DDR

Output load current =

2.25

2.5

2.75

−35 mA

10/77

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ML22594-XXX

AC Characteristics (1)

DV_DD= SPV_DD= 4.5 to 5.5 V, IOV_DD= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C

Parameter

Symbol

f_duty

Condition

—

Min.

40

10

—

Typ.

50

—

Max.

60

Unit

%

Master clock duty cycle

RESETB input pulse width

Reset noise rejection pulse width

Noise rejection pulse width

t_RST

—

µs

ns

t_NRST

t_NINP

RESETB pin

—

0.1

5

CSB, SCK, and SI pins

f_OSC= 4.096 MHz

At STOP/SLOOP/CLOOP/

VOL command input

After status read

f_OSC= 4.096 MHz

After input first command at

two-time command input

mode

—

Command input interval time1

t_INT

10

0

—

µs

Command input interval time2

Command input enable time

t_INTC

f_OSC= 4.096 MHz

During continuous playback

At SLOOP input

4.096 MHz

t_cm

—

10

4

ms

At PUP command input

CBUSYB “L” level output time

t_PUP

At external clock input

4.096 MHz

At external clock input

POP = “0”

DAEN = “0”→”1”

or SPEN = “0”→”1”

4.096 MHz

At AMODE command input

CBUSYB “L” level output time（*3）

t_PUPA1

39

72

41

74

43

76

ms

At external clock input

POP = “1”

At AMODE command input

CBUSYB “L” level output time

t_PUPA2

DAEN = “0”→”1”

(SPEN = “0”)

4.096 MHz

At external clock input

POP = “0”

At AMODE command input

CBUSYB “L” level output time

t_PUPA3

32

—

34

—

36

10

ms

µs

DAEN = “0”→”1”

(SPEN = “0”)

At PDWN command input

CBUSYB “L” level output time

t_PD

f_OSC= 4.096 MHz

4.096 MHz

At external clock input

POP = “0”

DAEN = “1”→”0”

or SPEN = “1”→”0”

4.096 MHz

At AMODE command input

CBUSYB “L” level output time（*3）

t_PDA1

106

108

110

ms

At external clock input

POP = “1”

At AMODE command input

CBUSYB “L” level output time

t_PDA2

143

103

145

105

147

107

ms

DAEN = “1”→”0”

(SPEN = “0”)

4.096 MHz

At external clock input

POP = “0”

At AMODE command input

CBUSYB “L” level output time

t_PDA3

DAEN = “1”→”0”

(SPEN = “0”)

11/77

FEDL22594-08

ML22594-XXX

CBUSYB “L” level output time 1 (*1)

CBUSYB “L” level output time 2 (*2)

CBUSYB “L” level output time 3 (*4)

t_CB1

t_CB2

t_CB3

f_OSC= 4.096 MHz

—

10

3

µs

ms

µs

200

Note: Output pin load capacitance = 45 pF (Max.)

*1: Applies to cases where a command is input, except after the PUP, PDWN, PLAY, START or AMODE

command input.

*2: Applies to cases where the PLAY or START command is input.

*3: When FAD3-0 is initial value (8h)

*4: Applies to cases where the STOP command is input

12/77

FEDL22594-08

ML22594-XXX

AC Characteristics (2) CPU serial interface

DV_DD= SPV_DD= 4.5 to 5.5 V, IOV_DD= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C

Parameter

SCK input enable time from CSB fall

SCK hold time from CSB rise

Symbol

t_ESCK

t_CSH

Condition

—

Min.

100

—

Typ.

—

Max.

—

Unit

ns

—

Data floating time from CSB rise

Data setup time from SCK rise

t_DOZ

RL = 3 kΩ

DIPH = “L”

DIPH = “H”

—

100

—

t_DIS1

50

Data hold time from SCK rise

t_DIH1

50

—

Data output delay time from SCK fall

Data setup time from SCK fall

t_DOD1

t_DIS2

—

90

—

50

Data hold time from SCK fall

t_DIH2

50

—

Data output delay time from SCK rise

SCK “H” level pulse width

t_DOD2

t_SCKH

t_SCKL

t_DBSY1

t_DBSY2

—

90

—

100

—

SCK “L” level pulse width

—

CBUSYB output delay time from SCK rise

CBUSYB output delay time from SCK fall

Note: Output pin load capacitance = 45 pF (Max.)

DIPH = “L”

DIPH = “H”

90

—

AC Characteristics (3) External ROM serial interface

DV_DD= SPV_DD= 4.5 to 5.5 V, IOV_DD= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C

Parameter

Symbol

Condition

Min.

50

10

—

Typ.

—

Max.

—

Unit

ns

ESCK input enable time from ECSB fall edge

ESCK input hold time from ECSB rise edge

Data setup time from ESCK rise edge

Data hold time from ESCK rise edge

Data output delay time from ESCK rise edge

ESCK clock frequency

t_ECSSf_OSC= 4.096 MHz

t_ECSHf_OSC= 4.096 MHz

—

ns

t_EDIS

t_EDIH

f_OSC= 4.096 MHz

—

ns

—

ns

t_EDODf_OSC= 4.096 MHz

—

5

ns

t_ESCKFf_OSC= 4.096 MHz 16.0 16.384 16.5

MHz

ns

ESCK “H” level pulse width

t_ESCKHf_OSC= 4.096 MHz

t_ESCKLf_OSC= 4.096 MHz

26

—

1

ESCK “L” level pulse width

ns

Data output delay time from FLW rise edge.

Data output delay time from FLW fall edge.

Note: Output pin load capacitance = 45 pF (Max.)

t_EFLH

t_EFHL

—

ms

1

13/77

FEDL22594-08

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TIMING DIAGRAMS

CPU Serial Interface Data Timing (When DIPH = “L”)

VIH

CSB

VIL

t_CSH

t_ESCK

t_SCKH

VIH

VIL

SCK

t_DIS1

t_DIH1

t_SCKL

VIH

VIL

SI

t_DOD1

t_DOZ

VIH

VIL

SO

t_DBSY1

CBUSYB ^VOH

VOL

CPU Serial Interface Data Timing (When DIPH = “H”)

VIH

CSB

VIL

t_CSH

t_ESCK

t_SCKL

VIH

VIL

SCK

t_DIS2

t_DIH2

t_SCKH

VIH

VIL

SI

t_DOZ

VIH

VIL

SO

t_DBSY2

CBUSYB ^VOH

VOL

External ROM Serial Interface Data Timing

VOH

ECSB

VOL

t_ESCKF

t_ESCKH

t_ECSH

t_ECSS

VOH

ESCK

VOL

t_EDISt_EDIH

t_ESCKL

VIH

ESI

VIL

t_EDOD

VOH

ESO

VOL

14/77

FEDL22594-08

ML22594-XXX

Power-On Timing

5V

90%

SPV_DD

DV_DD

3.3V

IOV_DD

t_RST

VIH

VIL

RESETB

Status

10%

Power down

Oscillation is stopped after power-on.

Be sure to power-on IOVDD after DVDD/SPVDD.

When IOVDD isn't used, it is possible that it is fixed in 0V.

Be sure to set “L”level the RESETB pin before the first command input.

Power Shut-down Timing

5V

SPV_DD

DV_DD

3.3V

IOV_DD

Power down

Status

Be sure to power shut-down DVDD/SPVDD after IOVDD.

When IOVDD isn't used, it is possible that it is fixed in 0V.

15/77

FEDL22594-08

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Reset Input Timing

RESETB

t_RST

Oscillating

Oscillation stopped

XTXTB

V

_DDLSG

GND

SPM

Hi-Z

GND

SPP

Playing

Power down

Status

Note: The same timing applies in cases where the Reset signal is input during waiting for command.

16/77

FEDL22594-08

ML22594-XXX

Power-Up Timing

CSB

SCK

SI

t_PUP

CBUSYB ^VOH

VOL

VOH

NCRn

(internal)

VOL

VOH

BUSYBn

(internal)

VOL

Oscillation stopped

Power down

Oscillating

XTXTB

Performing reset

Oscillation stabilized

Awaiting command

Status

processing

Power-Down Timing

CSB

SCK

SI

t_PD

CBUSYB^VOH

VOL

VOH

NCRn

(internal)^VOL

BUSYBn^VOH

(internal) ^VOL

Oscillation

stopped

Oscillating

XTXTB

Command is being

processed

Awaiting command

Power down

Status

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ML22594-XXX

Playback Start Timing by the PLAY Command

PLAY command

1^stbyte

PLAY command

2^ndbyte

CSB

SCK

SI

t_CB1

t_CB2

CBUSYB^VOH

VOL

VOH

NCRn

(internal)

VOL

(*1)

VOH

BUSYBn

(internal)

VOL

1/2VDD

SPM

1/2VDD

SPP

Address is being

controlled

Command standby

Awaiting command

Playing

Awaiting command

Status

Command is being processed

*1:

Length of the “L” interval of BUSYBn is = t_CB2+ voice production time length.

Playback Stop Timing

STOP command

CSB

SCK

SI

t_CB3

VOH

CBUSYB

VOL

VOH

NCRn

(internal)

VOL

VOH

BUSYBn

(internal)

VOL

1/2VDD

SPM

1/2VDD

SPP

Playing

Awaiting command

Status

Command is being processed

18/77

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ML22594-XXX

Continuous Playback Timing by the PLAY Command

PLAY command

2^ndbyte

PLAY command PLAY command

1^stbyte 2^ndbyte

CSB

SCK

SI

t_cm

t_CB1

t_CB2

CBUSYB^VOH

VOL

VOH

NCRn

(internal)^VOL

BUSYBn

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing phrase 1

Playing phrase 2

Status

Address is being

controlled

Silence Insertion Timing by the MUON Command

PLAY command

MUON commandMUON command

PLAY command PLAY command

1^stbyte 2^ndbyte

2^ndbyte

1^stbyte 2^ndbyte

CSB

SCK

SI

t_cm

t_CB1

t_CB2

CBUSYB ^VOH

VOL

VOH

NCRn

(internal)

(*1)

VOL

BUSYBn

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing

Silence is being inserted

Waiting for silence insertion to be finished

Playing

Status

Address is being

controlled

*1: The “L” level period of the NCR pin during playback or silence insertion operation varies depending on the

timing at which the MUON command is input.

19/77

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ML22594-XXX

Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands

SLOOP command

CLOOP command

PLAY command

2^ndbyte

VIH

VIL

CSB

SCK

SI

t_INT

t_cm

t_CB2

VOH

VOL

CBUSYB

VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing

Awaiting command

Status

Address is being

controlled

Address is being

controlled

Command is being processed

Timing of Volume Change by the CVOL Command

CVOL command

1^stbyte

CVOL command

2^ndbyte

CSB

SCK

SI

t_CB1

CBUSYB^VOH

VOL

VOH

NCRn

(internal)

VOL

BUSYBn ^VOH

VOL

(internal)

Awaiting command

Status

Command is being

processed

Command is being

processed

20/77

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ML22594-XXX

External ROM interface at FLW rise

VIH

FLW

VIL

t_EFLH

PCSB^VOH

Hi-Z

VOL

PSCK^VOH

VOL

PSI^VOH

VOL

Status

Output

Hi-Z

External ROM interface at FLW fall

VIH

FLW

VIL

t_EFHL

Hi-Z

PCSB^VOH

VOL

PSCK ^VOH

Hi-Z

VOL

PSI^VOH

VOL

Status

Hi-Z

Output

21/77

FEDL22594-08

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FUNCTIONAL DESCRIPTION

Synchronous Serial Interface

The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device.

For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in

sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK

clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock.

For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the

SCK clock signal.

Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by

the signal input through the DIPH pin:

- When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges

of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock

pulses.

- When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling

edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock

pulses.

It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses

caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a

failure in normal input of command. In addition, the serial interface can be brought back to its initial state by

driving the CSB pin at a “H” level.

When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock.

When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state.

• Command Input Timing: SCK rising edge operation (when DIPH pin = “L” level)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SI

• Command Input Timing: SCK falling edge operation (when DIPH pin = “H” level)

CSB

SCK

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

SI

• Command Output Timing: SCK falling edge operation (when DIPH pin = “L” level)

CSB

SCK

(MSB)

D7 D6 D5 D4 D3 D2 D1

(LSB)

D0

SO

Command Output Timing: SCK rising edge operation (when DIPH pin = “H” level)

CSB

SCK

(MSB)

D7 D6 D5 D4 D3 D2 D1

(LSB)

D0

SO

22/77

FEDL22594-08

ML22594-XXX

To prevent malfunction caused by serial interface pin noise, the ML22594 is provided with the two-time

command input mode, where the user inputs one command two times. Use the PUP command to set the

two-time command input mode. For the method of setting the two-time command input mode, see the the

section on “1. PUP command” described later.

In two-time command input mode, input one command two times in succession. Then, the command becomes

valid only when the data input first matches the data input second. After the first data input, if a data mismatch

occurs when the second data is input, a ”H” level is output from the ERR pin. An error, if occurred, can be

cleared by the ERCL command.

PLAY command

1^stbyte

PLAY command

1^stbyte

PLAY command

2^ndbyte

PLAY command

2^ndbyte

CSB

SCK

SI

t_INTC

t_CB1

t_CB2

CBUSYB^VOH

VOL

VOH

NCRn

(internal)

VOL

VOH

BUSYBn

(internal)

VOL

1/2VDD

SPM

1/2VDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

Command is being

processed

Command is being

processed

Command is being

processed

23/77

FEDL22594-08

ML22594-XXX

To know the volume controls more

Three commands (: CVOL, AVOL and AMODE) can control volume.

CVOL sets volume of each channel. AVOL sets volume of signal after mixing.

And AMODE sets input gain of amplifier.

CVOL setting

DAG bit on AMODE

AVOL setting

Channel1

DAC

Filter

GAIN

DAC

Channel2

3

MIXING

AMP

SPP

SPM

AMP

Channel3

Channel4

GAIN

AMP

AIG bit on AMODE

AIN

Voice Synthesis Algorithm

The ML22594 contains four algorithm types to match the characteristic of playback voice: HQ-ADPCM

algorithm, 8-bit straight PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight PCM algorithm.

Key feature of each algorithm is described in the table below.

Voice synthesis

Feature

algorithm

Algorithm that enables high sound quality and high

HQ-ADPCM

compression, which have been achieved by the improved

4-bit ADPCM that uses variable bit-length coding.

Algorithm that plays back mid-range of waveform as 10-bit

equivalent voice quality.

8-bit Nonlinear PCM

8-bit PCM

Normal 8-bit PCM algorithm

16-bit PCM

Normal 16-bit PCM algorithm

24/77

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Memory Allocation and Creating Voice Data

The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM

area.

The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses

of voice data for 1024 phrases(512phrases for internal ROM, 512phases for external ROM), use/non-use of the

edit ROM function and so on.

The test area contains data for testing.

The voice area contains actual waveform data.

The edit ROM area contains data for effective use of voice data. For the details, refer to the section on “Edit

ROM Function.”

No edit ROM area is available unless the edit ROM is used.

The ROM data is created using a dedicated tool.

Configuration of Internal ROM data(6Mbit)

Configuration of External ROM data(128Mbit)

0x00000

0x000000

Voice control area

(Fixed 64Kbits)

0x01FFF

(Fixed 64Kbits)

0x001FFF

0x02000

Test area

0x002000

Test area

0x0206F

0x02070

0x00206F

0x002070

Filter area

0x021AF

0x0021AF

0x021B0

0x0021B0

Voice area

Edit ROM area

Depends on creation of ROM

data

0xFFFFFF

0xBFFFF

Playback Time and Memory Capacity

The playback time depends on the memory capacity, sampling frequency, and playback method.

The equation showing the relationship is given below.

The equation below gives the playback time when the edit ROM function is not used.

1.024 × (Memory capacity − 64) (Kbits)

Playback time =

(sec)

Sampling frequency (kHz) × Bit length

Example: Let the sampling frequency be 16 kHz and HQ-ADPCM algorithm. Then the playback time is

approx. 121 seconds, as shown below.

1.024 × (6144 − 64) (Kbits)

Playback time =

≅ 121 (sec)

16 (kHz) × 3.2 (bits) (average)

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Edit ROM Function

With the edit ROM function, multiple phrases can be played in succession. The following functions can be

configured using the edit ROM function:

 Continuous playback:

There is no limit to the continuous playback count that can be specified. It

depends on the memory capacity only.

 Silence insertion: 20 to 1024 ms

Using the edit ROM function enables an effective use of the memory capacity of voice ROM.

Below is an example of the ROM configuration in the case of using the edit ROM function.

Examples of Phrases Using the Edit ROM Function

A

E

A

B

C

D

Phrase 1

Phrase 2

Phrase 3

Phrase 4

Phrase 5

B

C

D

B

D

Silence

E

B

D

Example of ROM Data Where the Contents Above Are Stored in ROM

Address control

area

A

B

C

D

E

Editing area

26/77

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Mixing Function

The ML22594 can perform simultaneous mixing of four channels. It is possible to specify FADR, PLAY,

STOP, and CVOL for each channel separately.

• Precautions for Waveform Clamp at the Time of Channel Mixing

If channel mixing is done, the possibility of an occurrence of a clamp increases from the mixing calculation point

of view. If it is known beforehand that a clamp will occur, then adjust the sound volume of each channel using

the VOL command.

• Mixing of Different Sampling Frequency

It is not possible to perform channel mixing by a different sampling frequency group.

When performing channel mixing, the sampling frequency group of the first playback channel is selected.

Therefore, note that if channel mixing is performed by a sampling frequency group other than the selected

sampling frequency group, then the playback will not be of constant speed: some times faster and at other times

slower.

The available sampling groups for channel mixing by a different sampling frequency are listed below.

8.0 kHz, 16.0 Hz, 32.0 kHz

12.0 kHz, 24.0 kHz, 48 kHz

6.4 kHz, 12.8 kHz, 25.6 kHz

… (Group 1)

… (Group 2)

… (Group 3)

Figures below show cases where a phrase is played at a sampling frequency belonging to a different sampling

frequency group.

fs＝16.0kHz（Invalid、Will be played as fs＝12.8kHz）

fs＝16.0kHz

Channel 1

fs＝25.6kHz

Channel 2

Figure 1 Case where a phrase is played at a sampling frequency belonging to a different

sampling frequency group during playback on channels 1 and 2

Played normally if not being played by

other channel.

fs = 16.0 kHz

Channel 1

Channel 2

fs = 25.6 kHz (Valid)

End of channel 1

Figure 2 Case where a phrase is played at a sampling frequency belonging to a different

sampling frequency group after playback is finished at the other channel

27/77

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Note on continuous playback and mixing playback

The ML22594 cannot perform correctly the continuous playback and the mixing playback if the phrases in the

built-in ROM and the external ROM are combined.

When storing the speech data in both the built-in ROM and the external ROM, combine among phrases stored in

only either built-in ROM or the external ROM for the continuous playback and the mixing playback

Over-current detectible function at Speaker pins

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The over-current detectible function for the Speaker pins detect a short between SPP and SPM, and a short

between SPP/SPM and GND.

The over-current detectible function is effective on speaker power-up by the AMODE command.

AMODE

spkr_mode

powerup

AMODE

spkr_mode

powerdown

AMODE

spkr_mode

powerup

PLAY

PUP

PDWN

PUP

Serial I/F

SPVDD

SPP

SPGND

SPVDD

SPM

Status

ERR

HiZ

SPGND

analog powerup

speaker powerup

analog powerdown

speaker powerdown

analog powerdown

speaker powerdown

analog powerup

speaker powerup

DVDD

over-current detectible

function active

over-current detectible

function active

over-current detectible function for Speaker pins

When the over-current is detected, the speaker amplifier output pin(SPP/SPM) go to power-down forcibly, and a

short error is informed by the ERR pin “H”.

In the case of error outbreak, please confirm a status of error by the RDSTAT command, stop playback, and set

the speaker power-down by the AMODE command. Afterwards, please clear an error by the ERCL command.

If performing playback again, set the speaker power-up by the AMODE command, and next set the PLAY

command.

However, when shorting to GND is going on, even if the following operation is done, the speaker amplifier

output pin(SPP/SPM) go to power-down forcibly, and the ERR pin becomes “H”.

(1)After setting power-down by the AMODE command , do power-up by the AMODE command

(2)After detect a short error, when input ERCL command without power-down operation of speaker amplifier

by the AMODE command

AMODE

spkr_mode

powerdown

AMODE

spkr_mode

powerup

AMODE

spkr_mode

powerup

RDSTAT

ERR read

Serial I/F

SPP

ERCL

PUP

SPVDD

SPGND

SPVDD

SPM

HiZ

SPGND

detect a short

analog powerup

speaker powerup

analog powerup

speaker powerup

analog powerup

speaker powerdown

analog powerdown

speaker powerdown

analog powerdown

speaker powerdown

Status

ERR

over-current detectible

function active

over-current detectible

function active

over-current detectible function Operation Flow

(Example)

29/77

FEDL22594-08

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Command List

Each command is configured in 1-byte (8-bit) units. Each of the AMODE, AVOL FADR, PLAY, MUON, and

CVOL commands forms one command by two bytes.Be sure to input the following commands only.

Input each command with CBUSYB set to a ”H” level.

Command D7

D6

D5

D4

D3

D2

D1

D0

Description

Shifts the device currently

powered down to a command

PUP

0

WCM wait state. Also the two-time

command input mode is set

by this command.

Analog section control

command.

Configures settings for

power-up operation and

analog input/output.

0

1

HPF1 HPF0

AMODE

AVOL

DAG1 DAG0 AIG1 AIG0

DAEN

SPEN POP

Selects the type of HPF.

Analog mixing signal volume

setting command. Use the

data of the 2nd byte to

specify volume.

0

—

0

—

0

AV5

0

AV4

0

1

AV3

1

0

AV2

1

0

AV1

0

AV0

0

Sets the fade-in time in cases

where the speaker amplifier

is enabled by the AMODE

command.

FAD

0

FAD3

FAD2

FAD1 FAD0

Shifts the device from a

command wait state to a

power-down state.

PDWN

FADR

0

1

0

Playback phrase specification

command.

Can be specified for each

channel.

0

F7

0

F6

1

F5

0

1

F4

0

C1

F3

C1

C0

F2

C0

F9

F1

F9

F8

F0

F8

Playback start command.

Use the data of the 2nd byte

to specify a phrase number.

Can be specified for each

channel.

PLAY

F7

F6

F5

F4

F3

F2

F1

F0

Playback start command

without phrase specification.

Used to start playback on

multiple channels at the same

time after phrases are

START

0

1

0

1

0

CH3

CH2

CH1

CH0 specified with the FADR

command. After a phrase is

played with the PLAY

command, the same phrase

can be played with this

command.

Playback stop command.

CH0 Can be specified for each

channel.

STOP

30/77

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ML22594-XXX

Command D7

0

D6

1

D5

1

D4

1

D3

D2

D1

D0

Description

Silence insertion command.

Use the data of the 2nd byte

to specify the length of

silence. Can be specified

for each channel.

CH3

CH2

CH1

CH0

MUON

M7

M6

M5

M4

M3

M2

M1

M0

Repeat playback mode

setting command. The

setting is enabled during

playback.

Can be specified for each

channel.

SLOOP

CLOOP

1

0

CH3

CH2

CH1

CH0

Repeat playback mode

release command. When

the STOP command is input,

0

1

CH3

CH2

CH1

CH0 repeat playback mode is

released automatically. Can

be specified for each

channel.

Volume setting command.

CH0

1

0

1

0

CH3

CV3

CH2

CV2

CH1

CV1

Use the data of the 2nd byte

CVOL

to specify volume. Can be

—

CV4

CV0

specified for each channel.

Status serial read command.

This command reads the

ERR

RDSTAT

1

0

1

0

command status and the

status of the fail safe function

for each channel.

Status output command.

This command outputs the

command status of each

channel from the STATUS

pin.

0

BUSY/NCR

C1

0

C0

0

OUTSTAT

1

0

1

Fail safe setting command.

Sets settings for power

supply voltage detection,

temperature detection, and

monitoring time.

0

SAFE

ERCL

TM2 TM1

TM0 TSD1 TSD0

BLD2

BLD1 BLD0

This command clears error

while the fail safe function is

operating.

1

31/77

FEDL22594-08

ML22594-XXX

Description of Command Functions

1. PUP command

 command

0

WCM

The PUP command is used to shift the ML22594 from a power down state to a command waiting state.

The ML22594 can only accept the PUP command while it is in a power down state. Therefore, in a power

down state, the device will ignore any other command if entered.

The ML22594 enters a power down state under any of the following conditions:

1) When power is turned on

2) At RESETB input

3) When CBUSYB go to a “H” level after inputting the power down command

CSB

SCK

t_PUP

SI

CBUSYB

Oscillation stopped

Oscillating

XTXTB

Reset being

processed

Status

Power down

Awaiting command

Oscillation stabilized

The WCM bit is used to set the two-time command input mode. When set to ”1”, the command input thereafter

will be processed in two-time command input mode and becomes valid only when the first data input matches

the second one.

WCM Two-time command input mode

0

1

No (initial value)

Yes

The regulator starts operating after the PUP command is entered. Any command will be ignored if entered

while oscillation is stabilized. However, if a “L” level is input to the RESETB pin, the LSI enters a power

down state immediately.

Neither line output nor speaker output is enabled by the PUP command. Power up the analog section by the

AMODE command.

32/77

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ML22594-XXX

2. AMODE command

 command

0

1

HPF1

HPF0

POP

1st byte

2nd byte

DAG1 DAG0 AIG1 AIG0 DAEN SPEN

The AMODE command is used to configure various settings for the analog section.

If the PDWN command is input while the analog section is in the power-up state, the analog section enters a

power down state under the setting conditions that were in effect when the analog section was powered up by the

AMODE command. To perform a power-down operation using different conditions from those used at analog

section power-up, set settings by the AMODE command.

To change the setting of DAEN/SPEN while the analog section is in the power-up state, first put the analog

section into the power-down state and then put the analog section into the power-up state again by the AMODE

command.

The detailed command settings are shown below.

Each setting is initialized upon reset release or by the PUP command.

Don’t input the STOP command during the AMODE command is being proccessed (CBUSYB=”L”).

Input the AMODE command for analog section into the power-down state before the PDWN command is input.

The HPF1/HPF0 bits set the cut-off frequency of the HPF.

HPF1

HPF0

Cut-off frequency

Off (initial value)

200 Hz

300 Hz

400 Hz

0

1

0

1

0

1

The POP bit specifies whether to suppress generation of “pop” noise.

- If the bit is “0” (no pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND

level to the SG level in about 35 ms, at which time the analog section enters the power-up state. If the DAEN

bit is “0”, the LINE output falls from the SG level to the DGND level in about 110 ms, at which time the

analog section enters the power down state.

- If the bit is “1” (with pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND

level to the SG level in about 90 ms, at which time the analog section enters the power-up state. If the DAEN

bit is “0”, the LINE output falls from the SG level to the DGND level in about 140 ms, at which time the

analog section enters the power down state.

POP

Pop noise suppression

0

1

No (initial value)

Yes

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 When powering up the speaker amplifier

Setting values: POP bit = “0”, DAEN and SPEN bits = “0” → “1”

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PUPA1

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

LINE output _GND

(internal)

1/2SPVDD

Hi-Z

SPM

GND

SPP

Command is being

processed

Status

Awaiting command

Command is being

processed

 When powering up the line amplifier (with pop noise suppression)

Setting values: POP bit = “1”, DAEN bit = “0” → “1” (SPEN bit = “0”)

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PUPA2

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

SPP

GND

(LINE output)

Awaiting command

POP noise suppressed

Status

Awaiting command

Command is being

processed

Command is being

processed

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 When powering up the line amplifier (without pop noise suppression)

Setting values: POP bit = “0”, DAEN bit = “0” → “1” (SPEN bit = “0”)

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PUPA3

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

SPP

GND

(LINE output)

Command is being

processed

Awaiting command

Status

Awaiting command

Command is being

processed

 When putting the speaker amplifier into the power down state

Setting values: POP bit = “0”, DAEN and SPEN bits = “1” → “0”

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PDA1

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

1/2SPVDD

LINE output

SPM

GND

Hi-Z

SPP

GND

Command is being

processed

Status

Awaiting command

Command is being

processed

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 When putting the line amplifier into the power down state (with pop noise suppression)

Setting values: POP bit = “1”, DAEN bit = “1” → “0” (SPEN bit = “0”)

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PDA2

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

SPP

GND

(LINE output)

Awaiting command

POP noise suppressed

Status

Awaiting command

Command is being

processed

Command is being

processed

 When putting the line amplifier into the power down state (without pop noise suppression)

Setting values: POP bit = “0”, DAEN bit = “1” → “0” (SPEN bit = “0”)

AMODE command

1st byte

AMODE command

2nd byte

CSB

SCK

SI

t_CB1

t_PDA3

VOH

VOL

CBUSYB

VOH

VOL

NCR

(internal)

VOH

VOL

BUSYB

(internal)

1/2DVDD

SPP

GND

(LINE output)

Command is being

processed

Awaiting command

Status

Awaiting command

Command is being

processed

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The DAG1,0 bits are used to set the gain of the internal DAC signal. The AIG1,0 bits are used to set the gain

of an analog signal from the AIN pin. DAG1,0 and AIG1,0 are only enabled when the speaker amplifier is

used.

DAG1 DAG0

Volume

0

1

0

1

0

1

Input OFF

Input ON (–6 dB)

Input ON (0 dB) (initial value)

Input ON (0 dB) (Setting prohibited)

AIG1

AIG0

Volume

0

1

0

1

0

1

Input OFF (initial value)

Input ON (–6 dB)

Input ON (0 dB)

Input ON (0 dB) (Setting prohibited)

Input the analog signal from the AIN pin after the AMODE command (CBUSYB=”H”).

The DAEN bit takes power-up and power-down control of the DAC section.

DAEN

Status of the DAC section

0

1

Power-down state (initial value)

Power-up state

The SPEN bit takes power-up and power-down control of the speaker section.

When the SPEN bit = “0”, the SPP pin is configured as a LINE output.

SPEN

Status of the speaker section

0

1

Power-down state (initial value)

Power-up state

Relationship between DAEN, SPEN, and POP signals and the analog section

DAEN

SPEN POP

Mode

Status

At speaker output

Power-down (initial value)

0

Power-down (without pop noise

suppression)

At LINE output

Power-down

Power-down (with pop noise

suppression)

At speaker output

At LINE output

0

1

DAC/speaker power-up

―

1

0

―

Speaker output

LINE output

DAC power-up (without pop noise

suppression)

1

0

DAC power-up (with pop noise

suppression)

1

0

1

LINE output

Pin status during power down

The status of each output pin during power down by the AMODE command is shown below.

Analog output pin

State

DGND

Hi-Z

V_DDL

V_DDR

SG

SPM

SPP

DGND

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3. AVOL commnd

 command

0

1

0

1st byte

2nd byte

AV5 AV4 AV3 AV2 AV1 AV0

The AVOL command is used to adjust the volume of the speaker amplifier. It is possible to input the AVOL

command regardless of the status of the NCR signal.

The command enables 50-level adjustment of volume, as shown in the table below. When the PUP or AMODE

command is input, the value set by the AVOL command is initialized (0 dB).

AV5–0

3F

3E

3D

3C

3B

3A

39

38

37

36

35

34

33

32

31

30

2F

2E

2D

2C

2B

2A

29

28

27

26

25

24

23

22

21

20

Volume

+12dB

AV5–0

1F

1E

1D

1C

1B

1A

19

18

17

16

15

14

11

12

11

10

0F

0E

0D

0C

0B

0A

09

08

07

06

05

04

03

00

01

00

Volume

−8.0

−9.0

+11.5

+11.0

+10.5

+10.0

+9.5

+9.0

+8.5

+8.0

+7.5

+7.0

+6.5

+6.0

+5.5

+5.0

+4.5

+4.0

+3.5

+3.0

+2.5

+2.0

+1.5

+1.0

+0.5

+0.0 (initial value)

−1.0

−2.0

−3.0

−4.0

−5.0

−6.0

−7.0

−10.0

−11.0

−12.0

−13.0

−14.0

−16.0

−18.0

−20.0

−22.0

−24.0

−26.0

−28.0

−30.0

−32.0

−34.0

OFF

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4. FAD command

 command

0

1

0

1st byte

2nd byte

FAD3

FAD2

FAD1

FAD0

The FAD command is used to set the fade-in time for the speaker amplifier.

The fade-in time cna be adjusted through 16 levels, as shown in the table below. The initial value after reset is

298 µs. When the PUP command is input, the value set by the FAD command is initialized (298 µs).

FAD3–0 Fade-in time (µs)

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

442

422

401

381

360

340

319

298 (initial value)

278

257

237

216

195

175

154

134

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5. PDWN command

 command

0

1

0

The PDWN command is used to shift the ML22594 from a command waiting state to the power down state.

However, since every setting will be initialized after entering the power down state, initial settings need to be set

after power-up. This command is invalid during playback.

To resume playback after the ML22594 has shifted to the power down state, first input the PUP and AMODE

commands and then input the PLAY command.

CSB

SCK

SI

CBUSYB

NCR

(internal)

BUSYB

(internal)

Oscillation

Oscillating

stopped

XT•XTB

Command is being

processed

Status

Awaiting command

Power down

Oscillation stops after a lapse of command processing time after the PDWN command is input. The regulator

stops operation after a lapse of command processing time after the PDWN command is input. At this time, the

SPM output of the speaker amplifier goes into a Hi-Z state to prevent generation of pop noise.

Initial stauts at reset input and status during power down

The status of each output pin is as follows:

Analog output pin

State

DGND

Hi-Z

V_DDL

V_DDR

SG

SPM

SPP

DGND

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6. FADR command

 command

0

1

C1

F3

C0

F2

F9

F1

F8

F0

1st byte

2nd byte

F7

F6

F5

F4

The FADR command is used to specify a phrase to be played. A playback channel and a playback phrase are

set by this command. The FADR command can be set for each channel; however, the command cannot be

input for multiple channels simultaneously. Input the FADR command with each NCR set to a ”H” level.

When a playback phrase is specified for each channel, use the START command to start playback.

Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data,

specify the phrase that was specified when the ROM was created.

Number of phrase ( Internal ROM and External ROM )

Number of phrase

F9-F0

Internal ROM

External ROM

512

000h – 1FFh

200h – 3FFh

Channel settings

C1

C0

0

Channel

0

1

Channel 0

Channel 1

Channel 2

Channel 3

1

0

1

The diagram below shows the timing for specifying (F9–F0) = 02H as the phrase to play on channel 1.

FADR command

1st byte

FADR command

2nd byte

CSB

SCK

SI

CBUSYB

NCR

(internal)

BUSYB

(internal)

Awaiting command

Status

Command is being

processed

Command is being

processed

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7. PLAY command

 command

0

1

0

C1

F3

C0

F2

F9

F1

F8

F0

1st byte

2nd byte

F7

F6

F5

F4

The PLAY command is used to start playback with phrase specified. This command can be input when the

NCR signal on the target channel is at a “H” level.

Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data,

specify the phrase that was specified when the ROM was created.

The figure below shows the timing of phrase (F9–F0 = 01H) playback.

PLAY command

1st byte

PLAY command

2nd byte

CSB

SCK

SI

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Address is being

controlled

Awaiting command

Playing

Awaiting command

Status

Command is being processed

When the 1^stbyte of the PLAY command is input, the device enters a state awaiting input of the 2^ndbyte of the

PLAY command after a lapse of command processing time. When the 2^ndbyte of PLAY command is input,

after a lapse of command processing time, the device starts reading from the ROM the address information of the

phrase to be played. Thereafter, playback operation starts, the playback is performed up to the specified ROM

address, and then the playback terminates automatically.

The NCR signal is at a “L” level during address control, and goes “H” when the address control is finished and

playback starts. When the NCR signal on the target channel goes “H”, it is possible to input the PLAY

command for the next playback phrase.

During address control, the BUSYB signal is at a “L” level during playback and goes “H” when playback is

finished. Whether the playback is going on can be known by the BUSYB signal.

Number of phrase ( Internal ROM and External ROM )

Number of phrase

F9-F0

Internal ROM

External ROM

512

000h – 1FFh

200h – 3FFh

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Channel settings

C1

C0

0

Channel

Channel 0

Channel 1

Channel 2

Channel 3

0

1

0

1

PLAY Command Input Timing for Continuous Playback

The diagram below shows the PLAY command input timing in cases where one phrase is played and then the

next phrase is played in succession.

PLAY command

2nd byte

PLAY command PLAY command

1st byte 2nd byte

CSB

SCK

SI

t_cm

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing phrase 1

Playing phrase 2

Status

Address is being controlled

As shown in the diagram above, if performing continuous playback, input the PLAY command for the second

phrase within 10 ms (t_cm) after the NCR signal on the target channel goes “H”. Input the following PLAY

command after checking that playback is completed by the RDSTAT command, when it is not continuous

playback.

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8. START command

 command

0

1

0

1

CH3 CH2 CH1 CH0

The START command is a channel synchronization start (i.e., starts phrase playback on multiple channels

simultaenously) command. It is necessary to specify playback phrases using the FADR command before

inputting the START command. Setting any bit(s) from CH0 to CH3 to “1” starts playback on the

corresponding channel(s). Input the START command with each NCR set to a ”H” level.

The figure below shows the timing when starting playback on channel 00 and channel 1 simultaneously.

Channel settings

Channel

CH0

CH1

CH2

CH3

Setting this bit to “1” starts playback on channel 0.

Setting this bit to “1” starts playback on channel 1.

Setting this bit to “1” starts playback on channel 2.

Setting this bit to “1” starts playback on channel 3.

Be sure to set the channel setting bits( CH0-CH3).

START command

CSB

SCK

SI

t_cB2

CBUSYB

NCR0

(internal)

NCR1

(internal)

BUSYB0

(internal)

BUSYB1

(internal)

SPP output

Address is

being controlled

Awaiting

command

Awaiting

command

Playing

Status

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START Command Input Timing for Continuous Playback

The diagram below shows the START command input timing in cases where one phrase is played and then the

next phrase is played in succession.

START command

CSB

SCK

SI

t_cm

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing phrase 1

Playing phrase 2

Status

Address is being controlled

As shown in the diagram above, if performing continuous playback, input the START command for the second

phrase within 10 ms (t_cm) after the NCR signal on the target channel goes “H”. Input the following START

command after checking that playback is completed by the RDSTAT command, when it is not continuous

playback.

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9. STOP command

 command

0

1

0

CH3 CH2 CH1 CH0

The STOP command is used to stop playback. It can be set for each channel. Setting any bit(s) from CH0 to

CH3 to “1” stops playback on the corresponding channel(s). If the speech synthesis processing for all channels

stops, the AOUT output goes to the V_SGlevel and the NCR and BUSYB signals go to a “H” level.

Although it is possible to input the STOP command regardless of the status of NCR during playback, a

prescribed command interval time needs taking.

STOPcommand

CSB

SCK

SI

CBUSYB

NCR

fs×29cycle

(internal)

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Command is being

processed

Playing

Awaiting

Status

Channel settings

Channel

CH0

Setting this bit to “1” stops playback on channel 0.

Setting this bit to “1” stops playback on channel 1.

Setting this bit to “1” stops playback on channel 2.

Setting this bit to “1” stops playback on channel 3.

CH1

CH2

CH3

Be sure to set the channel setting bits( CH0-CH3).

The STOP command allows specifying multiple channels at one time.

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10. MUON command

 command

0

1

CH3 CH2 CH1 CH0

M3 M2 M1 M0

1st byte

2nd byte

M7

M6

M5

M4

The MUON command allows inserting a silence between two playback phrases. The command can be input

when the NCR signal on the target channel is at a “H” level.

Set the silence time length after inputting this command. It can be set for each channel. The MUON

command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” plays

silence on the corresponding channel(s).

Channel settings

Channel

CH0

CH1

CH2

CH3

Setting this bit to “1” inserts a silence on channel 0.

Setting this bit to “1” inserts a silence on channel 1.

Setting this bit to “1” inserts a silence on channel 2.

Setting this bit to “1” inserts a silence on channel 3.

Be sure to set the channel setting bits( CH0-CH3).

As the silence length (M7–M0), a value between 20 ms and 1024 ms can be set at 4 ms intervals (252 steps in

total).

The equation to set the silence time length is shown below.

The silence length (M7–M0) must be set to 04h or higher.

t_mu=(2⁷×(M7)+2⁶×(M6)+2⁵×(M5)+2⁴×(M4)+2³×(M3)+2²×(M2)+2¹×(M1)+2⁰×(M0)+1)×4ms

The figure below shows the timing of inserting a silence of 20 ms between the repetitions of a phrase of (F7–F0)

= 01h.

PLAY command

2nd byte

MUON command MUON command

1st byte 2nd byte

PLAY command PLAY command

1st byte

2nd byte

CSB

SCK

SI

t_cm

CBUSYB

NCR

(internal)

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing

Silence is being inserted

Playing

Status

Waiting for silence insertion

to be finished

Address is being controlled

Waiting for playback to be finished

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When the PLAY command is input, the address control over phrase 1 ends, the phrase playback starts, and the

CBUSYB and NCR signals go to a “H” level. Input the MUON command after this CBUSYB signal changes

to a “H” level. After the MUON command input, the NCR signal remains “L” until the end of phrase 1

playback, and the device enters a state waiting for the phrase 1 playback to terminate.

When the phrase 1 playback is terminated, the silence playback starts and the NCR signal goes to a “H” level.

After the NCR signal has gone to a “H” level, re-input the PLAY command in order to play phrase 1.

After the PLAY command input, the NCR signal once again goes to a “L” level and the device enters a state

waiting for the termination of silence playback.

When the silence playback is terminated and then the phrase 1 playback starts, the NCR signal goes “H”, and the

device enters a state where it is possible to input the next PLAY or MUON command.

The BUSYB signal remains “L” until the end of a series of playback.

As shown in the diagram above, if performing continuous playback, input the MUON/PLAY/START command

for the second phrase within 10 ms (t_cm) after the NCR signal on the target channel goes “H”. Input the following

MUON/PLAY/START command after checking that playback is completed by the RDSTAT command, when it

is not continuous playback.

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11. SLOOP command

 command

1

0

CH3 CH2 CH1 CH0

The SLOOP command is used to set repeat playback mode. The command can be input for each channel.

The SLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to

“1” repeats playback on the corresponding channel(s). Input the SLOOP command with each NCR set to a ”H”

level.

Channel settings

Channel

CH0

CH1

CH2

CH3

Setting this bit to “1” repeats playback on channel 0.

Setting this bit to “1” repeats playback on channel 1.

Setting this bit to “1” repeats playback on channel 2.

Setting this bit to “1” repeats playback on channel 3.

Be sure to set the channel setting bits( CH0-CH3).

Once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is

released by the SLOOP command or until playback is stopped by the STOP command. In the case of a phrase

that was edited using the edit function, the edited phrase is repeatedly played. Following shows the SLOOP

command input timing.

PLAY command

2nd byte

SLOOP command

CLOOP command

CSB

SCK

SI

CBUSYB

NCR

(internal)

t_cm

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing

Awaiting command

Status

Address is being controlled

Command is being processed

Effective Range of SLOOP Command Input

The SLOOP command is only enabled during playback. After the PLAY command is input, input the SLOOP

command within 10 ms (t_cm) after the NCR signal on the target channel goes “H”. This will enable the SLOOP

command, so that repeat playback will be carried out. The NCR signal remains “L” during repeat playback

mode.

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12. CLOOP command

 command

1

0

1

CH3 CH2 CH1 CH0

The CLOOP command releases repeat playback mode. The command can be input for each channel. The

CLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1”

releases repeat playback on the corresponding channel(s). When repeat playback mode is released, the NCR

signal goes “H”.

It is possible to input the CLOOP command regardless of the status of the NCR signal during playback, but a

prescribed command interval needs taking.

Channel settings

Channel

CH0

CH1

CH2

CH3

Setting this bit to “1” releases repeat playback on channel 0.

Setting this bit to “1” releases repeat playback on channel 1.

Setting this bit to “1” releases repeat playback on channel 2.

Setting this bit to “1” releases repeat playback on channel 3.

Be sure to set the channel setting bits( CH0-CH3).

PLAY command

2nd byte

SLOOP command

CLOOP command

CSB

SCK

SI

CBUSYB

NCR

(internal)

t_cm

BUSYB

(internal)

1/2VDD

SPM

1/2VDD

SPP

Awaiting command

Playing

Awaiting command

Status

Address being

controlled

Command being

processed

Command being

processed

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13. CVOL command

 command

1

0

1

0

CH3 CH2 CH1 CH0

1st byte

2nd byte

CV4 CV 3 CV 2 CV 1 CV 0

The CVOL command is used to adjust the playback volume on each channel. It is possible to input the VOL

command regardless of the status of the NCR signal.

The CVOL command can be set for each channel. The CVOL command allows specifying multiple channels at

one time. Setting any bit(s) from CH0 to CH3 to “1” sets the playback volume on the corresponding channel(s).

The volume setting is initialized by the AMODE command.

Channel settings

Channel

CH0

CH1

CH2

CH3

Setting this bit to “1” sets the volume on channel 0.

Setting this bit to “1” sets the volume on channel 1.

Setting this bit to “1” sets the volume on channel 2.

Setting this bit to “1” sets the volume on channel 3.

Be sure to set the channel setting bits( CH0-CH3).

The command enables 32-level adjustment of volume, as shown in the table below. The initial value after reset

release is set to 0 dB. Upon reset release or when the PUP command is input, the values set by the CVOL

command are initialized.

CV4–0

1F

1E

1D

1C

1B

1A

19

18

17

16

15

Volume

0 dB (initial value)

−0.28

CV4–0

0F

0E

0D

0C

0B

0A

09

08

07

06

05

Volume

−6.31

−6.90

−7.55

−8.24

−0.58

−0.88

−1.20

−1.53

−1.87

−2.22

−2.59

−2.98

−3.38

−3.81

−4.25

−4.72

−5.22

−5.74

−9.00

−9.83

−10.74

−11.77

−12.93

−14.26

−15.85

−17.79

−20.28

−23.81

−29.83

OFF

14

13

12

11

04

03

02

01

10

00

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14. RDSTAT command

 command

1

0

1

0

ERR

The RDSTAT command enables reading the status of internal operation. It is possible to input the CLOOP

command regardless of the status of the NCR signal during playback, but a prescribed command interval needs

taking.

The ERR bit selects reading the playback status for each channel or reading the status of the fail-safe function.

Keep the SI pin to “L” when read the status.

ERR

Content of data to read

0

1

NCR and BUSYB signals for each channel (Initial value)

Status of the fail-safe function

If the ERR bit is set to ”0”, the following status will be read:

Output bit

Output

data

D7

D6

D5

D4

D3

D2

D1

D0

BUSYB3

BUSYB2

BUSYB1

BUSYB0

NCR3

NCR2

NCR1

NCR0

When the ERR bit = ”0”, the NCR and BUSYB signals of each channel are read. The NCR signal outputs a “L”

level while this LSI is performing command processing and goes to a “H” level when the LSI enters a command

waiting state. The BUSY signal outputs a “L” level during voice playback.

The table below shows the contents of each data output at a status read.

Output status signal

BUSY3

BUSY2

BUSY1

BUSY0

NCR3

Channel 3 BUSYB output

Channel 2 BUSYB output

Channel 1 BUSYB output

Channel 0 BUSYB output

Channel 3 NCR output

Channel 2 NCR output

Channel 1 NCR output

Channel 0 NCR output

NCR2

NCR1

NCR0

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If the ERR bit is set to “1”, the following status will be read

Output bit

OutPut

data

D7

0

D6

0

D5

D4

D3

D2

D1

D0

EXR

ERR

SPM

ERR

SPP

ERR

TSD

ERR

BLD

ERR

WCM

ERR

When the ERR bit=”1”, the state of six fail-safe Function is read.

If any of fail-safe function is activated,the ERR pin is set to a “H” level and the corresponding

error bit is set to “1”. If the ERR pins set to a “H” level,

check the error contents using the RDSTAT command and take appropriate measures.

ERR bit is cleared by ERCL command

Error signal

EXRERR

Error contents

External ROM read err bit.

This bit is set to “1” if the voice control area data of External ROM is “00h”.

It becomes an error when it accesses the External ROM under the condition that the External

ROM isn't connected.

SPM pin short error bit.

This bit is set to “1” if the SPM pin is short to SPP pin or GND

SPP pin short error bit

This bit is set to “1” if the SPP pin is short to SPM pin or GND

High temperature error bit.

SPMERR

SPPERR

TSDERR

This bit is set to “1” if the temperature of the LSI reaches or exceeds the temperature set by the

SAFE command. For details see the section on the SAFE command.

Power supply voltage error bit.

BLDERR

This bit is set to “1” if the power supply voltage level reaches or falls below the voltage set by

the SAFE command. For details see the section on the SAFE command.

Command tansfer errro bit.

WCMERR

This bit is set to “1” if a transfer error occurs in two-time command input mode.

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15. OUTSTAT command

 command

1

0

BUSY/NCR

C1

C0

The OUTSTAT command is used to output the BUSYB or NCR signal on the specified channel from the

STATUS pin. It is possible to input the CLOOP command regardless of the status of the NCR signal during

playback, but a prescribed command interval needs taking.

BUSY/NCR

STATUS pin status

Outputs the NCR signal on the specified channel.

Outputs the BUSYB signal on the specified channel.

0

1

Channel settings

C1

0

C0

0

Channel

Channel 0 (initial value)

Channel 1

0

1

0

Channel 2

1

Channel 3

OUTSTAT command

CSB

SCK

SI

CSB

SCK

SI

CBUSYB

NCR

(internal)

NCR

(internal)

BUSYB

(internal)

STATUS

(output)

STATUS

(output)

NCR output

BUSYB output

NCR output

BUSYB output

STATUS

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16. SAFE command

 command

1

0

1

0

TM2 TM1 TM0 TSD1 TSD0 BLD2 BLD1 BLD0

The SAFE command is sets the settings for the low-voltage detection and temperature detection functions.

The BLD2–0 bits are used to set the power supply voltage detection level. The judgment voltage can be

selected from among six levels from 2.7 to 4.0 V. The power supply voltage is monitored each time it reaches

the value set by TM2–0, and if the power supply voltage reaches or falls below the set detection voltage two

times or more, the ERR pin outputs a ”H” level and the RDSTAT command’s BLDERR bit is set to ”1”.

If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the BLDERR bit

is at ”1”, it is possibly a power supply related failure.

BLD2 BLD1 BLD0 Judgment power supply voltage

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OFF

2.7V±5% (initial value)

3.0V±5%

3.3V±5%

3.6V±5%

4.0V±5%

(4.0V±5%)

The TSD1–0 bits are used to set the temperature detection level. Tj=140°C or OFF can be selected as the

judgment temperature. The temperature is monitored each time it reaches the value set by TM2–0, and if the

temperature reaches or exceeds the set value two times or more, the ERR pin outputs a ”H” level and the

RDSTAT command’s TSDERR bit is set to ”1”.

If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the TSDERR bit

is at ”1”, reduce the volume using the AVOL command or put the analog section into the power down state

using the AMODE command.

TSD1 TSD0

Judgment temperature (Tj)

0

1

0

1

0

1

OFF

Setting prohibited

140±10°C (initial valle,)

The judgment temperature(Tj) is 140±10°C. This LSI is beyond Tj=130°C in the operating temperature(-40°C -

+150°C) depending on a operating condition and occurs by a high temperature error. The ambient temperature

at that case is as follows.

Power supply(D^VDD=SP^VDD

)

Power dissipation(P_D)

0.686W

Amient temperature(Ta)

Not detect in the operating temperature

detect more than 104°C

4.5V

5.0V

5.5V

0.861W

1.055W

detect more than 98°C

*θja＝31.2[°C/W](JEDEC 2layers(refer to 67pages)), 1W/8ohm-Speaker

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θja changes by an implementation condition. The maximum ambient temperature(Tamax) that this LSI does

not detect the high temperature error is calculated in the following expressions in using the power dissipation.

Tamax = 130[°C]

The maximum ambient temperature(Tamax) in power supply voltage 5.0V and θja=36[°C/W] is as follows.

Tamax = 130[°C] 36 × 0.861 ≒ 99[°C]

-

θja[°C/W] × P_D[W]

-

The TM2–0 bits are used to set the monitor interval to detect a low voltage or temperature.

TM2 TM1 TM0

Monitor interval

Constantly monitors

2 ms (initial value)

4 ms

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 ms

16 ms

32 ms

64 ms

128 ms

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17. ERCL command

 command

1

The ERCL command is used to clear an error if it occurs.

If an error occurs, a “H” level is outputted from the ERR pin. When the ERCL command is inputted, the ERR

pin outputs a ”L” level.

However, when the high temperature error and the power-supply voltage error continue, TSDERR of the

RDSTAT command , BLDERR of the RDSTAT command and the ERR pin keep outputting "H" even if the

ERCL command is inputted.

Timing diagram for when an error occurs at the time of setting the two-time command input mode

START command

2nd times

ERCL command

1st time

ERCL command

2nd times

VIH

VIL

CSB

SCK

SI

t_INTC

t_CB1

VOH

VOL

CBUSYB

VOH

VOL

NCRn

(internal)

BUSYBn

(internal)

ERR

RDSTAT

ERR register

(internal)

00h

01h

00h

Timing diagram for when an error occurs at the External ROM

ERCLcommand

CSB

SCK

SI

t_CB1

VOH

CBUSYB

VOL

RDSTAT

00h

ERRregister

(internal)

20h

00h

ERR

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If a power supply voltage error occurs and then the power supply voltage is returned (when the SAFE

command’s BLD2–0 bits = 001h)

ERCL command

CSB

SCK

SI

t_CB1

VOH

CBUSYB

VOL

RDSTAT

ERR register

00h

02h

00h

(internal)

ERR

3.0V

2.6V

3.0V

DV_DD

If a power supply voltage error occurs but the power supply voltage is not returned

ERCL command

CSB

SCK

SI

t_CB1

VOH

CBUSYB

VOL

RDSTAT

ERR register

00h

02h

(internal)

ERR

3.0V

2.6V

DV_DD

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When Speaker-short situation is released before Error Clear Flow(*1)

AMODE

spkr_powerup

AMODE

spkr_powerdown

AMODE

spkr_powerup

RDSTAT

ERCL

Serial I/F

RDSTAT

ERR reg

(internal)

00h

10h (*2)

ERR

Speaker short

State

When Speaker-short situation is continued after Error Clear Flow(*1).

AMODE

spkr_powerup

AMODE

spkr_powerdown

AMODE

spkr_powerup

RDSTAT

ERCL

Serial I/F

RDSTAT

ERR reg

(internal)

00h

10h (*2)

00h

10h

ERR

Speaker short

State

When ERCL is inputed before Error Clear Flow(*1).

AMODE

spkr_powerup

AMODE

spkr_powerdown

ERCL

RDSTAT

ERCL

Serial I/F

RDSTAT

ERRreg

(internal)

10h (*2)

00h

10h (*2)

00h

ERR

Speaker short

State

*1:Error Clear Flow:RDSTAT=>AMODE(Speaker Power-down) => ERCL

*2: SPM pin short error

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Command Flow Charts

1-Byte Command Input Flow (applied to the PUP, PDWN, START, STOP, SLOOP, CLOOP, OUTSTAT, and

ERCL commands)

Start

CBUSYB “H”?

N

Y

Input command

CBUSYB “H”?

N

Y

End

1-Byte Command Input Flow (STOP commands)

Start

CBUSYB

“H”?

N

Y

Input command

BUSYB

“H”?

N

Y

End

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2-Byte Command Input Flow (applied to the AMODE, AVOL, FAD, FADR, PLAY, MUON, CVOL, and SAFE

commands)

Start

CBUSYB “H”?

N

Y

Input the 1st byte of command

CBUSYB “H”?

N

Y

Input the 2nd byte of command

CBUSYB “H”?

N

Y

End

Status Read Flow

RDSTAT command

CBUSYB “H”?

N

Y

Read status (SI=”L”)

Power-On Flow

Apply power, Drive RESETB “L”

Waited for

10 µs?

N

Y

Drive RESETB “H”

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Example of Power-Up Flow

Power-down state

PUP command

AMODE command

Example of Playback Start Flow

Power-up state

Idle (not playback)?

Y

N

Single-channel playback

PLAY command

Multi-channel playback

FADR command

START command

Example of Playback Stop Flow

Playing

STOP command

Continuous Playback Start Flow

PLAY/START/MUON command

Playback(playing)

Within 10mS

PLAY/START/MUON command

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Loop Start Flow

PLAY/START command

Playback(playing)

Within 10mS

SLOOP command

Loop Stop Flow

Looping

Stop after playback is finished all the

way through the phrase

Stop playback forcibly

STOP command

CLOOP command

Power-Down Flow

Power-up state

PDWN command

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Detailed Flow of “Power-Up ⇒ Playback ⇒ Power-Down”

Power-down state

A

CBUSYB “H”?

N

CBUSYB “H”?

N

Y

PUP command

RDSTAT command

CBUSYB “H”?

N

CBUSYB “H”?

Y

N

Y

1st byte of AMODE command

Read status

CBUSYB “H”?

N

BUSYB “H”?

Y

N

Y

2nd byte of AMODE command

1st byte of AMODE command

CBUSYB “H”?

N

CBUSYB “H”?

N

Y

1st byte of PLAY command

2nd byte of AMODE command

CBUSYB “H”?

N

CBUSYB “H”?

Y

N

Y

2nd byte of PLAY command

PDWN command

CBUSYB “H”?

A

N

Y

Power-down state

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Detailed flow of “SPP/SPM Short detecting”

SPPERR/SPMERR

ERR ”H”

RDSTAT command

CBUSYB ”H”

N

Y

*It is confirmed that SPMERR or SPPERR is "H".

Read status

Playback end

N

STOP command

Y

1st byte of AMODE command

CBUSYB ”H”

N

Y

2nd byte of AMODE command

* Speaker-Mode is set Power-Down.

CBUSYB ”H”

N

Y

ERCL command

* Err-bit and Err-port are cleared.

CBUSYB ”H”

N

Y

waiting for command

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1-Byte Command input flow of two-time command input mode

（applied to the PDWN,SLOOP,CLOOP,RDSTAT,OUTSTAT,and ERCL commands）

One-time command input

One-time ERCL command input

Two-time command input

Two-time ERCL command input

N

ERR ”L”

Y

N

ERR ”L”

N

CBUSYB ”H”

Y

CBUSYB ”H”

End

Y

One-time command input(Re-input)

Two-time command input(Re-input)

N

ERR ”L”

N

CBUSYB ”H”

Y

End

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1-Byte Command input flow of two-time command input mode

（STOP commands）

One-time command input

One-time ERCL command input

Two-time command input

Two-time ERCL command input

N

ERR ”L”

Y

N

ERR ”L”

N

BUSYB

“H”?

Y

CBUSYB

“H”?

End

Y

One-time ERCL command input

Two-time ERCL command input

N

ERR ”L”

N

BUSYB

“H”?

Y

End

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2-Byte Command input flow of two-time command input mode

（applied to the AMODE,AVOL,FAD,FADR,PLAY,MUON,CVOL, and SAFEcommands）

One-time command input (1Byte)

Two-time command input (1Byte)

One-time ERCL command input

Two-time ERCL command input

N

ERR ”L”

Y

ERR ”L”

N

CBUSYB ”H”

Y

N

CBUSYB ”H”

Y

One-time command input(1Byte)(Re-input)

Two-time command input(1Byte) (Re-input)

N

ERR ”L”

N

CBUSYB ”H”

Y

One-time command input (2Byte)

Two-time command input (2Byte)

N

ERR ”L”

One-time ERCLcommand input

Two-time ERCLcommand input

Y

N

CBUSYB ”H”

N

ERR ”L”

Y

End

Y

N

CBUSYB ”H”

Y

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Handling of the SG Pin

The SG pin is the signal ground pin for the built-in speaker amplifier. Connect a capacitor between this pin and

the analog ground so that this pin will not carry noise.

The recommended capacitance value is shown below; however, it is recommended that the user determine the

capacitance value after evaluation.

Always start playback after each output voltage is stabilized.

Recommended

capacitance value

SG

Remarks

The larger the connection capacitance, the longer the speaker

amplifier output pin (SPM and SPP) voltage stabilization time.

0.1 µF ±20%

Handling of the V_DDLPins

The V_DDLpin is the power supply pins for the internal circuits. Connect a capacitor between each of these pins

and the ground in order to prevent noise generation and power fluctuation.

The recommended capacitance value is shown below; however, it is recommended that the user determine the

capacitance value after evaluation.

Always start the next operation after each output voltage is stabilized.

Recommended

capacitance value

Remarks

The larger the connection capacitance, the longer the

stabilization time.

V_DDL

10 µF ±20%

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Power Supply Wiring

The power supplies of this LSI are divided into the following three:

• Digital power supply (DV_DD) and Digital ground(DGND)

• Speaker amplifier power supply (SPV_DD) and Speaker amplifier ground(SPGND)

• External ROM interface power supply(IO V_DD

)

As shown in the figure below, be sure to diverge the wiring of DV_DDand SPV_DDfrom the root of the same power

supply. DGND/SPGND is similar, too.

IOV_DDis sure to wire External ROM power supply.

3.3V ^*1

DV_DD

DGND

IOV_DD

SPV_DD

SPGND

5V

*1 : IOV_DDis sure to wire External ROM power supply.

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APPLICATION CIRCUIT

At using internal speaker amplifier (speaker output)

RESETB

CSB

MCU

SPM

SPP

SCK

SI

speaker

SO

CBUSYB

ERR

0.1µF

SG

STATUS

DIPH

0.1µF

AIN

TESTI1

FLW

IOV_DD

V_DDL

0.1uF

ECSB

ESCK

ESO

ESI

10uF

External

ROM

DV_DD

SPV_DD

10uF

0.1uF

15pF

5V

3.3V^*1

DGND

XT

4.096MHz

SPGND

XTB

15pF

*1IOV_DDis sure to wire External ROM power supply.

At using external speaker amplifier (line output)

RESETB

CSB

SCK

MCU

SPM

SPP

0.1µF

SP-AMP

SI

SO

speaker

CBUSYB

ERR

STATUS

DIPH

0.1µF

SG

AIN

TESTI1

FLW

IOV_DD

V_DDL

0.1uF

10uF

ECSB

ESCK

ESO

ESI

External

ROM

DV_DD

SPV_DD

10uF

0.1uF

15pF

5V

3.3V^*1

DGND

XT

4.096MHz

SPGND

XTB

15pF

*1IOV_DDis sure to wire External ROM power supply.

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RECOMMENDED CERAMIC OSCILLATION

Recommended ceramic resonators for oscillation and conditions are shown below for reference.

KYOCERA Corporation

Optimal load capacity

Freq [Hz]

Type

C1

C2

Rf

Rd Supply voltage Operating Temperature

[pF]

[pF] [Ohm] [Ohm]

Range [V]

Range [°C]

4.096M PBRV4.096MR50Y000

15(internal)

---

--

4.5 to 5.5

-40 to +125

MURATA Corporation

Optimal load capacity

Rd Supply voltage Operating Temperature

Freq [Hz]

Type

C1

C2

Rf

[pF]

[pF] [Ohm] [Ohm]

Range [V]

Range [°C]

4M

CSTCR4M00G55B-R0

CSTCR4M09G55B-R0

39(internal)

---

--

4.5 to 5.5

-40 to +125

4.096M

Circuit diagram

V_DD

DV_DD/SPV_DD

DGND/

SPGND

GND

XT XTB

C2

C1

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LIMITATION ON THE OPERATION TIME (PLAY-BACK TIME)

ML22594’s operating temperature is 105°C. But the average ambient temperature at 1W play-back (8ohm

drive) during 10 years in the reliability design is Ta=70°C. (max ( the package heat resistance θ

ja=24.6[°C/W]) )

When ML22594 operates 1W play-back(8ohm drive) consecutively, the product life changes by the package

temperature rise by the consumption. This limitation does not matter in the state that a speaker amplifier does not

play.

The factor to decide the operation time ( play-back time ) is the average ambient temperature( Ta ), play-back

Watts( at the speaker drive mode), the soldering area ratio*1, and so on. In addition, the limitation on the

operation time changes by the heat designs of the board.

PACKAGE HEAT RESISTANCE VALUE (REFERENCE VALUE)

The following table is the package heat resistance value θja (reference value).

This value changes the condition of the board (size, layer number, and so on)

The board

θja

The condition

JEDEC 4layers^*1

24.6[°C /W]

（W/L/t＝76.2/114.5/1.6（mm））

JEDEC 2layers^*2

No wind (0m/s)

the soldering area ratio*³：100%

31.2[°C /W]

（W/L/t＝76.2/114.5/1.6（mm））

*1 : The wiring density : 1st layer(Top) 60% / 2nd layer 100% / 3rd layer 100% / 4th layer(Bottom) 60%.

*2 : The wiring density : 1st layer(Top) 60% / 2nd layer(Bottom) 100%.

*3 : The soldering area ratio is the ratio that the heat sink area of ML22594 and a land pattern on the board are

soldered. 100% mean that the heat sink area of ML22594 is completely soldered to the land pattern on the board.

About the land pattern on the board, be sure to refer to the next clause (PACKAGE DIMENSIONS).

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PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in

storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name,

package name, pin number, package code and desired mounting conditions (reflow method, temperature and

times).

Notes for heat sink type Package

This LSI adopts a heat sink type package to raise a radiation of heat characteristic. Be sure to design the land

pattern corresponding to the heat sink area of the LSI on a board, and solder each other. The heat sink area of the

LSI solder open or GND on the board.

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REVISION HISTORY

Page

Document No.

Date

Description

Current

Edition

FEDL22594FULL-01

Sep. 19, 2012

–

51

55

11

18

34

35

68

2

Final edition 1.

Add EXRERR.

51

55

11

18

-

FEDL22594FULL-02

FEDL22594-03

Nov. 20, 2012

Apr. 24, 2013

Add External ROM error timing diagram.

Add tCB3.

Change Playback Stop Timing.

Add tPUPA3 timing diagram.

Add tPDA3 timing diagram.

Change Application Circuit.

Differences table correction.

Add Playback method.

FEDL22594-04

FEDL22594-05

Dec. 9, 2014

Mar. 8, 2015

-

68

2

-

3

Add instructions.

5,6

8

6,7

9

Add instructions to ”DC Characteristics".

Add instructions to “AC Characteristics".

Modify CPU Serial Interface Data Timing.

Modify Power-On Timing.

12

13

15

23

-

13

14

15

23

24

Modify Power Shut-down Timing.

Add t_INTC.

FEDL22594-06

Oct. 16, 2017

Add “To know the volume controls more”.

Modify “Playback Time and Memory

Capacity”.

25

34

42

25

34

42

Modify “When putting the speaker amplifier

into the power down state”.

Modify “PLAY Command Input Timing for

Continuous Playback”.

53

70

53

70

STATUS of OUTSTAT command is added.

Unit correction

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Page

Document No.

Date

Current

Edition

Description

4

Modify Block Diagram.

Modify External ROM Serial Interface Data

Timing.

14

-

14

Add Note on continuous playback and mixing

playback.

28

60

FEDL22594-07

Aug. 9, 2018

Add 1-Byte Command Input Flow (STOP

commands) charts.

-

Add 1-Byte Command input flow of two-time

command input mode （ STOP commands)

charts.

-

67

74

FEDL22594-08

Apr. 17, 2020

74

Change of the package

76/77

FEDL22594-08

ML22594-XXX

Notes

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,

semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent

personal injury or fire arising from failure, please take safety measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and

fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the

use of our Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided

only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken

into account when designing circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and

examples of application circuits for the Products. No license, expressly or implied, is granted hereby under

any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the

information contained in this document; therefore LAPIS Semiconductor shall have no responsibility

whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such

technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,

consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please

contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships,

trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment,

nuclear power control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance

with the recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this

document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS

Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such

information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the

RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office.

LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance

with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must

abide by the procedures and provisions stipulated in all applicable export laws and regulations, including

without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade

Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

77/77


型号：	ML22594
厂家：	ROHM
描述：	存储器外挂型存储
文件：	总78页 (文件大小：3432K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML22594 [ROHM]

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