ML22120 [ROHM]
ML22120是一款非常适合用于车辆声学警告系统（AVAS）和车外语音的语音合成LSI。该产品内置对车辆接近警告声等播放声音的调整功能。通过改变所播放声音的音高和音量，即可满足AVAS相关法规的要求，从而可以轻松实现车辆接近警告声。另外，还配有均衡器功能，可简化安装在车辆中之后和不同车型的声音调整。不仅如此，该产品还内置故障检测功能，可以检测出与微控制器之间的通信异常和外置振荡电路异常等问题，因此客户可以安心且安全地使用。;
| 型号： | ML22120 |
| 厂家： | 
ROHM |
| 描述： | ML22120是一款非常适合用于车辆声学警告系统（AVAS）和车外语音的语音合成LSI。该产品内置对车辆接近警告声等播放声音的调整功能。通过改变所播放声音的音高和音量，即可满足AVAS相关法规的要求，从而可以轻松实现车辆接近警告声。另外，还配有均衡器功能，可简化安装在车辆中之后和不同车型的声音调整。不仅如此，该产品还内置故障检测功能，可以检测出与微控制器之间的通信异常和外置振荡电路异常等问题，因此客户可以安心且安全地使用。 通信 语音合成 控制器 微控制器 |
| 文件： | 总122页 (文件大小：1550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL22120-01
Issue date: Mar 1, 2023
ML22120
Speech Synthesis LSI with pitch control function for Automotive
■ Overview
ML22120 is a speech synthesis LSI with a serial flash memory interface for sound data and compatible with the sound data
playback function (Sound Generator).
It has a Clock Synchronous Serial Interface and I2C interface (slave).
The pitch and volume can be changed dynamically by controlling the setting register.
It adopts a 16-bit D/A converter and low-pass filter which realize high-quality sound.
It has the 5Band equalizer as a sound quality effect processing.
The functions necessary for sound output are integrated into a single chip, so that sound functions can be realized simply by
adding this LSI and an external speaker amplifier.
In this data sheet, the sound data playback function is referred to as Sound Generator.
Serial
FLASH
CH0
Filter
MIX
Pitch Control
Pitch Control
Pitch Control
Pitch Control
Volume
Volume
Volume
Volume
LINE
AMP
16bit
DAC
CH1
CH2
CH3
Sound Generator
Host
MCU
SPI / I2C
5Band
EQ
Master
Volume
Lch
SAI
5Band
EQ
Rch
Application Circuit
FEDL22120-01
ML22120
■ Feature
● Sound Generator
Speech synthesis algorithm:
Maximum number of phrases: 64 Phrases
Flash memory capacity: Maximum 128Mbits
Sampling frequency (kHz)
Maximum sound production time (sec)
16bit Straight PCM
48.0
174
24.0
349
12.0
698
32.0
262
16.0
524
8.0
1048
● Sampling frequency: 48.0kHz/24.0kHz/12.0kHz，32.0kHz/16.0kHz/8.0kHz
● Playback function
Repeat function
Mixing-function:
4-channels
Volume adjustment function:
Volume setting for each channel -76.7dB to +25.5dB/0.1dB step (including MUTE)
Master volume setting for Lch/Rch -76.7dB to +25.5dB/0.1dB step (including MUTE)
With fade function
Pitch adjustment function:
4-channels
CH0/CH1:0.0625 times to 4 times (0.00390625 times step)
CH2/CH3:0.0625 times to 1 times (0.00390625 times step)
With fade function
● Serial audio interface (master)
PCM format:
16bit Straight PCM
Sampling frequency at transfer(gfs): 48.0/32.0kHz (not depend on the sampling frequency of the Sound
Generator)
Data length:
16bit
MCLK frequency:
BCLK frequency:
128/256/512gfs selectable
32gfs to 64gfs
LRCLK transfer mode/ frame synchronous transfer mode selectable
LRCLK forward/reverse selectable
1-bit delay ON/OFF selectable
MSB first/LSB first selectable
● 5Band equalizer
Band center frequency, Band width, and Gain can be set.
● Low-pass filter
● 16-bit D/A converter
● Line amplifier output:
● MCU interface:
● Master clock frequency:
● Power-supply voltage:
10kΩ driving
Clock Synchronous Serial Interface/I2C Interface (Slave)
4.096MHz, 4.000MHz
2.7V to 3.6V
● Power-supply voltage for a serial flash memory interface:
● Operating temperature range:
2.7V to 3.6V
-40 OC to +105 OC( +125 OC*1 ) *1 Key interlocking application
● Package:
32-pin TQFP (7mm x 7mm, 0.8mm pitch)
32-pin WQFN (5mm x 5mm, 0.5mm pitch)
24-pin WQFN (4mm x 4mm, 0.5mm pitch)
ML22120TB (32-pin TQFP)
● Ordered Part Name:
ML22120GD (32-pin WQFN) Under Development
ML22120GP (24-pin WQFN)
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■ Pin Configuration (TOP VIEW)
● ML22120TB
25
26
27
28
29
DGND
DVDD
16
15
14
13
12
11
SI/SDA
CSB/SCL
VDDL
(N.C.)
SG
LOUT
(N.C.)
RESETB
(N.C.)
(TOP VIEW)
TQFP32
STATUS2
STATUS1_MCLKO
BCLK
30
31
32
10
9
LRCLK
SAI_OUT
(N.C.) Unused pin
● ML22120GD
SI/SDA 25
DGND
DVDD
VDDL
16
15
14
13
12
11
26
27
28
29
CSB/SCL
(N.C.)
(TOP VIEW)
WQFN 32
STATUS2
(N.C.)
SG
STATUS1_MCLKO
LOUT
BCLK 30
31
32
10 (N.C.)
LRCLK
9
RESETB
SAI_OUT
(N.C.) Unused pin
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● ML22120GP
SI/SDA
CSB/SCL
19
20
21
22
23
24
DGND
DVDD
10 VDDL
12
11
(TOP VIEW)
WQFN 24
STATUS1_MCLKO
BCLK
9
8
7
SG
LRCLK
SAI_OUT
LOUT
RESETB
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■ Pin Description
Pin
Initial
Symbol
IOVDD
I/O Attribute
Description
32
pin
24
pin
value *1
Serial flash memory interface power supply pin.
Connect a bypass capacitor between this pin and the DGND pin.
Serial flash memory interface chip select output pin.
Output the "H" level during non-access and the "L" level during
access.
3
4
1
2
P
-
—
H
ERCSB
O
Negative
Setting the EROFF pin to "L" enables output.
Serial flash memory interface serial clock output pin.
Setting the EROFF pin to "L" enables output.
Serial flash memory interface serial data input pin.
Setting the EROFF pin to "L" enables input.
5
6
7
3
4
5
ERSCK
ERSI
O
I
-
-
-
L
L
L
A pull-down resistor is internally connected.
Serial flash memory interface serial data output pin.
Setting the EROFF pin to "L" enables output.
Pin to disable the serial flash memory interface.
When this bit is set to "L", the serial flash memory interface pin is
enabled. A pull-down resistor is internally connected.
Set this pin to "L" during playback operation using serial flash
ERSO
O
8
6
EROFF
I
Positive memory.
When this pin set to "H", the serial flash memory interface is in a
L
condition of high-impedance.
Set to "H" when rewriting by connecting the FLASH writer to ERCSB /
ERSCK / ERSI / ERSO.
Reset-input pin.
The LSI is initialized by the "L" level input. After a reset is input, all the
Negative circuits stop operating and enter the standby state.
At power-on, input an "L" level to this pin. After the power supply
voltage stabilizes, set this pin to an "H" level.
9
7
RESETB
I
—
11
12
8
9
LOUT
SG
O
O
-
Used exclusively for line amplifier output.
Reference voltage output pin for line amplifier.
Connect a capacitor between this pin and DGND pin.
1.5V regulator output pin.
L
L
-
Used as internal power supply.
Connect a capacitor between this pin and DGND pin as close as
possible.
14
10
VDDL
O
-
L
Digital power supply pin.
Connect a bypass capacitor between this pin and the DGND pin.
Digital ground pin.
15
11
12
DVDD
P
-
-
—
—
16
1,
DGND
G
2,
10,
13,
23,
24,
27
Unused pin.
Leave open.
-
N.C.
-
-
Hi-Z
*1 Initial value at reset input and standby. The pin whose IO is "I" indicates a fixed level from outside.
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Pin
Initial
Symbol
XT
I/O Attribute
Description
32
pin
24
pin
value *1
Crystal or ceramic resonator connection pin.
A feedback resistor of about 1MΩ is built in between the XT pin and
the XTB pin.
17
18
13
14
I
Negative To use an external clock, input from this pin. Delete the capacitor
when a crystal or ceramic resonator is connected.
When using a resonator, connect it as close as possible.
Leave it open when not in use.
L
Crystal or ceramic resonator connection pin.
When an external clock is used, leave it open and capacitor is not
Positive required when a crystal or ceramic resonator is connected.
When using a resonator, connect it as close as possible.
Leave it open when not in use.
XTB
O
H
Input pin for testing.
19
20
15
16
TEST0
I
Positive A pull-down resistor is internally connected.
Fix to the DGND.
L
L
Status output pin 0.
STATUS0
O
-
Set the OUTSTAT0_0 to 5 registers to select the output of various
statuses, playback status of each channel, and internal error status.
I
I
-
-
SCK: Synchronous serial interface clock input pin.
SAD0: I2C slave address select pin. Set the slave address by fixing it
to DVDD or DGND.
L
21
22
17
18
SCK/SAD0
SO/SAD1
—
SO: Synchronous serial interface data output pin.
When the status is read, the data is output in synchronization with
SCK.
O
-
Hi-Z
when the status is not read, this pin enters a high-impedance state.
SAD1: I2C slave address select pin. Set the slave address by fixing it
to DVDD or DGND.
I
I
-
-
—
L
SI: Synchronous serial interface data input pin.
Data is fetched in synchronization with SCK.
SDA: I2C slave serial data input/output pin.
An input / output pin used for setting the write mode / read mode,
writing the slave address, and writing / reading data.
When using an I2C, be sure to insert a pull-up resistor between DVDD
pin.
25
19
SI/SDA
IO
-
Hi-Z
Output: Nch MOS OPEN DRAIN output
Input: High-impedance input
CSB: Synchronous serial interface chip select pin.
I
Negative The SCK and SI inputs are accepted only when this pin is at the "L"
H
level.
26
28
29
20
-
CSB/SCL
STATUS2
SCL: I2C slave serial clock pin.
I
-
-
When using an I2C, be sure to insert a pull-up resistor between DVDD
pin.
Status output pin 2.
Set the OUTSTAT2 register to select internal error status.
Status output pin 1 or SAI master clock output pin.
When the MCLKSEL bit of the IFSEL register is set to "0", set the
OUTSTAT1_0 to 5 registers to select the output of various statuses,
playback status of each channel, and internal error status.
When the MCLKSEL bit of the IFSEL register is set to "1", SAI master
clock is output.
Hi-Z
L
O
STATUS1_
MCLKO
21
O
-
L
30
31
32
22
23
24
BCLK
LRCLK
SAI_OUT
O
O
O
-
-
-
SAI bit clock output pin.
SAI word clock output pin.
SAI bit data output pin. Output data at the falling edge of BCLK.
L
L
L
*1 Initial value at reset input and standby. The pin whose IO is "I" indicates a fixed level from outside.
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■ Termination of Unused Pins
This section explains how to terminate unused pins.
Symbol
Recommended pin termination
Connect to the DGND.
EROFF
TEST0
XT
XTB
LOUT
STATUS0
STATUS1_
MCLKO
STATUS2
BCLK
Leave open.
LRCLK
SAI_OUT
N.C.
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■ I/O Equivalent Circuit
Classifi
cation
A
Circuit
Overview
Attribute: Input
Power: DVDD
Function: CMOS inputs with pull-down
Applicable pin: TEST0
Attribute: Input
Power: IOVDD
Function: CMOS inputs with pull-down
Applicable pin: EROFF, ERSI
B
Attribute: Input
Power: DVDD
Function: CMOS inputs
Applicable pin: SCK/SAD0, RESETB
C
Attribute: Output
Power: DVDD
Function: CMOS outputs
Applicable pin: STATUS0, STATUS1_MCLKO,
STATUS2, LRCLK, BCLK, SAI_OUT
Attribute: Output
Power: IOVDD
Function: CMOS outputs
Applicable pin: ERCSB, ERSCK, ERSO
D
Attribute: Input/output
Power: DVDD
Function: CMOS inputs / outputs
Applicable pins: SO/SAD1
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Classifi
cation
E
Circuit
Overview
Attribute: input/output
Power: DVDD
Function: CMOS inputs / Nch Open Drain outputs
Applicable pins: CSB/SCL, SI/SDA
F
Attribute: Oscillator circuit
Power: DVDD
Function: 4.096M, 4.000M oscillation
Applicable pins: XT, XTB
XTB
XT
G
Attribute: Analog
Power: DVDD
Function: Sound output
Applicable pin: LOUT
H
Attribute: Analog
Power: DVDD
Function: Line amplifier reference voltage output
Applicable pins: SG
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■ Electrical characteristics
● Absolute maximum rating
DGND=0V, Ta=25°C
Rating Unit
Parameter
Symbol
DVDD
IOVDD
VIN1
Condition
Power supply voltage 1
—
-0.3 to +4.6
V
Input voltage 1
Input voltage 2
—
-0.3 to DVDD+0.3
-0.3 to IOVDD+0.3
V
V
VIN2
—
When the LSI is mounted on
JEDEC 2-layer board.
Applies to pins other than VDDL
pin.
Allowable loss
PD
1000
10
mW
mA
Output short-circuit current
Storage temperature
IOS
Applies to the VDDL pin.
—
50
mA
°C
TSTG
-55 to +150
● Recommended operating conditions
DGND=0V
Unit
Parameter
Symbol
Condition
Range
2.7 to 3.6
DVDD
,
DVDD
IOVDD
IOVDD
,
—
—
—
V
Power-supply voltage
Operating temperature
Top
fOSC
-40 to +105 ( +125*1 )
°C
Min.
Typ.
4.096
4.000
Max.
Master clock frequency
MHz
Typ
-5%
Typ
+5%
*1 Key interlocking application
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● DC characteristics
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Applicable pin
CSB/SCL
SCK/SAD0
SI/SDA
Min.
Typ.*1
Max.
Unit
"H" input voltage 1
"H" input voltage 2
"L" input voltage 1
VIH1
—
(SO)/SAD1
XT
0.8×DVDD
—
DVDD
V
RESETB
TEST0
EROFF
VIH2
—
—
0.8×IOVDD
—
—
IOVDD
V
V
ERSI
CSB/SCL
SCK/SAD0
SI/SDA
VIL1
(SO)/SAD1
XT
0
0.2×DVDD
RESETB
TEST0
EROFF
"L" input voltage 2
"H" output voltage 1
VIL2
—
0
—
—
0.2×IOVDD
—
V
V
ERSI
VOH1
IOH = -50µA
XTB
DVDD-0.4
LRCLK
BCLK
SAI_OUT
SO/(SAD1)
STATUS0
STATUS1_MCLKO
STATUS2
ERCSB
"H" output voltage 2
VOH2
IOH = -1mA
DVDD-0.4
—
—
V
"H" output voltage 3
"L" output voltage 1
VOH3
VOL1
IOH = -1mA
IOL = 50µA
ERSCK
IOVDD-0.4
—
—
—
—
V
V
ERSO
XTB
0.4
LRCLK
BCLK
SAI_OUT
SO/(SAD1)
STATUS0
STATUS1_MCLKO
STATUS2
ERCSB
"L" output voltage 2
VOL2
IOL = 2mA
—
—
0.4
V
V
"L" output voltage 3
"L" output voltage 4
VOL3
IOL = 2mA
IOL = 3mA
ERSCK
—
—
0.4
ERSO
(SI)/SDA
(CSB)/SCL
VOL4
IOOH1
IOOL1
IOOH2
IOOL2
—
—
—
—
—
—
—
0.4
10
—
V
VOH=DVDD
(in high-impedance state)
VOL=DGND
(in high-impedance state)
VOH=IOVDD
Output leakage
current 1
µA
µA
µA
µA
(SI)/SDA
(CSB)/SCL
SO/(SAD1)
–10
—
Output leakage
current 2
10
—
ERCSB
ERSCK
ERSO
(in high-impedance state)
VOL=DGND
–10
(in high-impedance state)
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DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
IIH1
Condition
Applicable pin
XT
Min.
0.8
Typ.*1
5.0
Max.
20
Unit
µA
"H" input current 1
VIH = DVDD
CSB/SCL
SCK/SAD0
SI/SDA
"H" input current 2
IIH2
VIH = DVDD
—
—
10
µA
(SO)/SAD1
RESETB
TEST0
"H" input current 3
"H" input current 4
"H" input current 5
"L" input current 1
IIH3
IIH4
IIH5
IIL1
VIH = DVDD
VIH = IOVDD
VIH = IOVDD
VIL = DGND
20
20
2
300
300
40
700
700
300
–0.8
µA
µA
µA
µA
EROFF
ERSI
XT
–20
–5.0
CSB/SCL
SCK/SAD0
SI/SDA
"L" input current 2
IIL2
VIL = DGND
(SO)/SAD1
RESETB
EROFF
–10
—
—
µA
TEST0
f
OSC=4.096MHz
During playback
Current
consumption
fs=48kHz, f=1kHz,
(4ch simultaneous)
operating the line
amplifier output
IDDO
—
—
6*2
15*2
mA
1*2
1*2
10.0*2
30.0*2
µA
µA
Standby
Current
Ta=-40 to +55°C
—
—
—
—
IDDS
consumption*3
Ta=-40 to +125°C
*1 Typ. : DVDD=IOVDD=3.0V,DGND=0 V,Ta=25°C
*2 Total values of the DVDD pin and IOVDD pin
*3 RESETB pin is at the “L” level.
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● Analog Part Characteristics
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
RC4MHz
Symbol
Frc
Condition
Min.
3.68
Typ.
Max.
4.51
Unit
—
4.096
MHz
When 1/2DVDD ± 1 mA is
applied
Line amplifier output resistance
RLA1
RLA2
VAO
—
10
—
—
—
300
—
Ω
kΩ
V
Line amplifier
output-load-resistance
Line amplifier Out put Voltage
Range
For DGND
No output load
DVDD /6
DVDD×5/6
0.95x
DVDD /2
57
1.05x
DVDD /2
135
SG pin output voltage
VSG
RSG
—
—
DVDD /2
96
V
SG pin output resistance
kΩ
13/122
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● AC characteristic
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
Master clock duty cycle
RESETB input pulse width
Symbol
fduty
Condition
Min.
40
Typ.
50
Max.
60
Unit
%
—
—
tRST
10
—
—
μs
Reset noise rejection pulse width tNRST
RESETB pin
—
—
0.1
μs
Initialization time after reset
release
tPRC
—
—
—
5
ms
4.096MHz external clock input
POP="H"
OUT_EN="L"→"H"
4.096MHz external clock input
POP="L"
OUT_EN="L"→"H"
4.096MHz external clock input
POP="H"
OUT_EN="H"→"L"
4.096MHz external clock input
POP="L"
Line amplifier power up time
tPUP1
—
73
77
ms
(with Pop Noise Suppression)
Line amplifier power up time
tPUP0
—
—
—
33
37
ms
ms
ms
(without Pop Noise Suppression)
Line amplifier power down time
tPD1
144
104
148
108
(with Pop Noise Suppression)
Line amplifier power down time
tPD0
(without Pop Noise Suppression)
OUT_EN="H"→"L"
fOSC = 4.096MHz
Playback start time
Fade start time
tPSTA
tFAD
—
—
—
—
—
—
400
400
5
μs
μs
fOSC = 4.096MHz
Playback stop time
tPSTP
fOSC = 4.096MHz
ms
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● AC Characteristics (Clock Synchronous Serial Interface)
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
SCK setup time from CSB falling edge
SCK input enable time from CSB falling edge
SCK hold time from CSB rising edge
Data floating time from CSB rising edge
Data setup time from SCK
Symbol
tSCKS
tESCK
tCSH
Condition
Min.
100
100
100
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
tDOZ
RL=3KΩ
—
100
—
tDIS
50
Data hold time from SCK
tDIH
—
50
—
Data output delay time from SCK
SCK "H" level pulse width
tDOD
—
—
90
—
tSCKH
tSCKL
—
100
100
SCK "L" level pulse width
—
—
<When rewriting the flash memory using the clock synchronous serial interface>
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
SCK setup time from CSB falling edge
SCK input enable time from CSB falling edge
SCK hold time from CSB rising edge
Data floating time from CSB rising edge
Data setup time from SCK
Symbol
tSCKS
tESCK
tCSH
Condition
Min.
125
125
125
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
tDOZ
RL=3KΩ
—
125
—
tDIS
50
Data hold time from SCK
tDIH
—
50
—
Data output delay time from SCK
SCK "H" level pulse width
tDOD
—
—
110
—
tSCKH
tSCKL
—
125
125
SCK "L" level pulse width
—
—
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● AC Characteristics (I2C Interface)
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
tSCL
Min
0
Max.
400
—
Unit
kHz
μs
SCL clock frequency
SCL hold time (start/restart condition)
SCL clock "L" level time
SCL clock "H" level time
SCL setup time (restart condition)
SDA hold time
tHD;STA
tLOW
0.6
1.3
0.6
0.6
0
—
μs
tHIGH
—
μs
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
—
μs
—
μs
SDA setup time
0.1
0.6
1.3
—
—
μs
SDA setup time (stop condition)
Bus free time
—
μs
—
μs
Capacitive load on each bus line
Cb
400
pF
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● AC Characteristics (SAI Interface (Master))
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
SAI_BCLK period
Symbol
Condition
—
Min.
32gfs
146
146
—
Typ.
—
Max.
64gfs
—
Unit
Hz
ns
tC_BCLK
SAI_BCLK "H" period
SAI_BCLK "L" period
SAI_LRCLK delay time
SAI_SAIOUT delay time
tHW_BCLK
tLW_BCLK
tD_LRCLK
tD_SAIOUT
—
—
—
—
—
—
—
ns
—
20
ns
—
—
20
ns
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● AC Characteristics (Flash Memory Interface)
DVDD=IOVDD=2.7 to 3.6V, DGND=0V, Ta=-40 to +125°C, Load capacitance of output pin =15pF(max.)
Parameter
ERSCK enable time from ERCSB falling edge
ERSCK hold time from ERCSB rising edge
Data setup time from ERSCK rising edge
Data hold time from ERSCK rising edge
Data delay time from ERSCK falling edge
ERSCK frequency
Symbol
tECSS
Condition
Min.
50
Typ.
—
Max.
—
Unit
ns
—
—
—
—
—
—
—
—
tECSH
tEDIS
50
—
—
ns
10
—
—
ns
tEDIH
10
—
—
ns
tEDOD
tESCKF
tESCKH
tESCKL
—
—
5
ns
1.228
26
16.384
—
17.20
—
MHz
ns
ERSCK "H" level pulse width
ERSCK "L" level pulse width
26
—
—
ns
ERCSB/ERSCK/ERSO delay time from EROFF rising
edge
ERCSB/ERSCK/ERSO delay time from EROFF falling
edge
tEFLH
tEFHL
—
—
—
—
—
—
1
1
ms
ms
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■ Block diagram
The block diagram is shown below.
XTB XT
MCU
Interface
CSB/SCL
Oscillation
SCK/SAD0
BUS
Controller
OSC 4.096MHz
RC 4.096MHz
SI/SDA
PLL
SO/SAD1
DATA BUS
Pitch Control
(4ch)
STATUS0
STATUS2
STATUS1
STATUS1_MCLKO
Memory
Address
Controller
Sound
Generator
(4ch)
MCLKO
RESETB
TEST0
Channel Volume
(4ch)
ERCSB
Serial
Flash Memory
Interface
ERSCK
ERSI
Digital Mixing
(4ch)
ERSO
EROFF
IOVDD
LPF
DVDD
5Band
Equaliser
(2ch)
DGND
VDDL
Serial
Audio
Interface
Master Volume
（Lch/Rch）
LRCLK
BCLK
SAI_OUT
16bit DAC
LINE AMP
LOUT
SG
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■ Function description
● Clock Synchronous Serial Interface
Various registers are written and read by the CSB, SCK, SI, SO pins.
For data inputting, after "L" level is input to the CSB pin, data is input to the SI pin in MSB first in synchronization with the
input clock signal of the SCK pin. The SI pin data is loaded into the LSI in synchronization with the SCK pin clock, and the
input data is determined by the SCK pin clock of the eighth pulse.
Write access and read access to the register can be selected according to the MSB data when each register address is set.
When the MSB of the address data is set to the “L” level, write access is performed, and the SI pin data is taken into the LSI
as write data in synchronization with the SCK pin clock. If the MSB of the address data is set to “H” level, read access is
performed and the data is output from the SO pin in synchronization with the SCK pin clock.
The address is automatically incremented while the CSB is at the "L" level, and data can be written and read continuously.
The selection of the rising or falling edge of the SCK pin clock depends on the state of the SCK pin at the falling edge of the
CSB pin.
When the SCK pin is "H" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the rising edge of the
SCK pin clock, and the status signal is output from the SO pin on the falling edge of the SCK pin clock.
When the SCK pin is "L" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the falling edge of the
SCK pin clock, and the status signal is output from the SO pin on the rising edge of the SCK pin clock.
The serial interface can be returned to the initial state by setting the CSB pin to "H" level.
When the CSB pin is “H” level or when read data isn’t output, the SO pin is in a high impedance state.
Data input timing： SCK rising edge operation
(When the SCK is "H" at the falling edge of the CSB)
CSB
SCK
D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
SI
Data input timing： SCK falling edge operation
(When the SCK is "L" at the falling edge of the CSB)
CSB
SCK
D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
SI
Data output timing： SCK falling edge operation
(When the SCK is "H" at the falling edge of the CSB)
CSB
SCK
D7 D6 D5 D4 D3 D2 D1 D0
SO
(MSB)
(LSB)
Data output timing： SCK rising edge operation
(When the SCK is "L" at the falling edge of the CSB)
CSB
SCK
D7 D6 D5 D4 D3 D2 D1
SO
D0
(LSB)
(MSB)
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One-time input mode
•
Timing chart when writing data
CSB
SCK
W A6
A5 A4 A3 A2 A1 A0 D7 D6D5 D4 D3D2 D1 D0D7 D6 D5D4 D3 D2D1 D0 D7 D6
D2 D1 D0
SI
Register Address
1st write data
2nd write data
W: Read/Write flag
Last write data
3rd write data
Write:“0”
•
Timing chart when reading data
CSB
SCK
R A6 A5 A4 A3 A2A1 A0
SI
Register Address
R: Read/Write flag
Read:“1”
D7 D6D5 D4 D3D2 D1 D0D7 D6 D5D4 D3 D2D1 D0 D7 D6
D2 D1 D0
SO
1st read data
2nd read data
3rd read data Last read data
Two-times input mode
•Timing chart when writing data
CSB
SCK
SI
W A6
A5 A4 A3 A2 A1 A0 W A6 A5 A4 A3 A2 A1 A0D7 D6 D5D4 D3 D2D1 D0 D7 D6
D2 D1 D0
Register Address
Register Address
1st write data
1st write data
W: Read/Write flag
Write:“0”
•
Timing chart when reading data
CSB
SCK
R A6
R A6 A5 A4 A3 A2A1 A0
A5A4 A3 A2A1 A0
Register Address
SI
Register Address
R: Read/Write flag
Read:“1”
D7 D6D5 D4 D3D2 D1 D0D7 D6
D2D1 D0
SO
1st read data
1st read data
In the two-times input mode, if two-times input error is detected when reading a register, read data "1" is output.
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● I2C Interface (Slave)
This serial interface conforms to the I2C bus specifications. It supports Fast modes and can transmit and receive data at
400kbit/s. The SCL and SDA pins are used to write various register and to read the status. The slave addresses are set by the
SAD 0 to 1 pins.
When I2C is used, be sure to connect a pull-up resistor between SCL and SDA pins and DVDD pin.
In the communication flow between the master and this device (slave) on the I2C bus, after the start condition is set, the slave
address (upper 3 bits of the slave address are set by the SAD0 to 1 pins) is entered in the first 7 bits, the data direction is
determined in the 8th bit (when the 8th bit is "0", data is written from the master, and data is read from the master when "1")
and communication is performed in byte units thereafter. At this time, acknowledgment is required for each byte.
The reception operation supports auto-increment transfer and random access transfer, and the transmission operation
supports auto-increment operation. Use the I2C access mode selection(I2CSEL) register to set auto-increment transfer and
random access transfer. The flow of write operation and read operation is shown below.
One-time input mode
・ Write operation (auto-increment transfer)
S
SA[6:0]
W
A
RA[7:0]
A
WD[7:0]
WD[7:0]
A
A
WD[7:0]
RA[7:0]
A
A
WD[7:0]
WD[7:0]
P
・ Write operation (random access transfer)
SA[6:0] RA[7:0]
S
W
A
A
P
・ Read operation (auto-increment transfer)
SA[6:0] RA[7:0]
S
W
A
A
Sr
SA[6:0]
R
A
RD1[7:0]
A
RD2[7:0] ~A
P
Dummy Write
Current address read
S:
Start condition
Slave address
Read/Write flag Write=“0”
Acknowledge
SA[6:0]:
W:
A:
RA[7:0]:
WD[7:0]:
P:
Register address in this LSI
Write data
Stop condition
Sr:
R:
Restart condition
Read/Write flag Read=“1”
RD1,2[7:0]: Read data
~A:
P:
Not-Acknowledge
Stop condition
From master to slave
From slave to master
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Two-times input mode
・ Write operation (random access transfer)
S
SA[6:0]
W
A
RA[7:0]
A
RA[7:0]
A
WD1[7:0]
A
R
WD1[7:0]
P
・ Read operation (auto-increment transfer)
SA[6:0] RA[7:0] RA[7:0]
S
W
A
A
A
Sr SA[6:0]
A
RD1[7:0]
A
RD1[7:0] ~A
P
Dummy Write
Current address read
S:
Start condition
Slave address
Read/Write flag Write=“0”
Acknowledge
SA[6:0]:
W:
A:
RA[7:0]:
WD[7:0]:
P:
Register address in this LSI
Write data
Stop condition
Sr:
R:
RD1[7:0]:
Restart condition
Read/Write flag Read=“1”
Read data
~A:
P:
Not-Acknowledge
Stop condition
From master to slave
From slave to master
The slave address can be set as follows using the SAD1 to SAD0 pin.
Highest
SAD1 SAD0 Lower 4 bits
Slave address
100_0101
101_0101
110_0101
111_0101
1
1
1
1
0
0
1
1
0
1
0
1
0101
0101
0101
0101
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● SAI (Serial Audio Interface)
Various serial data formats are supported by a combination of register settings.
A WSLO, DLYO and FMTO are used to represent the supported formats.
For WSLO, DLYO and FMTO, refer to the " SAITCON register" in the "Registers" chapter.
<DLYO=“0”，FMTO=“0”，ISSCKO=“0”>
LRCLK
Right
Left
Left
Right
Right
（WSLh="1"）
LRCLK
（WSLO="0"）
Right
1
2
3 …………… 14 15 16
1
2
3 …………… 14 15 16 …………
3SB
3SB
MSB 2SB
MSB 2SB
14SB
MSB 2SB
3SB
LSB
LSB
15SB
15SB
14SB
SAI_OUT
BCLK
<DLYO=“0”，FMTO=“0”，ISSCKO=“1”>
LRCLK
WSLh="1"）
Left
Left
Right
Right
Right
（
LRCLK
（WSLO="0"）
Right
1
2
3 …………… 16 …………
1
2
3 …………… 16 …………
3SB
3SB
3SB
MSB 2SB
MSB 2SB
MSB 2SB
LSB
LSB
SAI_OUT
BCLK
<DLYO=“1”, FMTO=“0”，ISSCKO=“1”>
LRCLK
WSLh="1"）
（
Right
Right
Right
Left
Left
LRCLK
（WSLO="0"）
Right
1
2
3 …………… 16 …………
1
2
3 …………… 16 …………
3SB
3SB
3SB
MSB 2SB
MSB 2SB
MSB 2SB
LSB
LSB
SAI_OUT
BCLK
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<DLYO=“0”，FMTO=“1”，ISSCKO=“1”>
In frame synchronous transfer mode, Rch data follows immediately after Lch data.
LRCLK
Left
2
Right
2
Left
1
3 …………… 16
3SB
1
3
……………16…………
3SB
3SB
MSB 2SB
MSB 2SB
MSB 2SB
LSB
LSB
SAI_OUT
BCLK
<DLYO=“1”，FMTO=“1”，ISSCKO=“1”>
In frame synchronous transfer mode, Rch data follows immediately after Lch data.
LRCLK
Right
Left
Left
1
2
3 …………… 16
3SB
1
2
3
……………16…………
3SB
3SB
MSB 2SB
MSB 2SB
MSB 2SB
SAI_OUT
BCLK
LSB
LSB
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● Volume settings
For the SoundGenerator volume, set volume control independently / volume control linked to CH0 (initial value: volume
control independently) of each channel by the VOLCON_SD register. Set the volume of each channel by the
VOL_SD_CHn_L/H(n = 0 to 3) registers.
For the volume after mixing, set volume control independently / volume control linked to Lch (initial value: volume control
independently) by the LRSEL register. The volume after mixing can be set by the VOL_MASTL_L/H register and
VOL_MASTR_L/H register.
Channel0(CH0)
Channel1(CH1)
Lch/LOUT
Rch
VOL_SD_CH0_L/H
VOL_MASTL_L/H
VOL_SD_CH0_L/H
VOL_SD_CH1_L/H
VOL_MASTL_L/H
VOL_MASTR_L/H
1
0
1
0
Channel2(CH2)
Channel3(CH3)
VOL_SD_CH0_L/H
VOL_SD_CH2_L/H
1
0
LRSEL
control independently /
control linked to Lch
VOL_SD_CH0_L/H
VOL_SD_CH3_L/H
1
0
VOLFADE_CON
VOLFADE_STEP
VOLCON_SD
control independently /
control linked to CH0
Fade control
VOL_MASTL_L/H
VOL_MASTR_L/H
VOL_SD_CHn_L/H
Volume setting
Volume setting
The combination of volume control for each channel is as follows.
―: Apply VOL_SD_CHn_L / H (volume control independently)
レ: Apply VOL_SD_CH0_L / H (volume control linked to CH0)
VOLCON_SD register
Volume control
CH2
VOLEN_SD_
CHn bit(n=1 to 3)
CH3
CH1
000(Initial value)
―
―
―
―
レ
レ
レ
レ
―
―
レ
レ
―
―
レ
レ
―
レ
―
レ
―
レ
―
レ
001
010
011
100
101
110
111
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Furthermore, by enabling fade when changing the volume in the VOLFADE_CON register, the volume transition time can be
adjusted in the fade step set in the VOLFADE_STEP register. The volume changes every 0.1 dB.
Volume fade is effective when changing the volume of each channel using the VOL_SD_CHn_L/H(n = 0 to 3) registers, or
when changing the VOL_MASTL_L/H register and VOL_MASTR_L/H register.
＜When changing the volume of each channel in the VOL_SD_CHn_L/H(n = 0 to 3) registers＞
・ When playing sound code data of fs = 24kHz
fs:24kHz（41.67us）
Fade period（0.125×0.4×10＝0.5ms）
0x2FC（-0.4dB）
0x300
VOL_SD_CHn_L/H register
0dB
VOLFADE_STEP register
Volume of CHn
0x00（volume fade step 0.125[ms]）
-0.3dB
-0.4dB
-0.2dB
-0.1dB
0dB
0dB
Waveform of CHn
The volume transitions according to the sampling frequency (fs). If sound code data of different fs is being played at the same
time, the volume transition time will be different. For the volume transition time, refer "VOLFADE_STEP register" in the
"Registers" chapter.
＜When changing the volume by the VOL_MASTL_L/H register and VOL_MASTR_L/H register＞
・GFS bit = 0 (OUTMODE register).
fs:48kHz（20.83us）
Fade period（0.0625×0.4×10＝0.25ms）
0x2FC（-0.4dB）
0x300
VOL_MASTL_L/H register
0dB
VOLFADE_STEP register
Volume of Lch
0x00（volume fade step 0.0625[ms]）
-0.3dB
-0.4dB
-0.2dB
-0.1dB
0dB
0dB
Waveform of Lch
The volume transitions at 48kHz or 32kHz depending on the GFS bit of the OUTMODE register. For the volume transition
time, refer "VOLFADE_STEP register" in the "Registers" chapter.
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● Pitch settings
SoundGenerator can play while changing the pitch (playback speed).
The pitch magnification of CH 0 to 1 can be set from 0.0625 times to 3.9960938 times in 0.00390625 times steps.
The pitch magnification of CH 2 to 3 can be set from 0.0625 times to 1 time in 0.00390625 times steps.
For the pitch of the SoundGenerator, set pitch control independently / pitch control linked to CH0 (initial value:pitch
control independently) by the PITCHCON_SD register.
The combinations of pitch for each channel are as follows.
―: Apply PIT_SD_CH1_L / H (pitch control independently)
レ: Apply PIT_SD_CH0_L / H (pitch control linked to CH0)
PITCHCON_SD register
Pitch control
PITCHEN_SD_CH1 bit
CH1
―
0
1
レ
Furthermore, by enabling fade when changing the pitch in the PITFADE_CON register, the pitch can be adjusted step by step
in the pitch step set in the PITFADE_STEP register.
fs:24kHz（41.67us）
Fade period（0.125×4＝0.5ms）
0x104（1.015625 times）
0x100
PIT_SD_CHn_L/H register
1 times
PITFADE_STEP register
Pitch of CHn
0x00（pitch fade step 0.125[ms]）
0x103
0x104
0x102
0x101
0x100
0x100
Waveform of CHn
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● Memory allocation and creating sound data
The sound code data stored in the serial flash memory consists of sound (i.e., phrase) control area, test area, and sound area.
The sound control area manages the sound data in the Memory. It contains data for controlling sound data for 64 phrases.
The sound area contains actual waveform data.
The Sound data is created using a dedicated tool (Speech LSI Utility).
Configuration of Serial Flash Memory Data (128Mbits)
0x00000
Test area
0x0007F
0x00080
Sound control area
0x0207F
0x02080
Sound area
0xFFFFFF
● Playback time and memory capacity
The playback time depends on memory capacity and sampling frequency. The relationship is shown below.
1.024 × (Memory Capacity (kbit)-65)
(sec)
Playback Time =
Sampling frequency (kHz) × bit length
When sound data with a sampling frequency of 48 kHz is registered in the 4Mbit serial flash memory, the playback time will
be approximately 5.37 seconds.
1.024 × (4096(kbit)- 65)
Playback Time =
≒ 5.37(sec)
48 (kHz) × 16 (bit)
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● Waveform clamp precautions for mixing
When mixing, the clamp may be generated as shown in the figure below due to the calculation of the synthesis. If the clamp
is known to be generated in advance, adjust the volume of each channel with the volume control register.
For details on volume control registers, refer the chapter "Registers".
DVDD
5/6DVDD
CH 0 waveform
1/6DVDD
DGND
DVDD
5/6DVDD
CH 1 waveform
1/6DVDD
DGND
DVDD
5/6DVDD
For CH 0 and 1
Mixing waveform
1/6DVDD
DGND
If the result of mixing CH 0 and 1 exceeds from the 1/6DVDD to 5/6DVDD level (as
indicated by the broken line), the sound quality may be reduced by clamping.
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● 5Band equalizer
The 5Band equalizer consists of a second-order IIR type Band Pass Filter. It is equipped with Lch (EQL) and Rch (EQR). The
center frequency and band width of each band can be set arbitrarily. ON / OFF can be set by setting the EQLCON register and
EQRCON register. The settings are as follows.
A0 = (1-tanπfb / fs) / (1 + tanπfb / fs)
A1 = (-2cos2πf0 / fs) / (1 + tanπfb / fs)
f0: Center frequency of the band [Hz]
fb: -3dB bandwidth [Hz]
fs: sampling frequency [Hz]
Gain×5ch
Coefficient(A0, A1)×5ch
Output
Input
Band0-IIR
Band1-IIR
Band2-IIR
Band3-IIR
Band4-IIR
For the actual register value, multiply the result of the above formula by 214 and use the integer value rounded to the nearest
whole number.
For details on Coefficient (A0, A1) and Gain, refer "Equalizer related registers" in the "Registers" chapter.
The equalizer can be adjusted using the dedicated tool (Speech LSI Utility). Set the value generated by the Speech LSI Utility
in the "Equalizer related registers".
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● Error detection function
It has a built-in error detection function, and the presence or absence of error detection can be read from the ERROR register.
The presence or absence of error detection can be output to the STATUS0 pin (set by the OUTSTAT0_0 to 5 registers), the
STATUS1_MCLKO pin (set by the OUTSTAT1_0 to 5 registers), and the STATUS2 pin (set by the OUTSTAT2 register).
For details on the ERROR register, OUTSTAT0_0 to 5 registers, OUTSTAT1_0 to 5 registers, OUTSTAT2 register, refer
the chapter "Registers".
The error detection is shown below.
Detects the stop of clock input from a crystal resonator or ceramic resonator.
When oscillation stop is detected with the XTSEL bit of the CLKSEL register set to “1”, the CLKERR bit becomes “1”. At
the same time, the clock backup function starts and automatically switches to the RC oscillation circuit (4.096MHz).
The CLKERR bit can be read from the ERROR register. The CLKERR bit can be cleared by writing to the ERROR
register. However, if the oscillation stop continues, the CLKERR bit continues to be “1”.
ERROR
Write
ERROR
Write
Register control
CLKSEL
ERROR
Read
ERROR
Read
XTSEL bit
XT pin
XTB pin
Oscillation stopped state
Normal oscillation state Oscillation stopped state
Crystal or
Normal oscillation state
Crystal or
Ceramic resonator
RC oscillation
RC oscillation
Ceramic resonator
Internal clock
CLKERR bit
For details on the ERROR register and CLKSEL register, refer the chapter "Registers".
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Flash memory error detection
When the RESETB pin is set to the “L” → “H” level, the flash memory is read during the internal reset process. If an error
is detected in the read data of the flash memory, the ROMERR bit becomes "1". In this case, initialize this LSI by resetting
with the RESETB pin.
The ROMERR bit can be read from the ERROR register. The ROMERR bit is not cleared even if writing to the ERROR
register.
ERROR
Write
ERROR
Write
Register control
RESETB pin
ERROR
Read
ERROR
Read
Flash memory error
Flash memory normal
Flash memory
Status
Internal reset
process
Internal reset
process
Waiting
Waiting
standby
standby
ROMERR bit
For details on the ERROR register, refer the chapter "Registers".
Two-times input error detection
In order to prevent malfunction due to noise of the serial interface pin, it is equipped with a function to input address and data
twice each. Setting the TWSEL bit of the IFSEL register to “1” shifts to the two-times input mode.
In the two-times input mode, the address and data is input two-times in succession, and it is valid only when the input data
matches. If a mismatch occurs during the second data input after the first data input, the TWERR bit is set to "1", and the
address or data entered is ignored.
The TWERR bit can be read from the ERROR register. The TWERR bit can be cleared by writing to the ERROR register.
Register control
ADR
DATA
ADR
ADR
DATA1 DATA2
ADR
ADR
DATA1 DATA1
IFSEL
Arbitrary register
ERROR register
TWSEL bit
Judgment timing
0xNN
Not rewritten because DATA1 and DATA2 not match
Arbitrary register
TWERR bit
For details on the ERROR register and IFSEL register, refer the chapter "Registers".
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● Serial flash memory rewrite function
The serial flash memory can be rewritten in the following two ways.
SOUND LSI
EROFF
Serial flash memory
①MCU Interface
②Serial flash memory Interface
CSB
SCK
SI
CSB
SCK
SI
ERCSB
ERSCK
ERSO
ERSI
SO
SO
Flash memory writer
etc.
①
Rewrite using the clock synchronous serial interface of the MCU interface
By using the CSB, SCK, SI and SO pins, which are clock synchronous serial interfaces of the MCU interface
the serial flash memory can be rewritten. When the protect code written in the FLS_ACCS register matches the information
stored in the flash memory, direct access to the serial flash memory is enabled from the CSB, SCK, SI and SO pins.
Serial flash memory
Release standby
FLS_ACCS register
Direct access
RESETB
EROFF
“L”
Protect code
Address
CSB
SCK
SI
STATUS0
Status
Internal reset
process
Standby
Waiting
Serial flash memory access
For details on the FLS_ACCS register, refer the chapter "Registers".
②
Rewrite using serial flash memory interface without this LSI
The serial flash memory can be rewritten using the ERCSB, ERSCK, ERSI and ERSO pins that is the serial flash memory
interface.
When the EROFF pin set to "H", the serial flash memory can be rewritten using the ERCSB, ERSCK, ERSI and ERSO
pins without this LSI. ( ERCSB, ERSCK and ERSO pins are in a condition of high-impedance. )
VIH
EROFF
VIL
tEFLH
VOH
Hi-Z
ERCSB
VOL
VOH
Hi-Z
ERSCK
VOL
VOH
Hi-Z
ERSO
VOL
Output Status
Hi-Z Status
Status
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■ Timing chart
● Common
Power-on timing
DVDD
90%
IOVDD
RESETB VIH
tRST
VIL
VDDL
Oscillation
stopped
RC Oscillation
(internal)
Oscillating
tPRC
STATUS0
LOUT
GND
Internal reset
process
Status
Standby
Waiting
Power down
When turning on the power, enter "L" in the RESETB pin.
While the RESETB pin is at L level, it is in standby mode.
Start up in the order of DVDD and IOVDD.The DVDD and IOVDD can also start up at the same time.
After the reset is released (RESETB is at L → H level), it goes through internal reset processing and becomes waiting status
(oscillating).
Access the register after tPRC has elapsed or after the STATUS0 pin has become “H”.
Be sure to enter "L" at the RESETB pin when the DVDD is below the (recommended) operating voltage range.
Power-off timing
DVDD
IOVDD
RESETB VIH
tRST
VIL
VDDL
RC Oscillation
(internal)
Oscillation
stopped
STATUS0
GND
LOUT
Status
Waiting
Standby
Power down
When turning off the power, enter "L" in the RESETB pin.
Shut down in the order of IOVDD and DVDD. The DVDD and IOVDD can also shut down at the same time.
Be sure to enter "L" at the RESETB pin when the DVDD is below the (recommended) operating voltage range.
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Reset input timing
VIH
VIL
RESETB
tRST
VDDL
RC Oscillation
(internal)
Oscillating
Oscillating
STATUS0
LOUT
GND
Internal reset
process
Waiting
Waiting
Playing
Status
Reset(standby)
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SAI interface timing (master)
tD_LRCLK
VIH
VIL
LRCLK
tC_BCLK
VIH
VIL
BCLK
tD_SAIOUT
tHW_BCLK tLW_BCLK
VIH
VIL
SAI_OUT
MCLKO is synchronized with BCLK.
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Serial flash memory interface timing
EROFF VIH
VIL
VIH
ERCSB
VIL
tESCKF
tESCKL
tECSH
tECSS
VIH
ERSCK
VIL
tEDIS
tEDIH
tESCK
VIH
VIL
ERSI
tEFHL
tEDOD
tEFLH
VO
VO
ERSO
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● Clock synchronous serial
Clock Synchronous Serial Interface Timing (SCK Initial Value = "H" Level)
VIH
CSB
VIL
tCSH
tSCKS tESCK
tSCKH
VIH
VIL
SCK
tDIS
tDIH
tSCKL
VIH
VIL
SI
tDOD
tDOZ
VIH
VIL
SO*
Clock Synchronous Serial Interface Timing (SCK Initial Value = "L" Level)
VIH
CSB
VIL
tCSH
tSCKS tESCK
tSCKL
VIH
VIL
SCK
tDIS
tDIH
tSCKH
VIH
VIL
SI
tDOD
tDOZ
VIH
VIL
SO*
* Outputs "H" or "L" to the SO pin only when reading.
At the time of writing, the SO pin is in a high impedance state.
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Crystal oscillation switching timing
CSB
SCK
Select Crystal oscillation
SI
RC Oscillation
Oscillating
(internal)
XT, XTB
Oscillation stable
Oscillation stopped
Waiting for oscillation stabilization
PUP_XT bit (STAT0 register)
Operate with
Crystal or Ceramic oscillation
Status
Operate with RC oscillation
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Sound output power-up timing (pop noise countermeasure bit POP =“1”)
CSB
SCK
OUT_EN =1
SI
tPUP1
LOUT *1
GND
SAI *2
Output start
Output stopped
PUP_OUT bit (STAT0 register)
Status
POP noise suppressed
Sound output power up
Sound output power down
*1 If playback from the LINE amplifier is not selected in OUT_MD [1: 0] of the OUTMODE register, it is fixed to
GND.
*2 If playback from the SAI pin is not selected in OUT_MD [1: 0] of the OUTMODE register, not output to the SAI
pin (BCLK / LRCLK / SAI_OUT / STATUS1_MCLKO).
Sound output power-up timing (pop noise countermeasure bit POP =“0”)
CSB
SCK
OUT_EN =1
SI
tPUP0
LOUT *1
GND
SAI *2
Output start
Output stopped
PUP_OUT bit (STAT0 register)
Status
processing
Sound output power up
Sound output power down
*1 If playback from the LINE amplifier is not selected in OUT_MD [1: 0] of the OUTMODE register, it is fixed to
GND.
*2 If playback from the SAI pin is not selected in OUT_MD [1: 0] of the OUTMODE register, not output to the SAI
pin (BCLK / LRCLK / SAI_OUT / STATUS1_MCLKO).
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Sound output power-down timing (pop noise countermeasure bit POP =“1”)
CSB
SCK
OUT_EN =0
SI
tPD1
LOUT *1
GND
SAI *2
Output stopped
Output
PUP_OUT bit (STAT0 register)
Status
POP noise suppressed
Sound output power down
Sound output power up
*1 If playback from the LINE amplifier is not selected in OUT_MD [1: 0] of the OUTMODE register, it is fixed to
GND.
*2 If playback from the SAI pin is not selected in OUT_MD [1: 0] of the OUTMODE register, not output to the SAI
pin (BCLK / LRCLK / SAI_OUT / STATUS1_MCLKO).
Sound output power-down timing (pop noise countermeasure bit POP =“0”)
CSB
SCK
OUT_EN =0
SI
tPD0
LOUT *1
GND
SAI *2
Output stopped
Output
PUP_OUT bit (STAT0 register)
Status
processing
Sound output power down
Sound output power up
*1 If playback from the LINE amplifier is not selected in OUT_MD [1: 0] of the OUTMODE register, it is fixed to
GND.
*2 If playback from the SAI pin is not selected in OUT_MD [1: 0] of the OUTMODE register, not output to the SAI
pin (BCLK / LRCLK / SAI_OUT / STATUS1_MCLKO).
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Flash memory access flow
CSB
SCK
FLS_ACCS mode
SI
setting
SO
EROFF
Hiz
Hiz
Hiz
ERCSB
ERSCK
ERSO
Hiz
ERSI
Status
FLS_ACCS mode
Normal mode
When FLS_ACCS mode is set, the pins are directly connected inside the LSI as shown below. When the EROFF pin
is set to H level, the ERCSB, ERSCK, ERSO and ERSI pins are in the HiZ(high-impedance) state.
Symbol
I/O
Symbol to be
connected
ERCSB
ERSCK
ERSO
I/O
EROFF=L
EROFF=H
HiZ
CSB
SCK
SI
I
I
I
O
O
O
HiZ
HiZ
SO
O
ERSI
I (Pull Down)
HiZ
MCU
LSI
Flash memory
CSB
SCK ESCK
ECSB
CSB
SCK
CSB
SCK
SI
ESO
ESI
SI
SO
SI
SO
SO
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SoundGenerator initial setting flow
Initial setting start
No
Internal regulator startup completed
STATUS0 pin == 1
Yes
CLKSEL register setting
Reference clock setting
STATUS1_MCLKO output setting
Status output settings
IFSEL register setting
OUTSTAT0/1_n register setting (n=0 to 5)
SAITCON register setting
MCLKCON register setting
SAI related settings
OUTDATA register setting
OUTMODE register setting
OUTCON register setting
Sound output settings
PITFADE_STEP register setting
PITFADE_CON register setting
Pitch related settings
VOLFADE_STEP register setting
VOLFADE_CON register setting
Volume related settings
EQxCON register setting
EQxGAINn register setting
EQxBANDnA0L/H register setting
EQxBANDnA1L/H register setting
(x=L, R)
Equalizer related settings
(n=0 to 4)
No
STAT0 register bit4
Start output from LINE amplifier or SAI pins
PUP_OUT == 1
Yes
Initial setting end
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SoundGenerator playback flow (Single channel / with loop)
Start
①Phrase information setting (single channel)
PHRASE_SD_CHn register setting
LOOPCON_SD register setting
Set playback CH
②Set the loop playback of the any CH
Set playback CH to loop playback
PIT_SD_CHn_L/H register setting
VOL_SD_CHn_L/H register setting
③Set the pitch of the any CH
④Set the volume of the any CH
PITCON_SD register setting
VOLCON_SD register setting
PLAYCON_SD register setting
⑤Set pitch control (independent or linked to CH0)
⑥Set volume control（independent or linked to CH0）
⑦Enable playback of the any CH
Enable playback CH
VOL_MASTL_L/H register setting
VOL_MASTR_L/H register setting
⑧Set master volume
⑨Enable playback (Common to all CHs)
Play the CH enabled in ⑦
PLAYCON_MAST register setting
End
CSB
SCK
SI
②
⑧
⑨
①
tPSTA
STAT1 register
STATP_SD_CHn bit
LOUT
Status
One phrase
Loop playing
Playing
Waiting（LINE amplifier ON）
・SoundGenerator can select once playback or loop playback depending on the presence or absence of loop setting. To
end loop playback, release the loop setting and wait for the phrase to end before ending playback. If want to end the
playback immediately, disable the any CH.
・If phrases with different sampling frequencies are started playing on different channels at the same time, there may be
a gap between the channels during a loop depending on the sound code data length.
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SoundGenerator playback flow (Single channel / without loop)
Start
①Phrase information setting (single channel)
PHRASE_SD_CHn register setting
LOOPCON_SD register setting
Set playback CH
②Set the loop playback of the any CH
Set playback CH to once playback
PIT_SD_CHn_L/H register setting
VOL_SD_CHn_L/H register setting
③Set the pitch of the any CH
④Set the volume of the any CH
PITCON_SD register setting
VOLCON_SD register setting
PLAYCON_SD register setting
⑤Set pitch control (independent or linked to CH0)
⑥Set volume control（independent or linked to CH0）
⑦Enable playback of the any CH
Enable playback CH
VOL_MASTL_L/H register setting
VOL_MASTR_L/H register setting
⑧Set master volume
⑨Enable playback (Common to all CHs)
Play the CH enabled in ⑦
PLAYCON_MAST register setting
End
CSB
SCK
SI
②
⑧
⑨
①
tPSTA
STAT1 register
STATP_SD_CHn bit
LOUT
Status
One phrase
Playing
Waiting(LINE amplifier ON）
Waiting(LINE amplifier ON）
SoundGenerator can select once playback or loop playback depending on the presence or absence of loop setting.
When playing once, the playback ends at the same time as the phrase ends.
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SoundGenerator pitch / volume change flow during playback
Start
Playback initial settings (with loop) have already been set
①Enable playback (Common to all CHs)
Play the CH enabled
PLAYCON_MAST register setting
No
②Playback start
STATP_SD_CHn == 1
Confirm the start of playback of the any CH
Yes
③Pitch change
Update the pitch of the any CH
PIT_SD_CHn_L/H register setting
④Volume change
Update the volume of the any CH
VOL_SD_CHn_L/H register setting
End
CSB
SCK
SI
①
③
④
tPSTA
STAT1 register
STATP_SD_CHn bit
LOUT
Status
Playing
Waiting(LINE amplifier ON）
The pitch and volume can be changed during playback.
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SoundGenerator loop playback release timing
CSB
SCK
SI
Release loop setting
STAT1 register
STATP_SD_CHn bit
LOUT
One phrase
One phrase
One phrase
Status
Playing(loop playing）
Waiting(LINE amplifier ON）
Loop playback is stopped at the end of the phrase.
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Playback end timing (without fade)
Start
①Set the volume of the any CH or
master volume to MUTE.
VOL_SD_CHn_L/H register setting
or
VOL_MASTL_L/H register setting
VOL_MASTR_L/H register setting
STOPCON_SD register setting
or
②Stops playback of the any CH or all CHs.
PLAYCON_MAST register setting
End
CSB
SCK
VOL_MASTL/R＝0x000
PLAYCON_MAST＝0x00
SI
tPSTP
STAT2 register
STATF_SD_CHn bit
STAT1 register
STATP_SD_CHn bit
LOUT
Waiting (LINE amplifier ON）
Playing silently
Status
Playing
・To stop the playback of multiple channels, set the volume (VOL_SD_CHn) of the any CH to MUTE.
To stop playback of all channels, set the master volume (VOL_MASTL L/H, VOL_MASTR L/H) to MUTE.
・To stop playback when playing a single channel, set the master volume (VOL_MASTL_L/H, VOL_MASTR_L/H) to
MUTE.
・To restart playback after stopping playback in the PLAYCON_MAST register, refer to the SoundGenerator playback
flow.
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Playback end timing (with fade)
Start
VOL_SD_CHn_L/H register setting
or
①Set the volume of the any CH or
master volume to MUTE.
VOL_MASTL_L/H register setting
VOL_MASTR_L/H register setting
②Confirm that the fade of the any CH or
master volume is completed.
No
STATF_SD_CHn == 0
STATF_MASTL/R == 0
Yes
STOPCON_SD register setting
or
③Stops playback of the any CH or all CHs.
PLAYCON_MAST register setting
End
CSB
SCK
VOL_MASTL/R＝0x000
PLAYCON_MAST＝0x00
SI
tFAD
tPSTP
STAT3 register
STATF_MAST_L/R bit
STAT1 register
STATP_SD_CHn bit
LOUT
Status
Waiting(LINE amplifier ON）
Playing silently
Playing
Fading out
・To stop the playback of multiple channels, set the volume (VOL_SD_CHn) of the any CH to MUTE.
To stop playback of all channels, set the master volume (VOL_MASTL_L/H, VOL_MASTR_ L/H) to MUTE.
・To stop playback when playing a single channel, set the master volume (VOL_MASTL_L/H, VOL_MASTR_L/H) to
MUTE.
・To restart playback after stopping playback in the PLAYCON_MAST register, refer to the SoundGenerator playback
flow.
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SoundGenerator CH additional playback flow
・When playing a CH that is not playing while playing any CH
(When playing the stopped CH after stopping the playback of only some CHs with the STOPCON_SD register while
playing multiple CHs.)
Start
Phrase information setting (single channel)
PHRASE_SD_CHn register setting
LOOPCON_SD register setting
Set playback CH
Set the loop playback of the any CH
Set playback CH to loop playback
PIT_SD_CHn_L/H register setting
VOL_SD_CHn register setting
Set the pitch of the any CH
Set the volume of the any CH
PITCON_SD register setting
VOLCON_SD register setting
PLAYCON_SD register setting
Set pitch control (independent or linked to CH0)
Set volume control（independent or linked to CH0）
Enable playback of the any CH
Enable playback CH
End
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Volume change timing (all CHs) (without fade)
CSB
SCK
Change master volume
SI
STAT3 register
“L”
STATF_MAST_L/R bit
LOUT
Status
Playing
Volume change timing (all CHs) (with fade)
CSB
SCK
Change master volume
SI
tFAD
STAT3 register
STATF_MAST_L/R bit
LOUT
Status
Fading
Playing
Playing
*1 For the volume transition time, refer " VOLFADE_STEP register" in the registers.
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● I2C Interface (Slave)
I2C Interface Timing
Start
Condition
Restart
Condition
Stop
Condition
SDA
SCL
tBUF
tSU:STO
tHD:STA
tLOW tHIGH
tSU:STA tHD:STA
tSU:DAT tHD:DAT
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■ Registers
● Register bank list
Registers are arranged in banks for each function.
Banks are switched using the BANKSEL register, which is a register common to all banks.
BANKSEL register [3:0]
Select registers section
SoundGenerator0 related registers
SoundGenerator1 related registers
EqualizerLch related registers
EqualizerRch related registers
Setting prohibited
0x0
0x1
0x2
0x3
0x4-0xF
Check the following pages for the registers of each bank.
Writing to banks and addresses not listed is prohibited. Write the initial value to the unused bit of each register.
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● Registers list
All banks common registers list（BANKSEL[3:0]= 0x0，0x1，0x2，0x3）
The address space from 0x00 to 0x3F is common to all banks and can be accessed from any bank.
Writing to addresses not listed is prohibited. Write the initial value to the unused bit of each register.
Address
0x00
Register name
BANKSEL
CLKSEL
I2CSEL
Functions
Access bank selection
R/W
R/W
R/W
R/W
R/W
R/W
R
0x01
Reference clock selection
I2C access mode selection
0x02
0x03
IFSEL
IF selection
0x04
LRSEL
Selection of Lch / Rch setting values
Write prohibited
0x05~0x06
0x07
-
ERROR
STAT0
Notification of internal error status
Notification of internal status
R/W
R
0x08
0x09
STAT1
Notification of playback status of CH 0 to 3
Notification of volume fade status of CH 0 to 3
Notification of master volume Lch/Rch fade status
Write prohibited
R
0x0A
STAT2
R
0x0B
STAT3
R
0x0C~0x0F
0x10
-
R
FLS_ACCS
-
Serial flash memory access control
Write prohibited
W
0x11~0x15
0x16
R
SAITCON
-
SerialAudioInterface transfer format setting
Write prohibited
R/W
R
0x17
0x18
-
Write prohibited
R
0x19
MCLKCON
-
SerialAudioInterface MCLK output control
Write prohibited
R/W
R
0x1A
0x1B
OUTDATA
OUTMODE
OUTCON
-
Sound output data transfer channel setting
Sound output mode setting
R/W
R/W
R/W
R
0x1C
0x1D
Sound output control
0x1E~0x1F
0x20
Write prohibited
OUTSTAT0_0
OUTSTAT0_1
OUTSTAT0_2
OUTSTAT0_3
-
STATUS0 pin output setting of STAT0 register
STATUS0 pin output setting of STAT1 register
STATUS0 pin output setting of STAT2 register
STATUS0 pin output setting of STAT3 register
Write prohibited
R/W
R/W
R/W
R/W
R
0x21
0x22
0x23
0x24
0x25
OUTSTAT0_5
-
STATUS0 pin output setting of ERROR register
Write prohibited
R/W
R
0x26,0x27
0x28
OUTSTAT1_0
OUTSTAT1_1
OUTSTAT1_2
OUTSTAT1_3
-
STATUS1_MCLKO pin output setting of STAT0 register
STATUS1_MCLKO pin output setting of STAT1 register
STATUS1_MCLKO pin output setting of STAT2 register
STATUS1_MCLKO pin output setting of STAT3 register
Write prohibited
R/W
R/W
R/W
R/W
R
0x29
0x2A
0x2B
0x2C
0x2D
OUTSTAT1_5
-
STATUS1_MCLKO pin output setting of ERROR register
Write prohibited
R/W
R
0x2E
0x2F
OUTSTAT2
STATUS2 pin output setting of ERROR register
R/W
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Address
0x30~0x31
0x32
Register name
-
Functions
R/W
R
Write prohibited
PITFADE_STEP
PITFADE_CON
-
Pitch fade step setting
Pitch fade control
R/W
R/W
R
0x33
0x34,0x35
0x36
Write prohibited
VOLFADE_STEP
VOLFADE_CON
VOL_MASTL_L
VOL_MASTL_H
VOL_MASTR_L
VOL_MASTR_H
-
Volume fade step setting
Volume fade control
Master volume Lch setting
R/W
R/W
R/W
R/W
R/W
R/W
R
0x37
0x38
0x39
0x3A
Master volume Rch setting
0x3B
0x3C~0x3D
0x3E
Write prohibited
Playback start / stop control
Write prohibited
PLAYCON_MAST
-
R/W
R
0x3F
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SoundGenerator0 related registers list（BANKSEL[3:0]=0x0 ）
Writing to addresses not listed is prohibited. Write the initial value to the unused bit of each register.
The address space from 0x00 to 0x3F is common to all banks, so refer to "All banks common registers list".
Address
0x00~0x3F
0x40
Register name
-
Functions
R/W
-
All banks common registers
Pitch control of CH
PITCHCON_SD
VOLCON_SD
PLAYCON_SD
STOPCON_SD
-
R/W
R/W
W
0x41
Volume control of CH
Playback control of CH
Playback stop control of CH
Write prohibited
0x42
0x43
W
0x44~0x4F
0x50
R
PIT_SD_CH0_L
PIT_SD_CH0_H
PIT_SD_CH1_L
PIT_SD_CH1_H
PIT_SD_CH2_L
PIT_SD_CH2_H
PIT_SD_CH3_L
PIT_SD_CH3_H
-
Pitch setting of CH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x51
0x52
Pitch setting of CH1
Pitch setting of CH2
Pitch setting of CH3
0x53
0x54
0x55
0x56
0x57
0x58~0x5F
0x60
Write prohibited
VOL_SD_CH0_L
VOL_SD_CH0_H
VOL_SD_CH1_L
VOL_SD_CH1_H
VOL_SD_CH2_L
VOL_SD_CH2_H
VOL_SD_CH3_L
VOL_SD_CH3_H
-
Volume setting of CH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x61
0x62
Volume setting of CH1
Volume setting of CH2
Volume setting of CH3
Write prohibited
0x63
0x64
0x65
0x66
0x67
0x68~0x7F
SoundGenerator1 related registers list（BANKSEL[3:0]=0x1）
Writing to addresses not listed is prohibited. Write the initial value to the unused bit of each register.
The address space from 0x00 to 0x3F is common to all banks, so refer to "All banks common registers list".
Address
0x00~0x3F
0x40
Register name
Functions
R/W
-
-
All banks common registers
Phrase setting of CH0
Phrase setting of CH1
Phrase setting of CH2
Phrase setting of CH3
Write prohibited
PHRASE_SD_CH0
PHRASE_SD_CH1
PHRASE_SD_CH2
PHRASE_SD_CH3
-
R/W
R/W
R/W
R/W
R
0x41
0x42
0x43
0x44~0x47
0x48
LOOPCON_SD
-
Loop playback control
Write prohibited
R/W
R
0x49~0x7F
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EqualizerLch related registers list（BANKSEL[3:0]=0x2）
Writing to addresses not listed is prohibited. Write the initial value to the unused bit of each register.
The address space from 0x00 to 0x3F is common to all banks, so refer to "All banks common registers list".
Address
0x00~0x3F
0x40
Register name
-
Functions
R/W
-
All banks common registers
EQ Lch enable control
EQLCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x41
EQLGAIN0
EQ Lch Band0 gain setting
EQ Lch Band1 gain setting
EQ Lch Band2 gain setting
EQ Lch Band3 gain setting
EQ Lch Band4 gain setting
EQ Lch Band0 A0 coefficient setting
0x42
EQLGAIN1
0x43
EQLGAIN2
0x44
EQLGAIN3
0x45
EQLGAIN4
0x46
EQLBAND0A0L
EQLBAND0A0H
EQLBAND0A1L
EQLBAND0A1H
EQLBAND1A0L
EQLBAND1A0H
EQLBAND1A1L
EQLBAND1A1H
EQLBAND2A0L
EQLBAND2A0H
EQLBAND2A1L
EQLBAND2A1H
EQLBAND3A0L
EQLBAND3A0H
EQLBAND3A1L
EQLBAND3A1H
EQLBAND4A0L
EQLBAND4A0H
EQLBAND4A1L
EQLBAND4A1H
-
0x47
0x48
EQ Lch Band0 A1 coefficient setting
EQ Lch Band1 A0 coefficient setting
EQ Lch Band1 A1 coefficient setting
EQ Lch Band2 A0 coefficient setting
EQ Lch Band2 A1 coefficient setting
EQ Lch Band3 A0 coefficient setting
EQ Lch Band3 A1 coefficient setting
EQ Lch Band4 A0 coefficient setting
EQ Lch Band4 A1 coefficient setting
Write prohibited
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A-0x7F
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EqualizerRch related registers list（BANKSEL[3:0]=0x3）
Writing to addresses not listed is prohibited. Write the initial value to the unused bit of each register.
The address space from 0x00 to 0x3F is common to all banks, so refer to "All banks common registers list".
Address
0x00~0x3F
0x40
Register name
-
Functions
R/W
-
All banks common registers
EQ Rch enable control
EQRCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x41
EQRGAIN0
EQ Rch Band0 gain setting
EQ Rch Band1 gain setting
EQ Rch Band2 gain setting
EQ Rch Band3 gain setting
EQ Rch Band4 gain setting
EQ Rch Band0 A0 coefficient setting
0x42
EQRGAIN1
0x43
EQRGAIN2
0x44
EQRGAIN3
0x45
EQRGAIN4
0x46
EQRBAND0A0L
EQRBAND0A0H
EQRBAND0A1L
EQRBAND0A1H
EQRBAND1A0L
EQRBAND1A0H
EQRBAND1A1L
EQRBAND1A1H
EQRBAND2A0L
EQRBAND2A0H
EQRBAND2A1L
EQRBAND2A1H
EQRBAND3A0L
EQRBAND3A0H
EQRBAND3A1L
EQRBAND3A1H
EQRBAND4A0L
EQRBAND4A0H
EQRBAND4A1L
EQRBAND4A1H
-
0x47
0x48
EQ Rch Band0 A1 coefficient setting
EQ Rch Band1 A0 coefficient setting
EQ Rch Band1 A1 coefficient setting
EQ Rch Band2 A0 coefficient setting
EQ Rch Band2 A1 coefficient setting
EQ Rch Band3 A0 coefficient setting
EQ Rch Band3 A1 coefficient setting
EQ Rch Band4 A0 coefficient setting
EQ Rch Band4 A1 coefficient setting
Write prohibited
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A-0x7F
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● Description of Register Functions
All banks common registers list (BANKSEL[3:0]= 0x0, 0x1, 0x2, 0x3)
Access bank selection register（BANKSEL）
Bank
Address
：0x0，0x1，0x2，0x3
：0x00
Initial value ：0x00
Functions
：Access bank selection
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Access bank selection
0x0： SoundGenerator0 related registers
0x1： SoundGenerator1 related registers
0x2： EqualizerLch related registers
0x3： EqualizerRch related registers
0x4-0xF ： Setting prohibited
3-0
BANK[3:0]
R/W
0000
It is a common register for all BANK registers.
Registers other than addresses 0x00 to 0x3F are independent registers for each bank.
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Clock selection register（CLKSEL）
Bank
Address
：0x0，0x1，0x2，0x3
：0x01
Initial value ：0x00
Funcrions
：Reference clock selection
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00000
7-3
―
Reference clock selection
0： Use RC4Mz
2
XTSEL
Unused
R/W
R
0
1： Use a crystal or ceramic oscillator or an
external clock input
1-0
―
00
[Note]
・When using a crystal oscillator, ceramic oscillator, or external clock input, release the reset after turning on the power,
check the power-up of the internal regulator (PUP bit of the STAT0 register is "1"), and then set it. Do not set during
playback operation.
・If the XTSEL bit is set to "1", it will continue to be "1" even if it is set to "0".
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I2C access mode selection register（I2CSEL）
Bank
Address
：0x0，0x1，0x2，0x3
：0x02
Initial value ：0x00
Functions
：I2C access mode selection
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000000
7-1
―
I2C access mode selection
0
RANDOM
0： Use increment mode
R/W
0
1： Use random access mode
[Note]
・The setting of this register is valid when I2C interface is performed with the MCU interface. When communication is
performed by clock synchronous serial interface, only the increment mode is supported, and the setting of this register is
invalid.
・After switching the RANDOM bit, be sure to restart from the start condition.
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IF selection register（IFSEL）
Bank
Address
：0x0，0x1，0x2，0x3
：0x03
Initial value ：0x00
Functions
：IF seletion
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Input mode selection
0： Use one-times input mode
1： Use two-times input mode
―
4
3-1
0
TWSEL
Unused
R/W
R
0
000
0
STATUS1_MCLKO pin selection
0： Select STATUS1
1： Select MCLKO
MCLKSEL
R/W
[Note]
・The TWSEL bit is set to “1”, shifts to two-times input mode. For details on how to input address or data, refer "Clock
synchronous serial interface" and "I2C interface" in the function description.
・After switching the TWSEL bit, be sure to return the CSB pin to the “H” level or restart from the start condition.
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LR selection register（LRSEL）
Bank
Address
：0x0，0x1，0x2，0x3
：0x04
Initial value ：0x00
Functions
：Selection of Lch/Rch setting values
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
Selection of Rch setting value of equalizer
1
0
LR_EQ
0： Apply Rch setting value(control independently)
1： Apply Lch setting value(control linked to Lch)
Selection of Rch setting value of master volume
0： Apply VOL_MASTR_L/H(control independently)
1： Apply VOL_MASTL_L/H(control linked to Lch)
R/W
R/W
0
0
LR_VOL
[Note]
・When the LR_EQ bit is set to “1”, the equalizer Rch is controlled by the EqualizerLch related registers. EqualizerRch
related registers can be written / read.
・When the LR_VOL bit is set to “1”, the the master volume Rch is controlled by the VOL_MASTL_L/H register. The
VOL_MASTR_L/H register can be written / read.
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Error register（ERROR）
Bank
Address
：0x0，0x1，0x2，0x3
：0x07
Initial value ：0x00
Functions
：Notification of internal error status
Bit
7
Bit name
Unused
Functions
R/W
R
Initial value
0
―
Notification of the error of the flash memory
read data during the internal reset process
0： No error
6
5
4
3
2
ROMERR
Unused
TWERR
Unused
CLKERR
Unused
R
R
0
0
1： Error
―
Notification of the error in the two-times input
mode
R/W
R
0
0： No error
1： Error
―
0
Notification of stop error of crystal oscillator or
ceramic oscillator or external clock input
0： No error
R/W
R
0
1： Error
1-0
―
00
[Note]
・The ROMERR bit is not cleared even if it is written to this register. Initialize this LSI by resetting with the RESETB.
・The TWERR bit notifies an error when a mismatch occurs between the first data input and the second data input with the
TWSEL bit in the IFSEL register set to “1”. It is cleared by writing to this register.
・The CLKERR bit notifies an error when oscillation stop is detected with the XTSEL bit of the CLKSEL register set to “1”.
The playback status continues, so take measures such as stopping playback as necessary. It is cleared by writing to this
register. However, if oscillation is still stopped, the CLKERR bit is set to “1” again.
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Status register 0（STAT0）
Bank
Address
：0x0，0x1，0x2，0x3
：0x08
Initial value ：0x01
Functions
：Notification of internal status
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Notification of output status from LINE amplifier
or SAI pin
4
3
2
PUP_OUT
Unused
R
R
R
0
0
0
Notification of the status when the OUT_EN bit of
the OUTCON register is changed. *1
―
Notification of the status of the crystal oscillator
or ceramic oscillator or external clock input
0： Waiting for oscillation stabilization or stopping
1： Oscillating
PUP_XT
All banks common registers，
SoundGenerator0 related registers，
SoundGenerator1 related registers，
EqualizerLch related registers，
EqualizerRch related registers
0： Not set
1
0
REG_SET
R
R
0
1
1： Configured
Notification of internal regulator startup status
0： Internal regulator power down
1： Internal regulator power up
PUP
*1 Refer "Sound output power up and Sound output power down" in the timing chart.
[Note]
・When turn on the power and release the reset, be sure to check that the PUP bit is set to “1” before performing the following
processing. Writing and reading to other registers with the PUP bit set to “0” is not guaranteed.
・The REG_SET bit becomes "1" by writing to all of the following registers. To set the REG_SET bit to "1", be sure to write
the initial value even if the following registers are used as they are.
BANKSEL register[3:0]
register
0x0,0x1,0x2,0x3
0x2D ： OUTSTAT1_5
(All banks common registers）
0x0（SoundGenerator0 related registers）
0x1（SoundGenerator1 related registers）
0x2（EqualizerLch related registers）
0x3（EqualizerRch related registers）
0x67 ： VOL_SD_CH3_H
0x48 ： LOOPCON_SD
0x59 ： EQLBAND4A1H
0x59 ： EQRBAND4A1H
・The REG_SET bit is set to “0”, it means that the register has not been set or the register may have been initialized for some
reason. In that case, reset all the registers before accessing the playback mode setting register and playback control register.
・Confirm that the PUP_OUT bit is “1” before playing.
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Status register 1（STAT1）
Bank
Address
：0x0，0x1，0x2，0x3
：0x09
Initial value ：0x00
Functions
：Notification of playback status of CH 0 to 3
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Notification of playback status of CH3
0： Playing stopped
3
2
1
0
STATP_SD_CH3
STATP_SD_CH2
STATP_SD_CH1
STATP_SD_CH0
R
R
R
R
0
0
0
0
1： Playing
Notification of playback status of CH2
0： Playing stopped
1： Playing
Notification of playback status of CH1
0： Playing stopped
1： Playing
Notification of playback status of CH0
0： Playing stopped
1： Playing
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Status register 2（STAT2）
Bank
Address
：0x0，0x1，0x2，0x3，
：0x0A
Initial value ：0x00
Functions
：Notification of volume fade status of CH 0 to 3
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Notification of fade status of CH3
0： Fading stopped
1： Fading
3
2
1
0
STATF_SD_CH3
STATF_SD_CH2
STATF_SD_CH1
STATF_SD_CH0
R
R
R
R
0
0
0
0
Notification of fade status of CH2
0： Fading stopped
1： Fading
Notification of fade status of CH1
0： Fading stopped
1： Fading
Notification of fade status of CH0
0： Fading stopped
1： Fading
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Status register 3（STAT3）
Bank
Address
：0x0，0x1，0x2，0x3
：0x0B
Initial value ：0x00
Functions
：Notification of master volume Lch/Rch fade status
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
Notification of fade status of master volume Rch
0： Fading stopped
1
0
STATF_MAST_R
STATF_MAST_L
R
R
0
0
1： Fading
Notification of fade status of master volume Lch
0： Fading stopped
1： Fading
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Flash memory access control register（FLS_ACCS）
Bank
Address
：0x0，0x1，0x2，0x3
：0x10
Initial value ：0xXX
Functions
：Serial flash memory access control
Bit
Bit name
Functions
R/W
W
Initial value
0xXX
7-0
FLS_PRT[7:0]
Flash memory protect code
[Note]
・It is necessary to set the flash memory protection release information in advance using the dedicated tool
(SpeechLSIUtility).
・If the flash memory protection release information set by the dedicated tool (SpeechLSIUtility) is 0x69, the flash memory
interface is not connected even if it matches the flash memory protection code set in the FLS_ACCS register.
・If the flash memory protection release information set by the dedicated tool (SpeechLSIUtility) is other than 0x69, the flash
memory interface is connected when it matches the flash memory protection code set in the FLS_ACCS register.
・Once the clock synchronous serial interface and the flash memory interface are connected, the normal mode cannot be
restored. To return to the normal mode, input the "L" level to the reset input pin (RESETB pin) to initialize this LSI.
・When rewriting the flash memory, input the "L" → "H" level to the reset input pin (RESETB pin), and then set it in the
FLS_ACCS register. After inputting the “L” → “H” level to the RESETB pin, the FLS_ACCS register cannot be set after
setting other than the FLS_ACCS register.
・The flash memory cannot be rewritten using the I2C interface (slave), so do not write to this register.
.
Serial
FLASH
LSI
Match*1
Normal mode
（Internal control）
Sound
Generator
(4ch)
Volume
(4ch)
Match*1
Host
MCU
SPI
Pitch Control
Normal mode
（Internal control）
*1：The write conditions to the flash memory access control register match
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SerialAudioInterface transfer format setting register（SAITCON）
Bank
Address
：0x0，0x1，0x2，0x3
：0x16
Initial value ：0x00
Functions
：SerialAudioInterface transfer format setting
Bit
Bit name
BWO
Functions
Bit width for transfer
R/W
R/W
R
Initial value
7
6
5
0： 16bit Straight PCM
0
0
0
1： 8bit Straight PCM
Unused
FMTO
―
Transfer mode
0： LRCLK transfer mode
1： Frame synchronous transfer mode
MSB first or LSB first in the transmit data.
0： MSB first
R/W
4
3
2
1
MSBO
ISSCKO
AFOO
R/W
R/W
R/W
R/W
0
0
0
0
1： LSB first
BCLK pin as 32gfs or 64gfs.
0： 32gfs
1： 64gfs
Transmit data is left-aligned or right-aligned
0： Left-justify
1： Right-justify
Transmit data has a 1-clock delay or not.
0： Serial data delay
DLYO
1： No serial data delay
LRCLK polarities
0： Lch is transmitted when LRCLK is "L" level,
Rch is transmitted when LRCLK is "H" level
1： Lch is transmitted when LRCLK is "H" level,
Rch is transmitted when LRCLK is "L" level
0
WSLO
R/W
0
[Note]
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
・Set the WSLO bit to "1" in the frame synchronous transfer mode (set "1" for the FMTO bit).
・Set the AFOO bit to "0" in the frame synchronous transfer mode (set "1" to the FMTO bit).
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SerialAudioInterface MCLK control register （MCLKCON）
Bank
Address
：0x0，0x1，0x2，0x3
：0x19
Initial value ：0x00
Functions
：SerialAudioInterface MCLK output control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00000
7-3
―
MCLKO output setting
00： 128gfs
2-1
MCLK_FS
R/W
R/W
00
0
01： 256gfs
1*： 512gfs
MCLKO pin master clock output setting
0： Disable output
1： Enable output
0
MCLK_EN
*：0/1 Either is acceptable
MCLKSEL bit of the IFSEL register is "1" and the MCLK_EN of the MCLKCON register is "1", select playback from SAI
pin by OUT_MD [1: 0] bits of the OUTMODE register. After setting the OUT_EN bit to “1”, when the PUP_OUT bit in
STAT0 register becomes “1”, master clock output is started from the STATUS1_MCLKO pin.
[Note]
Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
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Sound output data transfer channel setting register（OUTDATA）
Bank
Address
：0x0，0x1，0x2，0x3
：0x1B
Initial value ：0x44
Functions
：Sound output data transfer channel setting
Bit
7
Bit name
Unused
Functions
R/W
R
Initial value
0
―
Setting the data to transmit to the Rch
000：CH0
001：CH1
010：CH2
011：CH3
1xx：Mixing CH0-3
―
6-4
3
OUT_RCH [2:0]
Unused
R/W
R
100
0
Setting the data to transfer to the Lch and LINE
amplifiers
000：CH0
001：CH1
2-0
OUT_LCH [2:0]
R/W
100
010：CH2
011：CH3
1xx：Mixing CH0-3
[Note]
Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
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Sound output mode setting register（OUTMODE）
Bank
Address
：0x0，0x1，0x2，0x3
：0x1C
Initial value ：0x01
Functions
：Sound output mode setting
Bit
Bit name
HPF
Functions
High-pass filter control
R/W
R/W
Initial value
0
0： No use high-pass filter
1： Use high-pass filter with a cut-off frequency of
200Hz
7
Selection of a group (gfs) of sampling frequencies
0： a group of 12，24，48kHz（SAI output：gfs=48kHz）
1： a group of 8，16，32kHz（SAI output：gfs=32kHz）
―
6
GFS
R/W
R
0
5-3
Unused
000
LINE amplifier Pop noise countermeasure control
during power-up / down processing
0： Without pop noise suppression
1： With pop noise suppression
2
POP
R/W
R/W
0
1-0
OUT_MD[1:0]
Playback mode setting*1
01
*1 If "00" is written to the OUT_MD [1: 0] bits, "01" is set to the OUT_MD [1: 0] bits.
The combinations of playback using the OUT_MD [1: 0] bits are as follows.
Playback mode
OUT_MD[1]
OUT_MD[0]
Play from LINE amplifier
Play from SAI pins
Play from LINE amplifier and SAI pins
0
1
1
1
0
1
[Note]
・OUTMODE register can be rewritten only when the OUT_EN bit of the OUTCON register is “0”.
・When using only SerialAudioInterface, it is recommended to set the POP bit to “0”.
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Sound output control register（OUTCON）
Bank
Address
：0x0，0x1，0x2，0x3
：0x1D
Initial value ：0x00
Functions
：Sound output control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Output control of playback mode set by
OUT_MD [1: 0]
4
OUT_EN
Unused
R/W
R
0
0： Output stopped
1： Output start
3-0
―
0000
[Note]
When changing OUT_EN bit from “0” to “1”, wait for the PUP_OUT bit in the STAT0 register to become “1” before playing.
When changing from "1" to "0", wait for the PUP_OUT bit in the STAT0 register to become "0" before performing the next
processing.
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STATUS0 pin output setting register 0（OUTSTAT0_0）
Bank
Address
：0x0，0x1，0x2，0x3
：0x20
Initial value ：0x01
Functions
：STATUS0 pin output setting of STAT0 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Output of the PUP_OUT bit to the STATUS0 pin
4
3
2
OS00_OE4
Unused
0： No output
R/W
R
0
0
0
1： Output
―
Output of the PUP_XT bit to the STATUS0 pin
OS00_OE2
0： No output
R/W
1： Output
Output of the REG_SET bit to the STATUS0 pin
1
0
OS00_OE1
OS00_OE0
0： No output
R/W
R/W
0
1
1： Output
Output of the PUP bit to the STATUS0 pin
0： No output
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS0 pin.
OUTSTAT0_0
OS00_OE4
STAT0
STAT0_OUT0
STATUS0 pin
PUP_OUT
STAT0_OUT1
STAT0_OUT2
STAT0_OUT3
OS00_OE2
OS00_OE1
OS00_OE0
PUP_XT
REG_SET
PUP
STAT0_OUT5
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STATUS0 pin output setting register 1（OUTSTAT0_1）
Bank
Address
：0x0，0x1，0x2，0x3
：0x21
Initial value ：0x00
Functions
：STATUS0 pin output setting of STAT1 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Output of the playback status bit of CH0-3 to the
STATUS0 pin
0： No output
1： Output
3-0
OS01_OE3-0
R/W
0000
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS0 pin.
OUTSTAT0_1
OS01_OE3
STAT1
STAT0_OUT1
STATP_SD_CH3
STATUS0 pin
OS01_OE2
STATP_SD_CH2
STATP_SD_CH1
STATP_SD_CH0
STAT0_OUT0
STAT0_OUT2
STAT0_OUT3
OS01_OE1
OS01_OE0
STAT0_OUT5
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STATUS0 pin output setting register 2（OUTSTAT0_2）
Bank
Address
：0x0，0x1，0x2，0x3
：0x22
Initial value ：0x00
Functions
：STATUS0 pin output setting of STAT2 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Output of the volume fade status bit of CH0-3 to
the STATUS0 pin
0： No output
1： Output
3-0
OS02_OE3-0
R/W
0000
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS0 pin.
OUTSTAT0_2
OS02_OE3
STAT2
STAT0_OUT2
STATF_SD_CH3
STATUS0 pin
OS02_OE2
OS02_OE1
OS02_OE0
STATF_SD_CH2
STATF_SD_CH1
STATF_SD_CH0
STAT0_OUT0
STAT0_OUT1
STAT0_OUT3
STAT0_OUT5
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STATUS0 pin output setting register 3（OUTSTAT0_3）
Bank
Address
：0x0，0x1，0x2，0x3
：0x23
Initial value ：0x00
Functions
：STATUS0 pin output setting of STAT3 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
Output of the volume fade status bit of master
volume Lch/Rch to the STATUS0 pin
0： No output
1-0
OS03_OE1-0
R/W
00
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS0 pin.
OUTSTAT0_3
OS03_OE1
STAT3
STAT0_OUT3
STATF_MAST_R
STATUS0 pin
OS03_OE0
STATF_MAST_L
STAT0_OUT0
STAT0_OUT1
STAT0_OUT2
STAT0_OUT5
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STATUS0 pin output setting register 5（OUTSTAT0_5）
Bank
Address
：0x0，0x1，0x2，0x3
：0x25
Initial value ：0x00
Functions
：STATUS0 pin output setting of ERROR register
Bit
7
Bit name
Unused
Functions
R/W
R
Initial value
0
―
Output of the ROMERR bit to the STATUS0 pin
6
OS05_OE6
Unused
0： No output
R/W
R
0
0
1： Output
5
―
Output of the TWERR bit to the STATUS0 pin
4
OS05_OE4
Unused
0： No output
R/W
R
0
1： Output
3
2
―
0
Output of the CLKERR bit to the STATUS0 pin
OS05_OE2
Unused
0： No output
1： Output
―
R/W
R
0
1-0
00
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS0 pin.
OUTSTAT0_5
OS05_OE6
ERROR
ROMERR
STAT0_OUT5
STATUS0 pin
OS05_OE4
OS05_OE2
TWERR
STAT0_OUT0
STAT0_OUT1
STAT0_OUT2
STAT0_OUT3
CLKERR
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STATUS1_MCLKO pin output setting register 0（OUTSTAT1_0）
Bank
Address
：0x0，0x1，0x2，0x3
：0x28
Initial value ：0x00
Functions
：STATUS1_MCLKO pin output setting of STAT0 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Output of the PUP_OUT bit to the
STATUS1_MCLLKO pin
0： No output
4
3
2
OS10_OE4
Unused
R/W
R
0
0
0
1： Output
―
Output of the PUP_XT bit to the STATUS1_MCLLKO
pin
OS10_OE2
R/W
0： No output
1： Output
Output of the REG_SET bit to the STATUS1_MCLLKO
pin
1
OS10_OE1
OS10_OE0
R/W
R/W
0
0
0： No output
1： Output
Output of the PUP bit to the STATUS1_MCLLKO pin
0
0： No output
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS1_MCLKO pin.
OUTSTAT1_0
OS10_OE4
STAT0
STAT1_OUT0
STATUS1_MCLKO pin
PUP_OUT
STAT1_OUT1
STAT1_OUT2
STAT1_OUT3
OS10_OE2
OS10_OE1
OS10_OE0
PUP_XT
REG_SET
PUP
STAT1_OUT5
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STATUS1_MCLKO pin output setting register 1（OUTSTAT1_1）
Bank
Address
：0x0，0x1，0x2，0x3
：0x29
Initial value ：0x00
Functions
：STATUS1_MCLKO pin output setting of STAT1 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Output of the playback status bit of CH0-3 to the
STATUS1_MCLKO pin
0： No output
3-0
OS11_OE3-0
R/W
0000
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS1_MCLKO pin.
OUTSTAT1_1
OS11_OE3
STAT1
STAT1_OUT1
STATP_SD_CH3
STATUS1_MCLKO pin
OS11_OE2
OS11_OE1
OS11_OE0
STATP_SD_CH2
STATP_SD_CH1
STATP_SD_CH0
STAT1_OUT0
STAT1_OUT2
STAT1_OUT3
STAT1_OUT5
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STATUS1_MCLKO pin output setting register 2（OUTSTAT1_2）
Bank
Address
：0x0，0x1，0x2，0x3
：0x2A
Initial value ：0x00
Functions
：STATUS1_MCLKO pin output setting of STAT2 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Output of the volume fade status bit of CH0-3 to
the STATUS1_MCLKO pin
0： No output
3-0
OS12_OE3-0
R/W
0000
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS1_MCLKO pin.
OUTSTAT1_2
OS12_OE3
STAT2
STAT1_OUT2
STATF_SD_CH3
STATUS1_MCLKO pin
OS12_OE2
OS12_OE1
OS12_OE0
STATF_SD_CH2
STATF_SD_CH1
STATF_SD_CH0
STAT1_OUT0
STAT1_OUT1
STAT1_OUT3
STAT1_OUT5
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STATUS1_MCLKO pin output setting register 3（OUTSTAT1_3）
Bank
Address
：0x0，0x1，0x2，0x3
：0x2B
Initial value ：0x00
Functions
：STATUS1_MCLKO pin output setting of STAT3 register
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
Output of the volume fade status bit of master
volume Lch/Rch to the STATUS1_MCLKO pin
0： No output
1-0
OS13_OE1-0
R/W
00
1： Output
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS1_MCLKO pin.
OUTSTAT1_3
OS13_OE1
STAT3
STAT1_OUT3
STATF_MAST_R
STATUS1_MCLKO pin
OS13_OE0
STATF_MAST_L
STAT1_OUT0
STAT1_OUT1
STAT1_OUT2
STAT1_OUT5
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STATUS1_MCLKO pin output setting register 5（OUTSTAT1_5）
Bank
Address
：0x0，0x1，0x2，0x3
：0x2D
Initial value ：0x54
Functions
：STATUS1_MCLKO pin output setting of ERROR register
Bit
7
Bit name
Unused
Functions
R/W
R
Initial value
0
―
Output of the ROMERR bit to the
STATUS1_MCLKO pin
0： No output
6
5
4
3
2
OS15_OE6
Unused
R/W
R
1
0
1： Output
―
Output of the TWERR bit to the STATUS1_MCLKO
pin
OS15_OE4
Unused
R/W
R
1
0： No output
1： Output
―
0
Output of the CLKERR bit to the STATUS1_MCLKO
pin
OS15_OE2
Unused
R/W
R
1
0： No output
1： output
1-0
―
00
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS1_MCLKO pin.
OUTSTAT1_5
OS15_OE6
ERROR
ROMERR
STAT1_OUT5
STATUS1_MCLKO pin
OS15_OE4
OS15_OE5
TWERR
STAT1_OUT0
STAT1_OUT1
STAT1_OUT2
STAT1_OUT3
CLKERR
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STATUS2 pin output setting register （OUTSTAT2）
Bank
Address
：0x0，0x1，0x2，0x3
：0x2F
Initial value ：0x54
Functions
：STATUS2 pin output setting of ERROR register
Bit
7
Bit name
Unused
Functions
R/W
R
Initial value
0
―
Output of the ROMERR bit to the STATUS2 pin
6
OS2_OE6
Unused
0： No output
R/W
R
1
0
1： Output
5
―
Output of the TWERR bit to the STATUS2 pin
4
OS2_OE4
Unused
0： No output
R/W
R
1
1： Output
3
2
―
0
Output of the CLKERR bit to the STATUS2 pin
OS2_OE2
Unused
0： No output
1： Output
―
R/W
R
1
1-0
00
[Note]
When “1” is set for multiple bits, the OR-processed signal is output from the STATUS2 pin.
OUTSTAT2
OS2_OE6
ERROR
ROMERR
STATUS2 pin
OS2_OE4
OS2_OE5
TWERR
CLKERR
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Pitch fade step setting register（PITFADE_STEP）
Bank
Address
：0x0，0x1，0x2，0x3
：0x32
Initial value ：0x00
Functions
：Pitch fade step setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Setting the pitch change step time of the pitch
7-0
PITFADE_STEP[7:0] fade function （0.00390625 times changing
time）
The pitch changes by one step (0.00390625 times) of the pitch setting register every set time until the set pitch is reached.
As shown below, the pitch transition time changes depending on the fade step setting value, pitch change amount, and
sampling frequency (fs).
fs：48kHz
[ms]
fs：24kHz
[ms]
Step：
0.125ms
0.125
0.25
0.375
0.5
：
fs：12kHz
[ms]
Step：
0.25ms
0.25
0.5
0.75
1
：
fs：32kHz
[ms]
Step：
0.09375ms
0.09375
0.1875
0.28125
0.375
fs：16kHz
[ms]
fs：8kHz
[ms]
Step：
0.375ms
0.375
0.75
1.125
1.5
：
PITFADE_
STEP
fs
conversion
Step：
0.0625ms
0.0625
0.125
0.1875
0.25
Step：
0.1875ms
0.1875
0.375
0.5625
0.75
[7:0]
0x00
0x01
0x02
0x03
：
3/fs
6/fs
9/fs
12/fs
：
：
：
：
0x7E
0x7F
0x80
：
381/fs
384/fs
7.9375
8
15.875
16
31.75
32
11.90625
12
23.8125
24
47.625
48
387/fs
：
8.0625
：
16.375
：
32.25
：
12.09375
24.1875
：
48.375
：
：
23.90625
24
765/fs
768/fs
15.9375
16
31.875
32
63.75
64
47.8125
48
95.625
96
0xFE
0xFF
The transition time until the set pitch is reached is expressed by the following formula.
Pitch transition time
＝｜[Current register value] － [New register value]｜× [PITFADE_STEP setting value+1] × 0.0625ms（fs:48kHz）
example）
Current register value（Pitch setting register value）
New register value（Pitch setting register value）
PITFADE_STEP[7:0] setting value
：0x100 = 256d
：0x200 = 512d
：0x07
Pitch transition time ＝ ｜[256] － [512]｜× （7＋1） × 0.0625ms ＝ 128[ms]
[Note]
By setting "1" in the PITFADE_CON register, the changed pitch is faded with the set value of this register.
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Pitch fade control register（PITFADE_CON）
Bank
Address
：0x0，0x1，0x2，0x3
：0x33
Initial value ：0x00
Functions
：Pitch fade control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000000
7-1
―
Control fade
0： No use a fade
1： Use a fade
0
PITFADE_EN
R/W
0
[Note]
When "1" is set, the pitch fades to the changed pitch with the setting value of the PITFADE_STEP register.
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Volume fade step setting regisger（VOLFADE_STEP）
Bank
Address
：0x0，0x1，0x2，0x3
：0x36
Initial value ：0x00
Functions
：Volume fade step setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Setting the volume change step time of the
volume fade function
7-0
VOLFADE_STEP[7:0]
（Time of change by 0.1 dB）
The volume changes by one step (0.1 dB) of the volume setting register every set time until the changed volume is reached.
As shown below, the volume transition time changes depending on the fade step setting value, volume change amount, and
sampling frequency (fs).
fs：48kHz
[ms]
fs：24kHz
[ms]
Step：
0.125ms
0.125
0.25
0.375
0.5
：
fs：12kHz
[ms]
Step：
0.25ms
0.25
0.5
0.75
1
：
fs：32kHz
[ms]
Step：
0.09375ms
0.09375
0.1875
0.28125
0.375
fs：16kHz
[ms]
fs：8kHz
[ms]
Step：
0.375ms
0.375
0.75
1.125
1.5
：
VOLFADE
_STEP
[7:0]
fs
conversion
Step：
0.0625ms
0.0625
0.125
0.1875
0.25
Step：
0.1875ms
0.1875
0.375
0.5625
0.75
0x00
0x01
0x02
0x03
：
3/fs
6/fs
9/fs
12/fs
：
：
：
：
0x7E
0x7F
0x80
：
381/fs
384/fs
7.9375
8
15.875
16
31.75
32
11.90625
12
23.8125
24
47.625
48
387/fs
：
8.0625
：
16.375
：
32.25
：
12.09375
24.1875
：
48.375
：
：
23.90625
24
765/fs
768/fs
15.9375
16
31.875
32
63.75
64
47.8125
48
95.625
96
0xFE
0xFF
The transition time until the set volume is reached is expressed by the following formula.
Volume transition time
＝｜[ Current dB value] － [New dB value]｜× [VOLFADE_STEP setting value＋1] × 0.0625ms（fs:48kHz）×10
or
＝｜[Current register value] － [New register value]｜× [VOLFADE_STEP setting value＋1] × 0.0625ms（fs:48kHz）
example）
Current dB value（Volume setting register value） ：－51.2dB / 0x100 = 256d
New dB value（Volume setting register value）
VOLFADE_STEP[7:0] setting value
：－25.6dB / 0x200 = 512d
：0x07
Volume transition time ＝ ｜[－51.2] － [－25.6]｜× （7＋1） × 0.0625ms × 10 ＝ 128[ms]
Volume transition time ＝ ｜[256] － [512]｜× （7＋1） × 0.0625ms ＝ 128[ms]
[Note]
・By setting "1" in the VOLFADE_CON register, the changed volume is faded with the set value of this register.
・When the volume is changed in the VOL_MASTL_L/H register and VOL_MASTR_L/H register, it fades at 48kHz or
32kHz depending on the GFS bit of the OUTMODE register.
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Volume fade control register（VOLFADE_CON）
Bank
Address
：0x0，0x1，0x2，0x3
：0x37
Initial value ：0x00
Functions
：Volume fade control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000000
7-1
―
Control fade
0： No use a fade
1： Use a fade
0
VOLFADE_EN
R/W
0
[Note]
When "1" is set, the volume fades to the changed volume with the setting value of the VOLFADE_STEP register.
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Master Volume Lch setting register L（VOL_MASTL_L）
Bank
Address
：0x0，0x1，0x2，0x3
：0x38
Initial value ：0x00
Functions
：Master volume Lch setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
7-0
VOLML_L[7:0]
Master volume Lch setting [7:0]
Master Volume Lch setting register H（VOL_MASTL_H）
Bank
Address
：0x0，0x1，0x2，0x3
：0x39
Initial value ：0x03
Functions
：Master volume Lch setting
Bit
7-2
1-0
Bit name
Unused
Functions
Master volume Lch setting[9:8]
R/W
R
Initial value
000000
11
―
VOLML_H[1:0]
R/W
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・This register is the volume adjustment after mixing. Therefore, the volume can be adjusted regardless of the VOL_SD_CHn
registers.
The volume can be set from MUTE, -76.7 dB to +25.5 dB in 0.1 dB steps.
Volume
[dB]
VOLML_H[9:8]
VOLML_L[7:0]
MUTE
‐76.7
‐76.6
‐76.5
：
0x000
0x001
0x002
0x003
：
‐0.2
‐0.1
0
+0.1
+0.2
：
0x2FE
0x2FF
0x300
0x301
0x302
：
+25.3
+25.4
+25.5
0x3FD
0x3FE
0x3FF
When setting the volume to -12dB, calculate using the following formula and write it to the register.
(-12（Volume dB value） ＋ 76.8) × 10 = 648d = 0x288
Write 0x88 to VOL_MASTL_L [7: 0] and 0x02 to VOL_MASTL_H [9: 8]
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Master Volume Rch setting register L（VOL_MASTR_L）
Bank
Address
：0x0，0x1，0x2，0x3
：0x3A
Initial value ：0x00
Functions
：Master volume Rch setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
7-0
VOLMR_L[7:0]
Master volume Rch setting [7:0]
Master Volume Rch setting register H（VOL_MASTR_H）
Bank
Address
：0x0，0x1，0x2，0x3
：0x3B
Initial value ：0x03
Functions
：Master volume Rch setting
Bit
7-2
1-0
Bit name
Unused
Functions
Master volume Rch setting [9:8]
R/W
R
Initial value
000000
11
―
VOLMR_H[1:0]
R/W
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・This register is the volume adjustment after mixing. Therefore, the volume can be adjusted regardless of the VOL_SD_CHn
registers.
The volume can be set from MUTE, -76.7 dB to +25.5 dB in 0.1 dB steps.
Volume
[dB]
VOLMR_H[9:8]
VOLMR_L[7:0]
MUTE
‐76.7
‐76.6
‐76.5
：
0x000
0x001
0x002
0x003
：
‐0.2
‐0.1
0
+0.1
+0.2
：
0x2FE
0x2FF
0x300
0x301
0x302
：
+25.3
+25.4
+25.5
0x3FD
0x3FE
0x3FF
When setting the volume to -12dB, calculate using the following formula and write it to the register.
(-12（Volume dB value） ＋ 76.8) × 10 = 648d = 0x288
Write 0x88 to VOL_MASTL_L [7: 0] and 0x02 to VOL_MASTL_H [9: 8]
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Master playback control register（PLAYCON_MAST）
Bank
Address
：0x0，0x1，0x2，0x3
：0x3E
Initial value ：0x00
Functions
：Playback start / stop control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000000
7-1
―
SoundGenerator playback control
0
PLAY_SD_MAST
0： stop
1： start
R/W
0
[Note]
・With the channel to be played set (the channel bit of the PLAYCON_SD register is set to “1”), set the PLAY_SD_MAST bit
to “1” to start playback. If the PLAY_SD_MAST bit is set to “0” during playback, playback of all Sound Generator channels
will stop immediately. At this time, the channel bit of the PLAYCON_SD register is not cleared.
・Read the STAT1 register to check the playback status of each channel.
PLAY_SD_MAST
PLAYCON_SD
register
PLAY_SD_CH3
Enable playback of CH3
Enable playback of CH2
Enable playback of CH1
Enable playback of CH0
PLAY_SD_CH2
PLAY_SD_CH1
PLAY_SD_CH0
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ML22120
SoundGenerator0 related registers list （ BANKSEL[3:0]= 0x0 ）
SoundGenerator pitch control register （PITCHCON_SD）
Bank
Address
：0x00
：0x40
Initial value ：0x00
Functions
：Pitch control of CH
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
Pitch control of CH1
0： Apply PIT_SD_CH1_L/H
(control CH1 independently)
1： Apply PIT_SD_CH0_L/H
(control linked to CH0)
―
1
0
PITCHEN_SD_CH1
Unused
R/W
R
0
0
For the pitch combinations of PITCHCON_SD, refer "Pitch settings" in the function description.
[Note]
Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0").
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SoundGenerator volume control register （VOLCON _SD）
Bank
Address
：0x00
：0x41
Initial value ：0x00
Functions
：Volume control of CH
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Volume control of CH3
0： Apply VOL_SD_CH3_L/H
(control CH3 independently)
1： Apply VOL_SD_CH0_L/H
(control linked to CH0)
3
2
VOLEN_SD_CH3
VOLEN_SD_CH2
R/W
R/W
0
0
Volume control of CH2
0： Apply VOL_SD_CH2_L/H
(control CH2 independently)
1： Apply VOL_SD_CH0_L/H
(control linked to CH0)
Volume control of CH1
0： Apply VOL_SD_CH1_L/H
(control CH1 independently)
1： Apply VOL_SD_CH0_L/H
(control linked to CH0)
1
0
VOLEN_SD_CH1
Unused
R/W
R
0
0
―
For volume combinations, refer to "Volume settings" in the function description.
[Note]
Change the setting while playback is stopped(When all the channel bits of the STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0").
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SoundGenerator playback control register （PLAYCON_SD）
Bank
Address
：0x00
：0x42
Initial value ：0xXX
Functions
：Playback control of CH
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Playback control of CH3
0： Keep current state
1： Playback
3
PLAY_SD_CH3
PLAY_SD_CH2
PLAY_SD_CH1
PLAY_SD_CH0
W
W
W
W
x
x
x
x
Playback control of CH2
0： Keep current state
1： Playback
2
Playback control of CH1
0： Keep current state
1： Playback
1
0
Playback control of CH0
0： Keep current state
1： Playback
[Note]
・When the bit of the channel to be played is “1” and the PLAY_SD_MAST bit of the master playback control register is
“1”, playback of the channel is started. Read the STAT1 register to check the playback status of each channel.
・To stop playback, set the volume to MUTE in the VOL_SD_CHn registers, check that the fade has ended in the STAT2
register, and then set the STOPCON_SD register. Set the channel bit to be stopped to "1". Not affect the playback status of
other channels. When the PLAY_SD_MAST bit in the master playback control register is set to “0”, playback of all
channels is stopped immediately.
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SoundGenerator playback stop control register（STOPCON_SD）
Bank
Address
：0x00
：0x43
Initial value ：0xXX
Functions
：Playback stop control of CH
Bit
Bit name
Unused
Functions
R/W
W
Initial value
xxxx
7-4
―
Playback control of CH3
0： Keep current state
1： Stop
3
STOP_SD_CH3
STOP_SD_CH2
STOP_SD_CH1
STOP_SD_CH0
W
W
W
W
x
x
x
x
Playback control of CH2
0： Keep current state
1： Stop
2
Playback control of CH1
0： Keep current state
1： Stop
1
0
Playback control of CH0
0： Keep current state
1： Stop
[Note]
・By setting the bit of the channel to stop playback to “1”, playback of that channel is stopped. Playback can be confirmed
by checking that the channel bit in the STAT1 register is "0".
・To stop playback, set the volume to MUTE in the VOL_SD_CHn registers, check that the fade has ended in the STAT2
register, and then set the STOPCON_SD register. Set the channel bit to be stopped to "1". Not affect the playback status of
other channels. When the PLAY_SD_MAST bit in the master playback control register is set to “0”, playback of all
channels is stopped immediately.
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SoundGenerator CHn pitch setting register L （PIT_SD_CHn_L） n=0 to 3
Bank
：0x00
Address
：0x50,0x52,0x54,0x56
Initial value ：0x00
Functions
：Pitch setting of CH
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
PIT_SD_CH0_L
PIT_SD_CH1_L
PIT_SD_CH2_L
PIT_SD_CH3_L
Address 0x50：Pitch setting of CH0 [7:0]
Address 0x52：Pitch setting of CH1 [7:0]
Address 0x54：Pitch setting of CH2 [7:0]
Address 0x56：Pitch setting of CH3 [7:0]
7-0
SoundGenerator CHn pitch setting register H （PIT_SD_CHn_H） n=0 to 3
Bank
：0x00
Address
：0x51,0x53,0x55,0x57
Initial value ：0x01
Functions
：Pitch setting of CH
Bit
Bit name
Functions
R/W
R
Initial value
000000
7-2
Unused
―
PIT_SD_CH0_H
PIT_SD_CH1_H
PIT_SD_CH2_H
PIT_SD_CH3_H
Address 0x51：Pitch setting of CH0 [9:8]
Address 0x53：Pitch setting of CH1 [9:8]
Address 0x55：Pitch setting of CH2 [9:8]
Address 0x57：Pitch setting of CH3 [9:8]
1-0
R/W
01
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
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The pitch magnification of CH 0 to 1 can be set from 0.0625 times to 3.9960938 times in 0.00390625 times
steps.
The pitch magnification of CH 2 to 3 can be set from 0.0625 times to 1 times in 0.00390625 times steps.
CH0 to1
Pitch
magnification
PIT_SD_CHn_H[9:8]
PIT_SD_CHn_L[7:0]
( n=0~1 )
CH2 to 3
Pitch
magnification
PIT_SD_CHn_H[9:8]
PIT_SD_CHn_L[7:0]
( n=2~3 )
3.9960938
3.9921875
3.9882813
3.984375
3.9804688
3.9765625
3.9726563
3.96875
3.9648438
3.9609375
3.9570313
3.953125
3.9492188
3.9453125
3.9414063
3.9375
0x3FF
0x3FE
0x3FD
0x3FC
0x3FB
0x3FA
0x3F9
0x3F8
0x3F7
0x3F6
0x3F5
0x3F4
0x3F3
0x3F2
0x3F1
0x3F0
：
0x3FF
0x3FE
0x3FD
0x3FC
0x3FB
0x3FA
0x3F9
0x3F8
0x3F7
0x3F6
0x3F5
0x3F4
0x3F3
0x3F2
0x3F1
0x3F0
：
Setting prohibited
(Set to “1”)
：
3
：
0x300
：
0x300
：
2
：
0x200
：
0x200
：
1
：
0x100
：
1
：
0x100
：
0.0625
0x010
0.0625
0x010
Setting prohibited
(Set to “0.0625”)
：
Setting prohibited
(Set to “0.0625”)
：
0x00F
：
0x00F
：
Setting prohibited
(Set to “0.0625”)
Setting prohibited
(Set to “0.0625”)
0x000
0x000
When 0x000 to 0x00F is written, 0x010 is read.
When 0x101 to 0x3FF is written to channels 2 to 3, 0x100 is read.
To set the pitch magnification to 1.1875 times, use the following formula to calculate and write to the register.
1.1875（pitch magnification） × 256 = 304d = 0x130
Write 0x30 to PIT_SD_CHn_L[7:0]，and 0x01 to PIT_SD_CHn_H[9:8].
[Note]
・For details on how to set the pitch for each channel, refer "Pitch settings" in the function description.
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Sound Generator CHn volume setting register L（VOL_SD_CHn_L） n=0 to 3
Bank
：0x00
Address
：0x60,0x62,0x64,0x66
Initial value ：0x00
Functions
：Volume setting of CH
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
VOL_SD_CH0_L[7:0] Address 0x60：Volume setting of CH0 [7:0]
VOL_SD_CH1_L[7:0] Address 0x62：Volume setting of CH1 [7:0]
VOL_SD_CH2_L[7:0] Address 0x64：Volume setting of CH2 [7:0]
VOL_SD_CH3_L[7:0] Address 0x66：Volume setting of CH3 [7:0]
7-0
Sound Generator CHn volume setting register H（VOL_SD_CHn_H） n=0 to 3
Bank
：0x00
Address
：0x61,0x63,0x65,0x67
Initial value ：0x03
Functions
：Volume setting of CH
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000000
7-2
―
VOL_SD_CH0_H[7:0] Address 0x61：Volume setting of CH0 [9:8]
VOL_SD_CH1_H[7:0] Address 0x63：Volume setting of CH1 [9:8]
VOL_SD_CH2_H[7:0] Address 0x65：Volume setting of CH2 [9:8]
VOL_SD_CH3_H[7:0] Address 0x67：Volume setting of CH3 [9:8]
1-0
R/W
11
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・For details on how to set the volume for each channel, refer "Volume settings" in the function description.
The volume can be set from MUTE, -76.7 dB to +25.5 dB in 0.1 dB steps.
VOL_SD_CHn_H[9:8]
VOL_SD_CHn_L[7:0]
Volume
[dB]
( n=0 to 3 )
MUTE
‐76.7
‐76.6
‐76.5
：
0x000
0x001
0x002
0x003
：
‐0.2
‐0.1
0
+0.1
+0.2
：
0x2FE
0x2FF
0x300
0x301
0x302
：
+25.3
+25.4
+25.5
0x3FD
0x3FE
0x3FF
When setting the volume to -12dB, calculate using the following formula and write it to the register.
(-12（Volume dB value） ＋ 76.8) × 10 = 648d = 0x288
Write 0x88 to VOL_SD_CHn_L[7: 0] and 0x02 to VOL_SD_CHn_H[9: 8]
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SoundGenerator1 related registers list（BANKSEL[3:0]= 0x 1）
SoundGenerator phrase setting register CH 0（PHRASE_SD_CH0）
Bank
Address
：0x01
：0x40
Initial value ：0x00
Functions
：Phrase setting of CH 0
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00
7-6
―
Specify the playback phrase for CH 0
000000： Specify phrase 0
000001： Specify phrase 1
：
5-0
PHR_CH0[5:0]
R/W
000000
111110： Specify phrase 62
111111： Specify phrase 63
SoundGenerator phrase setting register CH 1（PHRASE_SD_CH1）
Bank
Address
：0x01
：0x41
Initial value ：0x00
Functions
：Phrase setting of CH 1
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00
7-6
―
Specify the playback phrase for CH 1
000000： Specify phrase 0
000001： Specify phrase 1
：
5-0
PHR_CH1[5:0]
R/W
000000
111110： Specify phrase 62
111111： Specify phrase 63
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SoundGenerator phrase setting register CH 2（PHRASE_SD_CH2）
Bank
Address
：0x01
：0x42
Initial value ：0x00
Functions
：Phrase setting of CH 2
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00
7-6
―
Specify the playback phrase for CH 2
000000： Specify phrase 0
000001： Specify phrase 1
：
5-0
PHR_CH2[5:0]
R/W
000000
111110： Specify phrase 62
111111： Specify phrase 63
SoundGenerator phrase setting register CH 3（PHRASE_SD_CH3）
Bank
Address
：0x01
：0x43
Initial value ：0x00
Functions
：Phrase setting of CH 3
Bit
Bit name
Unused
Functions
R/W
R
Initial value
00
7-6
―
Specify the playback phrase for CH 3
000000： Specify phrase 0
000001： Specify phrase 1
：
5-0
PHR_CH3[5:0]
R/W
000000
111110： Specify phrase 62
111111： Specify phrase 63
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SoundGenerator loop playback control register（LOOPCON_SD）
Bank
Address
：0x01
：0x48
Initial value ：0x0F
Functions
：loop playback control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
0000
7-4
―
Control loop playback of CH3
0： once playback
3
LOOP_SD_CH3
LOOP_SD_CH2
LOOP_SD_CH1
LOOP_SD_CH0
R/W
R/W
R/W
R/W
1
1
1
1
1： loop playback
Control loop playback of CH2
0： once playback
2
1： loop playback
Control loop playback of CH1
0： once playback
1
0
1： loop playback
Control loop playback of CH0
0： once playback
1： loop playback
[Note]
・To play once, set "0" to LOOP_SD_CHn bit of this register, and set PLAY_SD_CHn bit of the PLAYCON_SD register.
And set the PLAY_SD_MAST bit in the PLAYCON_MAST register to "1". When play once is ended, the
PLAY_SD_CHn bit in the PLAYCON_SD register is automatically cleared, but the PLAY_SD_MAST bit is not cleared.
Not affect the playback status of other channels.
・To start loop playback, set "1" to LOOP_SD_CHn bit of this register, and set PLAY_SD_CHn bit of PLAYCON_SD
register. And set the PLAY_SD_MAST bit in the PLAYCON_MAST register to "1".
・To stop loop playback, set the LOOP_SD_CHn bit of this register to “0” to switch to once playback, stop after play once.
At this time as well, when play once is ended, the PLAY_SD_CHn bit in the PLAYCON_SD register is automatically
cleared, but the PLAY_SD_MAST bit in the PLAYCON_MAST register is not cleared. Not affect the playback status of
other channels.
・To stop playback immediately, set the volume to MUTE in the VOL_SD_CHn registers. Then, after confirming that the
fade has ended in the STAT2 register, set STOP_SD_CHn bit in the STOPCON_SD register to “1”. Not affect the
playback status of other channels.
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EqualizerLch related registers list（BANKSEL[3:0]=0x 2）
EQ Lch equalizer control register （EQLCON）
Bank
Address
：0x02
：0x40
Initial value ：0x00
Functions
：EQ Lch enable control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Band4 equalizer setting
0：disable
4
3
2
1
0
EQL4EN
EQL3EN
EQL2EN
EQL1EN
EQL0EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1：enable
Band3 equalizer setting
0：disable
1：enable
Band2 equalizer setting
0：disable
1：enable
Band1 equalizer setting
0：disable
1：enable
Band0 equalizer setting
0：disable
1：enable
[Note]
Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
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EQ Lch Band n gain setting register（EQLGAINn） n=0 to 4
Bank
：0x02
Address
：0x41,0x42,0x43,0x44,0x45
Initial value ：0xE7
Functions
：EQ Lch Band n gain setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0xE7
EQLGAIN0
EQLGAIN1
EQLGAIN2
EQLGAIN3
EQLGAIN4
Address 0x41：Band 0 gain setting [7:0]
Address 0x42：Band 1 gain setting [7:0]
Address 0x43：Band 2 gain setting [7:0]
Address 0x44：Band 3 gain setting [7:0]
Address 0x45：Band 4 gain setting [7:0]
7-0
The gain can be set in 0.5 dB steps from + 12 dB to MUTE.
EQLGAINn[7:0] ( n=0~4 )
Gain
0xFF
0xFE
+12.0dB
+11.5dB
0xFD ~ 0xE9
~( +0.5dB step )~
0xE8
0xE7
0xE6
+0.5dB
0dB
-0.5dB
0xE5 ~ 0x5A
~( +0.5dB step )~
0.59
0x58
-71.0dB
-71.5dB
0x57 ~ 0x00
MUTE
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EQ Lch Band n A0 coefficient setting register L（EQLBANDnA0L） n=0 to 4
Bank
：0x02
Address
：0x46,0x4A,0x4E,0x52,0x56
Initial value ：0x00
Functions
：EQ Lch Band n A0 coefficien setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
EQLBAND0A0L
EQLBAND1A0L
EQLBAND2A0L
EQLBAND3A0L
EQLBAND4A0L
Address 0x46：Band 0 A0 coefficient setting [7:0]
Address 0x4A：Band 1 A0 coefficient setting [7:0]
Address 0x4E：Band 2 A0 coefficient setting [7:0]
Address 0x52：Band 3 A0 coefficient setting [7:0]
Address 0x56：Band 4 A0 coefficient setting [7:0]
7-0
EQ Lch Band n A0 coefficient setting register H（EQLBANDnA0H） n=0 to 4
Bank
：0x02
Address
：0x47,0x4B,0x4F,0x53,0x57
Initial value ：0x00
Functions
：EQ Lch Band n A0 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Address 0x47：Band 0 A0 coefficient setting [15:8]
Address 0x4B：Band 1 A0 coefficient setting [15:8]
Address 0x4F：Band 2 A0 coefficient setting [15:8]
Address 0x53：Band 3 A0 coefficient setting [15:8]
Address 0x57：Band 4 A0 coefficient setting [15:8]
EQLBAND0A0H
EQLBAND1A0H
EQLBAND2A0H
EQLBAND3A0H
EQLBAND4A0H
7-0
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・By setting the EQLBANDnA0L/H register and EQLBANDnA1L/H register, the center frequency and bandwidth of the
equalizer can be set arbitrarily.
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
・Generate the setting value using the dedicated tool. Set that value in this register.
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EQ Lch Band n A1 coefficient setting register L（EQLBANDnA1L） n=0 to 4
Bank
：0x02
Address
：0x48,0x4C,0x50,0x54,0x58
Initial value ：0x00
Functions
：EQ Lch Band n A1 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Address 0x48：Band 0 A1 coefficient setting [7:0]
Address 0x4C：Band 1 A1 coefficient setting [7:0]
Address 0x50：Band 2 A1 coefficient setting [7:0]
Address 0x54：Band 3 A1 coefficient setting [7:0]
Address 0x58：Band 4 A1 coefficient setting [7:0]
EQLBAND0A1L
EQLBAND1A1L
EQLBAND2A1L
EQLBAND3A1L
EQLBAND4A1L
7-0
EQ Lch Band n A1 coefficient setting register H（EQLBANDnA1H） n=0 to 4
Bank
：0x02
Address
：0x49,0x4D,0x51,0x55,0x59
Initial value ：0x00
Functions
：EQ Lch Band n A1 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
EQLBAND0A1H
EQLBAND1A1H
EQLBAND2A1H
EQLBAND3A1H
EQLBAND4A1H
Address 0x49：Band 0 A1 coefficient setting [15:8]
Address 0x4D：Band 1 A1 coefficient setting [15:8]
Address 0x51：Band 2 A1 coefficient setting [15:8]
Address 0x55：Band 3 A1 coefficient setting [15:8]
Address 0x59：Band 4 A1 coefficient setting [15:8]
7-0
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・By setting the EQLBANDnA0L/H register and EQLBANDnA1L/H register, the center frequency and bandwidth of the
equalizer can be set arbitrarily.
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
・Generate the setting value using the dedicated tool. Set that value in this register.
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EqualizerRch related registers list（BANKSEL[3:0]=0x 3）
EQ Rch equalizer control register （EQRCON）
Bank
Address
：0x03
：0x40
Initial value ：0x00
Functions
：EQ Rch enable control
Bit
Bit name
Unused
Functions
R/W
R
Initial value
000
7-5
―
Band4 equalizer setting
0：disable
4
3
2
1
0
EQR4EN
EQR3EN
EQR2EN
EQR1EN
EQR0EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1：enable
Band3 equalizer setting
0：disable
1：enable
Band2 equalizer setting
0：disable
1：enable
Band1 equalizer setting
0：disable
1：enable
Band0 equalizer setting
0：disable
1：enable
[Note]
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
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EQ Rch Band n gain setting register（EQRGAINn） n=0 to 4
Bank
：0x03
Address
：0x41,0x42,0x43,0x44,0x45
Initial value ：0xE7
Functions
：EQ Rch Band n gain settng
Bit
Bit name
Functions
R/W
R/W
Initial value
0xE7
EQRGAIN0
EQRGAIN1
EQRGAIN2
EQRGAIN3
EQRGAIN4
Address 0x41：Band 0 gain setting [7:0]
Address 0x42：Band 1 gain setting [7:0]
Address 0x43：Band 2 gain setting [7:0]
Address 0x44：Band 3 gain setting [7:0]
Address 0x45：Band 4 gain setting [7:0]
7-0
The gain can be set in 0.5 dB steps from + 12 dB to MUTE.
EQRGAINn[7:0] ( n=0~4 )
Gain
0xFF
0xFE
+12.0dB
+11.5dB
0xFD ~ 0xE9
~( +0.5dB step )~
0xE8
0xE7
0xE6
+0.5dB
0dB
-0.5dB
0xE5 ~ 0x5A
~( +0.5dB step )~
0.59
0x58
-71.0dB
-71.5dB
0x57 ~ 0x00
MUTE
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EQ Rch Band n A0 coefficient setting register L（EQRBANDnA0L） n=0 to 4
Bank
：0x03
Address
：0x46,0x4A,0x4E,0x52,0x56
Initial value ：0x00
Functions
：EQ Rch Band n A0 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
EQRBAND0A0L
EQRBAND1A0L
EQRBAND2A0L
EQRBAND3A0L
EQRBAND4A0L
Address 0x46：Band 0 A0 coefficient setting [7:0]
Address 0x4A：Band 1 A0 coefficient setting [7:0]
Address 0x4E：Band 2 A0 coefficient setting [7:0]
Address 0x52：Band 3 A0 coefficient setting [7:0]
Address 0x56：Band 4 A0 coefficient setting [7:0]
7-0
EQ Rch Band n A0 coefficient setting register H（EQRBANDnA0H） n=0 to 4
Bank
：0x03
Address
：0x47,0x4B,0x4F,0x53,0x57
Initial value ：0x00
Functions
：EQ Rch Band n A0 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Address 0x47：Band 0 A0 coefficient setting [15:8]
Address 0x4B：Band 0 A0 coefficient setting [15:8]
Address 0x4F：Band 0 A0 coefficient setting [15:8]
Address 0x53：Band 0 A0 coefficient setting [15:8]
Address 0x57：Band 0 A0 coefficient setting [15:8]
EQRBAND0A0H
EQRBAND1A0H
EQRBAND2A0H
EQRBAND3A0H
EQRBAND4A0H
7-0
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・By setting the EQRBANDnA0L/H register and EQRBANDnA1L/H register, the center frequency and bandwidth of the
equalizer can be set arbitrarily.
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
・Generate the setting value using the dedicated tool. Set that value in this register.
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EQ Rch Band n A1 coefficient setting register L（EQRBANDnA1L） n=0 to 4
Bank
：0x03
Address
：0x48,0x4C,0x50,0x54,0x58
Initial value ：0x00
Functions
：EQ Rch Band n A1 coefficient L setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
Address 0x48：Band 0 A1 coefficient setting [7:0]
Address 0x4C：Band 1 A1 coefficient setting [7:0]
Address 0x50：Band 2 A1 coefficient setting [7:0]
Address 0x54：Band 3 A1 coefficient setting [7:0]
Address 0x58：Band 4 A1 coefficient setting [7:0]
EQRBAND0A1L
EQRBAND1A1L
EQRBAND2A1L
EQRBAND3A1L
EQRBAND4A1L
7-0
EQ Rch Band n A1 coefficient setting register H（EQRBANDnA1H） n=0 to 4
Bank
：0x03
Address
：0x49,0x4D,0x51,0x55,0x59
Initial value ：0x00
Functions
：EQ Rch Band n A1 coefficient setting
Bit
Bit name
Functions
R/W
R/W
Initial value
0x00
EQRBAND0A1H
EQRBAND1A1H
EQRBAND2A1H
EQRBAND3A1H
EQRBAND4A1H
Address 0x49：Band 0 A1 coefficient setting [15:8]
Address 0x4D：Band 1 A1 coefficient setting [15:8]
Address 0x51：Band 2 A1 coefficient setting [15:8]
Address 0x55：Band 3 A1 coefficient setting [15:8]
Address 0x59：Band 4 A1 coefficient setting [15:8]
7-0
[Note]
・The setting register L is updated by writing to the setting register H. To update the setting register L, write to the setting
register H.
・By setting the EQRBANDnA0L/H register and EQRBANDnA1L/H register, the center frequency and bandwidth of the
equalizer can be set arbitrarily.
・Change the setting while playback is stopped(When all the channel bits of STAT1 register are "0" or when the
PLAY_SD_MAST bit of the PLAYCON_MAST register is "0" and the OUT_EN bit of the OUTCON register is "0").
・Generate the setting value using the dedicated tool. Set that value in this register.
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■ Application Circuit
● Clock Synchronous Serial Interface
Host
MCU
RESETB
C8
Speaker
Amplifier
LOUT
Speaker
CSB
SCK
SO
CSB/SCL
SCK/SDA0
SI/SDA
SI
SO/SAD1
C7
SG
STATUS0
STATUS1_MCLKO
STATUS2*1
ERCSB
ERSCK
ERSO
Serial
FLASH
ERSI
Speaker
Amplifier
LRCLK
BCLK
EROFF
SAI_OUT
Speaker
TEST0
IOVDD
DVDD
VDDL
C1
XT
4.096MHz
C2
XTB
DGND
*1：24PIN version has no pin
Pin
Symbol
Recommended Constant
DVDD
DVDD
IOVDD
VDDL
C3
C4
C5
C6
C7
C8
3.3μF±20%
0.1μF±20%
1μF±20%
1uF±20%
SG
0.1uF±20%
0.1uF±20%
LOUT
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● I2C Interface (Slave)
Host
MCU
RESETB
C8
Speaker
Amplifier
LOUT
Speaker
CSB/SCL
SI/SDA
SCL
SDA
SO/SAD1*1
SCK/SAD0*1
C7
SG
STATUS0
STATUS1_MCLKO
STATUS2*2
ERCSB
ERSCK
ERSO
Serial
FLASH
ERSI
Speaker
Amplifier
LRCLK
BCLK
EROFF
SAI_OUT
Speaker
TEST0
IOVDD
DVDD
VDDL
C1
XT
4.096MHz
C2
XTB
DGND
*1：When 100_0101 is selected as the slave address
*2：24PIN version has no pin
Pin
DVDD
DVDD
IOVDD
VDDL
Symbol
C3
Recommended Constant
3.3μF±20%
C4
0.1μF±20%
C5
1μF±20%
C6
1uF±20%
SG
C7
0.1uF±20%
LOUT
C8
0.1uF±20%
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■ Recommended ceramic resonator
Recommended ceramic resonators are shown below.
● MURATA Corporation
Frequency [Hz]
4M
Product Name
Built-in load capacity [pF]
39
CSTCR4M00G55B-R0
CSTCR4M09G55B-R0
4.096M
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■ Package Dimensions
● ML22120TB （32pin TQFP）
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of layers of
a substrate.
PCB
（W/L/t＝ 76.2 / 114.3 / 1.6 （mm））
PCB Layer
Air cooling condition
JEDEC 4 layers
No wind（0m/sec）
59.04 [oC /W]
0.06 [W]
Heat resistance value（θJa）
Chip power consumption PMax OutputPower
The TjMax of this LSI is 130 oC. TjMax is expressed by the following formula.
TjMax=TaMax + θJa×PMax
The mounting area for package lead soldering to PC boards is shown on the next page.
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Figure of reference
116/122
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● ML22120GD （32pin WQFN）
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of layers of
a substrate.
PCB
（W/L/t＝ 76.2 / 114.3 / 1.6 （mm））
PCB Layer
Air cooling condition
JEDEC 4 layers
No wind（0m/sec）
31.76 [oC /W]
0.06 [W]
Heat resistance value（θJa）
Chip power consumption PMax OutputPower
The TjMax of this LSI is 130 oC. TjMax is expressed by the following formula.
TjMax=TaMax + θJa×PMax
The heat sink area of the LSI solder open or GND on the board.
The mounting area for package lead soldering to PC boards is shown on the next page.
117/122
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Figure of reference
118/122
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● ML22120GP （24pin WQFN）
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of layers of
a substrate.
PCB
（W/L/t＝ 76.2 / 114.3 / 1.6 （mm））
PCB Layer
Air cooling condition
JEDEC 4 layers
No wind（0m/sec）
36.53 [oC /W]
0.06 [W]
Heat resistance value（θJa）
Chip power consumption PMax OutputPower
The TjMax of this LSI is 130 oC. TjMax is expressed by the following formula.
TjMax=TaMax + θJa×PMax
The heat sink area of the LSI solder open or GND on the board.
The mounting area for package lead soldering to PC boards is shown on the next page.
119/122
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Figure of reference
120/122
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■ Revision history
Page
Previous
edition
Document No.
Date
Description
Current
edition
FEDL22120-01
Mar 1, 2023
-
-
Formal 1st edition.
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Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Semiconductor Products, refer to the latest product information (data sheets, user’s manuals, application
notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within
the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of
or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without
observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and
malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down or
malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the
derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.
You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other
use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be
taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any
losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related
information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology
or any third party with respect to LAPIS Technology Products or the information contained in this document (including but
not limited to, the Product data, drawings, charts, programs, algorithms, and application examples, etc.). Therefore LAPIS
Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out
of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications
requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and
must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic
lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc.
LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by using
the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability, such
as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
４
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,
LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility
for any damages arising from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws
or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export
Administration Regulations and the Foreign Exchange and Foreign Trade Act.
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS
Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2023 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
122/122
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