BU9882-E2_技术文档

TECHNICAL NOTE

Double-cell Memory for Plug & Play

EDID Memory

BR24C21/F/FJ/FV, BU9882/F/FV-W

BR24C21/F/FJ/FV

●Description

The BR24C21 series ICs are serial EEPROMs that support DDC1^TM/DDC2^TMinterfaces for Plug and Play displays.

●Features

1) Compatible with both DDC1^TM/DDC2^TM

2) Operating voltage range: 2.5V to 5.5V

3) Page write function: 8bytes

4) Low power consumption

Active (at 5V)

: 1.5mA (typ)

Stand-by (at 5V) : 0.1μA (typ)

5) Address auto increment function during Read operation

6) Data security

Write enable feature (VCLK)

Write protection at low Vcc

7) Various packages available: DIP-T8 / SOP8 / SOP-J8 / SSOP-B8

8) Initial data=FFh

9) Data retention: 10years

10) Rewriting possible up to 100,000 times

●Absolute maximum ratings (Ta=25℃)

●Recommended operating conditions

Parameter

Symbol

VCC

Rating

-0.3～+6.5

Unit

V

Parameter

Supply Voltage

Input Voltage

Symbol

VCC

Rating

2.5～5.5

0～VCC

Unit

V

Supply Voltage

800 (DIP-T8)

450 (SOP8)

450 (SOP-J8)

*1

*2

*3

VIN

V

Power Dissipation

Pd

mW

350 (SSOP-B8) *4

Storage

Temperature

Operating

Temperature

Terminal Voltage

Tstg

-65～+125

℃

●Memory cell characteristics

Topr

-

-40～+85

℃

Limits

Typ. Max.

Parameter

Min.

Unit

-0.3～VCC+0.3

V

Write/Erase Cycle

Data Retention

100,000

10

-

Cycle

Year

* Reduce by 8.0 mW/°C over 25°C (*1), 4.5mW/℃ (*2,3), and 3.5mW/℃ (*4)

Ver.B Oct.2005

●Electrical characteristics - DC (Unless otherwise specified, Ta=-40℃～+85℃､VCC=2.5V～5.5V)

Limits

Parameter

Symbol

Unit

Condition

Min.

0.7VCC

－

Typ.

－

10

Max.

－

VIH1

VIL1

VIH2

VIL2

VIL3

VOL

ILI

V

SCL, SDA

VCLK

“H” Input Voltage 1

“L” Input Voltage 1

“H” Input Voltage 2

“L” Input Voltage 2

“L” Input Voltage 3

“L” Output Voltage

Input Leakage Current

Output Leakage Current

Operating Current

Standby Current

0.3VCC

－

2.0

－

V

0.8

V

VCLK, VCC≧4.0V

－

0.2VCC

0.4

V

VCLK, VCC＜4.0V

－

V

SDA, IOL=3.0mA

-1

1

μA

mA

μA

SCL, VCLK, VIN=0V～VCC

SDA, VOUT=0V～VCC

VCC=5.5V, fSCL=400kHz

VCC=5.5V, SDA=SCL=VCC,VCLK=GND *1

ILO

-1

1

ICC

ISB

－

3.0

－

100

Note: This IC is not designed to be radiation-resistant

*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the

VCLK pin. After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the

operating current flows.

Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.

●Block diagram

1 Kbit EEPROM ARRAY

N.C. 1

8

7

6

5

VCC

8bit

7bit

ADDRESS

DECODER

SLAVE・WORD

DATA

2

VCLK

SCL

SDA

N.C.

7bit

ADDRESS REGISTER

REGISTER

START

CONTROL LOGIC

STOP

N.C. 3

GND 4

ACK

HIGH VOLTAGE

VCC LEVEL DETECT

Fig.1 Block Diagram

●Pin layout diagram

VCC

VCLK

SCL

SDA

Pin Name

I/O

－

IN

Functions

VCC

GND

N.C.

SCL

Power Supply

Ground （0V）

No Connection

(入力)

BR24C21

BR24C21F

BR24C21FJ

BR24C21FV

Serial Clock Input for Bi-directional Mode

Slave and Word Address,

SDA

IN/OUT

IN

Serial Data Input, Serial Data Output *1

Clock Input (Transmit-Only Mode)

Write Enable (Bi-directional Mode)

VCLK

N.C.

GND

*1 An open drain output requires a pull-up resistor.

Fig.2 Pin Layout

2/16

●Electrical characteristics - AC (Unless otherwise specified, Ta=-40℃～+85℃,VCC=2.5V～5.5V)

Fast-mode

Standard-mode

VCC=2.5V～5.5V

Parameter

Symbol

Unit

Min. Typ. Max. Min. Typ. Max.

Clock Frequency

fSCL

tHIGH

tLOW

tR

－

0.6

1.3

－

400

－

4.0

4.7

－

100 kHz

Data Clock High Period

Data Clock Low Period

SDA and SCL Rise Time

SDA and SCL Fall Time

Start Condition Hold Time

Start Condition Setup Time

Input Data Hold Time

－

μs

ns

－

0.3

－

1.0

0.3

－

tF

－

tHD:STA 0.6

tSU:STA 0.6

4.0

4.7

0

－

tHD:DAT

tSU:DAT 100

tPD

tSU:STO 0.6

0

－

Input Data Setup Time

Output Data Delay Time(SCL)

Stop Condition Setup Time

Bus Free Time

－

250

－

ns

－

0.9

－

3.5

－

μs

ms

μs

4.0

4.7

－

tBUF

tWR

tI

1.3

－

Write Cycle Time

10

0.1

10

0.1

Noise Spike Width (SDA and SCL)

－

AC OPERATING CHARACTERISTICS (Transmit-Only Mode)

Output Data Delay Time(VCLK)

VCLK High Period

tVPD

－

1.0

－

4.0

4.7

0

－

2.0

－

μs

tVHIGH 0.6

VCLK Low Period

tVLOW

tVSU

tVHD

tVHZ

tVPU

tVI

1.3

0

－

VCLK Setup Time

－

VCLK Hold Time

0.6

－

0

－

4.0

－

0

－

Mode Transition Time

Transmit-Only Powerup Time

Noise Spike Width (VCLK)

0.5

－

1.0

－

0.1

－

0.1

●Synchronous data timing

t_R

t_F

t_HIGH

SCL

t_LOW

t

_HD:DAT

t

_SU:DAT

t_HD:STA

SDA

D0

ACK

SDA

(IN)

tWR

STOP CONDITION

WRITE DATA(n)

t_BUF

t_PD

START CONDITION

SDA

(OUT)

Fig.4 Write Cycle Timing

START BIT

STOP BIT

SCL

SDA

tHD:STA

t^SU:STO

tSU:STA

SDA

STOP BIT

START BIT

VCLK

Fig.3 Synchronous Data Timing

・SDA data is latched into the chip at the rising edge of the SCL clock.

・Output data toggles at the falling edge of the SCL clock.

WRITE COMMAND

t_VHD

t_VSU

Fig.5 Write Enable Timing

3/16

●Transmit-only mode

・After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the

clock to the VCLK pin.

・When the power is on, the SCL pin needs to be set to VCC(High level).

・SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After

power on, the output data is as follows:

00h address data → 01h address data → 02h address data → …

The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.

When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)

・In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)

・The read operation is in Transmit-Only Mode and can be started after the power is stabilized.

tVHIGH tVLOW

Vcc

SCL

VCLK

tVPD

9

1

10

SDA

D1

D0

D7

D6

VCLK

SDA

ｔVPU

ADDRESS

DATA

n

NULL BIT

DATA=1

ADDRESS n+1

DATA

D7

D6

D5

D4

D3

00h ADDRESS DATA

Fig.7 Null Bit

Fig.6 Transmit Only Mode

●Bi-directional mode

○Bi-directional Mode and Recovery Function

・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to

Low transition at the SCL pin, while the state of SDA is at high-impedance.

・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK

counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode

(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal

to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.

・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional

Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only

way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an

Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for

Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is

input, it is possible to revert to Transmit-Only Mode.

・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.

B i - d i r e c t i o n a l

Bi-directional

B i - d i r e c t i o n a l

Transmit-oOnly

Bi-directional

B i - d i r e c t i o n a l

p a r m a n e n t l y

parmanently

T r a n s m i t - o n l y

T r a nTr

s

an

m

smit

i

-

t

O

-

nl

O

y

n l y

T r a n s m i t - o n l y

Transmit-only

T r a n s i t i o n M o d e w i t h p o s s i b i l i t y

Transition Mode with possibility to

ＭＯＤＥ

t o r e t u n e t o T r a n s m i t - O n l y M o d e

return to Transmit-Only Mode

ｎ＜１２８

ｎ

１２７１２８１２９

１

２

３

４

１

２

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

A D D R E S S 0 0 h

ADDRESS 00h

ｔＶＨＺ

Ｄ７Ｄ６Ｄ５Ｄ４

Ｓ

１

０

１

０

＊

Ｒ/ＷＡＣＫ

*Don’t care

Fig.8 Recovery Mode

Fig.9 Mode Change

4/16

○Bi-directional Mode

START Condition

・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.

・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to

any commands until this condition has been met.

(See Fig. 3 Synchronous Data Timing)

STOP Condition

・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL

is High.

・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.

・The STOP condition is also used to place the device into standby power mode after read sequences.

・A STOP condition can only be issued after the transmitting device has released the bus.

(See Fig.3 Synchronous Data Timing)

Device Addressing

・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most

significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as

“1010.”

・The next three bits of the slave address are inconsequential.

・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.

When set to “0”, a WRITE operation is initiated.

R/W set to "0" ・・・・・・・・ WRITE (This bit is also set to "0" for random read operation)

R/W set to "1" ・・・・・・・・ READ

1010

＊

R/W

＊：Don’t care

○Write Protect Function

・Write Enable (VCLK)

When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting

VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.（See

Fig.5 Write Enable Timing）

Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.

●Bidirectional mode command

○Byte Write

S

T

W

R

I

T

E

S

T

O

P

A

When the Master generates a STOP condition, the

BR24C21/F/FJ/FV begins the internal write cycle

to the nonvolatile array.

SLAVE

WORD

ADDRESS

R

DATA

ADDRESS

T

SDA

LINE

WA

0

WA

6

1

0

1

0

*

D7

D0

R

/

W

A

C

K

A

C

K

A

C

K

VCLK

*:Don’t care

Fig.10 Byte Write Cycle Timing

○Page Write

If the Master transmits the next data instead of

generating a STOP condition during the byte write

cycle, the BR24C21/F/FJ/FV transfers from byte

write function to page write function. After receipt

of each word, the three lower order address bits

are internally incremented by one, while the high

order four bits of the word address remains

constant.

S

W

R

I

S

T

A

R

T

O

P

SLAVE

WORD

T

E

DATA(n)

DATA(n+7)

ADDRESS

SDA

LINE

WA

0

＊＊＊

1 0 1 0

D7

D0

*

6

R A

A

C

K

A

C

K

A

C

K

/ C

WK

If the master transmits more than eight words, prior

to generating the STOP condition, the address

counter will “roll over,” and the previous

transmitted data will be overwritten.

VCLK

*:Don’t care

Fig.11 Page Write Cycle Timing

5/16

○Current Read

The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,

incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will

access data from address “n+1” and increment the current address counter. If the last accessed address is address

”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an

Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of

data. At this point, the device discontinues transmission.

(See Fig.14 Sequential Read Cycle Timing）

S

R

E

A

D

S

T

O

P

T

A

R

T

SLAVE

ADRESS

DATA

SDA

LINE

＊＊＊

1

0

1

0

D7

D0

R

A

C

K

A

C

K

/

W

*:Don’t care

Fig.12 Current Read Cycle Timing

○Random Read

The Random read operation allows the Master to access any memory location. This operation involves a two-step

process. First, the Master issues a Write command that includes the START condition and the Slave address field (with

R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address counter of

the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the Master, the

Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.” The device will

respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the Master does not

acknowledge the transmission but does generate the STOP condition, the IC will discontinue transmission.

S

T

A

R

T

W

R

I

T

E

S

T

A

R

T

R

E

A

D

S

T

O

P

SLAVE

ADDRESS

WORD

ADDRESS（ｎ）

SLAVE

ADDRESS

DATA(n)

SDA

LINE

WA

0

WA

6

1

0

1

0

*

1

0

1

0

*

D7

D0

A

C

K

R

/

W K

A

C

A

C

K

R

/

W K

A

C

*:Don’t care

Fig.13 Random Read Cycle Timing

○Sequential Read

･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read

operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits

in the address counter are incremented, allowing the entire array to be read during a single operation. When the

counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.

･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device

discontinues transmission.

･The sequential Read operation can be performed with both Current Read and Random Read.

S

R

S

T

O

P

T

A

R

T

E

A

D

SLAVE

ADDRESS

DATA(n)

DATA(n+x)

SDA

LINE

1

0

1

0

*

D7

D0

D7

D0

R

/

W K

A

C

A

C

K

A

C

K

A

C

K

*:Don’t care

Fig.14 Sequential Read Cycle Timing

(Current Read)

6/16

BU9882/F/FV-W

●Description

The BU9882 ICs are dual port EEPROMs compatible with the DDC2^TM. 2 independent ports allow 2 EDID channels to be

read simultaneously.

●Features

1) Designed for use with DDC2^TM

2) 2-port simultaneous read function

3) Operating voltage range: 2.5V-5.5V

4) Page write function: 8bytes

5) Low power consumption:

Active (at 5V) : 1.5mA(typ)

Stand-by (at 5V) : 0.1μA(typ)

6) Data security

Write protection with WP

Write protection at low power supply voltage

7) Various package types available: DIP14 / SOP14 / SSOP14

8) Initial data: FFh

9) Data retention: 10years

10) Rewriting possible up to 100,000 times

●Absolute maximum ratings

●Recommended operating conditions

Parameter

Symbol

VCC

Rating

Unit

V

Parameter

Supply Voltage

Input Voltage

Symbol

VCC

Rating

2.5～5.5

Unit

V

Supply Voltage

-0.3～+6.5

1

*

2

*

3

*

950 (DIP14)

VIN

0～VCC+1.0

V

Power Dissipation

Pd

450 (SOP14)

350 (SSOP14)

mW

Storage

Temperature

Operating

Temperature

Terminal Voltage

●Memory cell characteristics

Tstg

-65～+125

℃

Limits

Topr

-

-40～+85

℃

Parameter

Min.

Unit

Typ. Max.

4

*

-0.3～VCC+1.0

V

Write/Erase Cycle 100,000

-

Cycle

Year

* Reduce by 9.5 mW/°C over 25°C (*1), 4.5mW/℃(*2), 3.5mW/℃(*3).

Data Retention

10

*4 6.8V (Max.)

●Electrical characteristics – DC (Unless otherwise specified, Ta=-40℃～+85℃,VCC=2.5V～5.5V)

Limits

Parameter

Symbol

Unit

Condition

Min.

2.0

－

Typ.

－

Max.

－

VIH1

VIL1

VIL2

V

“H” Input Voltage 1

－

0.8

VCC≧4.0V

VCC＜4.0V

“L” Input Voltage 1

“L” Input Voltage 2

“L” output Voltage

－

0.2VCC

0.4

VOL1

－

SDA_PC0/1, IOL=3.0mA *１

SCL_PC0/1,DDCENA, BANKSEL,

Input Leakage Current 1

Input Leakage Current 2

Output Leakage Current

ILI1

ILI2

ILO

-1

－

1

50

1

μA

VIN=0V～VCC+1.0

___

WP

SDA_PC0/1,SCL/SDA_MON(DDCENA=GND),

VOUT=0V～VCC+1.0

fSCL=400kHz, VCC=5.5V

tWR=10ms

Operating Current

Standby Current

ICC

ISB

－

1.5

0.1

3.0

5

ｍA

μA

SCL/SDA_PC0/1=VCC

SCL/SDA_MON=H-Z

DDCENA=WPB=BANKSEL=GND

DUALPCB=VCC

Note: This IC is not designed to be radiation-resistant

*1 IOL at monitor mode (DDCENA＝HIGH) is the sum of current flowing from the pull up resistor at the SDA_MON side to the pull up resistance at SDA_PC0/PC1

7/16

●Block diagram

1Kbit

Fig.15 Block Diagram

●Pin layout diagram

VCC

WP

DUALPCB BANKSEL DDCENA SCL_MON SDA_MON

BU9882-W

BU9882F-W

BU9882FV-W

SCL_PC0 SDA_PC0

N.C.

SCL_PC1 SDA_PC1

N.C.

GND

Fig.16 Pin Layout

●Pin description

Pin Name

VCC

I/O

Functions

－

Power Supply

Ground （0V）

No Connection

GND

N.C.

Serial Clock Input, Access to BANK0 at DUAL PORT mode

Access to BANK0 or to BANK1 at SINGLE PORT mode

Slave and Word Address Serial Data Input, Serial Data Output

Access to BANK0 at DUAL PORT mode, Access to BANK0 or to BANK1 at SINGLE PORT mode

Serial Clock Input

Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode

Slave and Word Address Serial Data Input, Serial Data Output

Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode

Serial Clock Output

Connected to SCL_PC0/1 at DDCENA="High", "Hi-Z" output at DDCENA="Low"

Slave and Word Address Serial Data Output

Connected to SCL_PC0/1 DDCENA="High", "Hi-Z" output at DDCENA="Low"

Control of SCL_MON, SDA_MON

SCL_PC0

SDA_PC0

SCL_PC1

SDA_PC1

SCL_MON

IN

IN/OUT

IN

IN/OUT

OUT

SDA_MON

DDCENA

BANKSEL

OUT

IN

Select a SCL/SDA_MON Connected Port at DUAL PORT mode

Selected a BANK at SINGLE PORT mode

IN

DUALPCB

_

IN

Control of DUAL PORT/SINGLE PORT mode

Write Protect Control

WP

An open drain output requires a pull-up resistor.

8/16

●Electrical characteristics – AC (Unless otherwise specified, Ta=-40℃～+85℃､VCC=2.5V～5.5V)

Fast-mode

Standard-mode

Unit

Typ.

Parameter

Clock Frequency

Symbol

VCC=2.5V～5.5V

Min.

Typ. Max.

Min.

Typ. Max.

fSCL

tHIGH

tLOW

tR

－

0.6

1.3

－

400

－

4.0

4.7

－

100

－

kHz

μs

ns

Data Clock High Period

Data Clock Low Period

SDA and SCL Rise Time

SDA and SCL Fall Time

Start Condition Hold Time

Start Condition Setup Time

Input Data Hold Time

－

0.3

－

1.0

0.3

－

tF

－

tHD:STA

tSU:STA

tHD:DAT

tSU:DAT

tPD

0.6

0

4.0

4.7

0

－

Input Data Setup Time

Output Data Delay Time(SCL)

Stop Condition Setup Time

Bus Free Time

100

－

250

－

ns

0.9

－

3.5

－

μs

ms

μs

tSU:STO

tBUF

0.6

1.3

－

4.0

4.7

－

Write Cycle Time

tWR

10

0.1

10

0.1

Noise Spike Width (SDA and SCL)

tI

－

●Synchronous data timing

●Write cycle timing

t_R

t_F

t_HIGH

SCL

t_HD:STA

t_SU:DAT

t_LOW

t_HD:DAT

SDA

D0

ACK

SDA

(IN)

tWR

WRITE DATA (n)

t_BUF

t_PD

STOP CONDITION

START CONDITION

SDA

(OUT)

Fig.18 Write Cycle Timing

SCL

SDA

t_SU:STA

t_HD:STA

t_SU:STO

START BIT

STOP BIT

Fig.17 Synchronous Data Timing

・SDA data is latched into the chip at the rising edge of the SCL clock.

・The output date toggles at the falling edge of the SCL clock.

●Operation notes

○DDCENA Operation

When DDCENA is set to High, SCL_PC0/1 and SDA_PC0/1 will be connected to SCL_MON and SDA_MON,

respectively. Therefore, monitoring of the communications between the PC and EEPROM, and the communications of

the MONITOR and PC, is possible.

Selection of PC0/PC1 is determined according to the state of the DUALPCB and BANKSEL inputs.

When DDCENA is Low, the SCL/SDA_MON output is set to "Hi-Z".

SCL_MON,SDA_MON

DUALPCB

BANKSEL

(CONNECTION PORT)

PC0 PORT

Low

High

Low

High

Low (DUAL PORT)

High (SINGLE PORT)

PC1 PORT

PC0 PORT

9/16

○BANKSEL

BANKSEL serves as an input for connection port of SCL/SDA_MON during DUAL PORT mode.

It turns into the BANK selection terminal of internal memory in SINGLE PORT mode.

Only the PC0 port can access the memory in SINGLE PORT mode.

DUALPCB

BANKSEL

Low

CONNECTION BANK

PC0 PORT：BANK0

PC1 PORT：BANK1

BANK0

Low (DUAL PORT)

High

Low

High (SINGL PORT)

High

BANK1

○WP

When WP=Low, all data at all addresses are write-protected. The terminal has a built-in pull down resister. Make sure

that WP=High when writing data.

Utilize this function in order to prevent incorrect write command input from the PC, as well as incorrect input during

communication between the PC and monitor.

○Data Read

The data read function allows simultaneous read from SCL_PC0/1, SDA_PC0/1 in DUAL PORT mode.

○Data Write

Write operation is performed

S

T

A

R

T

W

R

I

using either PC0/1 (SCL or

SDA) even when accessed

simultaneously in DUAL PORT

mode. Port selection is made

by detecting the data D0 of

the first byte of the WRITE

command input.

S

T

O

P

SLAVE

WORD

ADDRESS

T

E

DATA

ADDRESS

SDA_PC

WA

0

WA

6

1

0

1

0

*

D7

D0

R

/

W

A

C

K

A

C

K

A

C

K

*:Don’t care

After this, the other port is

made unavailable for both

READ and WRITE commands

until the write operation is

completed.

During other port is write command.

this ack is no output.

D0 detected first write operation

performed through the port

Fig.19 Write Cycle Timing

○START Condition

All commands are preceeded by the START condition, which is a High to Low transition of SDA when SCL is High. This

IC continuously monitors the SDA and SCL lines for the START condition and will not respond to any commands until

this condition has been met.

○STOP Condition

All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is HIGH.

(See Fig.17)

○WRITE Command

Unless a STOP condition is executed, the data will not be written into the memory array.

○DEVICE ADDRESSING

Following a START condition, the Master outputs the device address of the slave to be accessed.

The most significant four bits of the Slave address are the "device type indentifier".

For the IC this is fixed as "1010".

The next three bits are "000".

The last bit of the stream determines the operation to be performed.

When set to "1", Read operation is selected ; when set to "0", Write operation is selected.

R/W set to "0" ・・・・・・・・ WRITE

R/W set to "1" ・・・・・・・・ READ

__

1010

0

R/W

10/16

●Commands

○Byte Write

S

T

A

R

T

W

R

I

T

E

S

T

O

P

When the Master generates a STOP condition, the IC

begins an internal write cycle to the nonvolatile array.

SLAVE

ADDRESS

WORD

ADDRESS

DATA

SDA

LINE

WA

0

WA

6

1

0

1

0

*

D7

D0

R

/

W

A

C

K

A

C

K

A

C

K

*:Don’t care

Fig.20 Byte Write Cycle Timing

○Page Write

After the receipt of each word, the three low order

address bits are internally increased by one. The

S

T

W

R

I

T

E

S

T

O

P

A

SLAVE

WORD

R

four higher order bits of the address(WA6～WA3)

remain constant. This IC is capable of eight byte

page write operation.

DATA(n)

DATA(n+7)

ADDRESS

T

ADDRESS

SDA

LINE

WA

0

1

0

1

0

D7

D0

*

6

If the master transnmits more than eight words,

prior to generating the STOP condition, the address

counter will "roll over", and the previous transmitted

data will be overwritten.

R

/

W

A

C

K

A

C

K

A

C

K

A

C

K

*:Don’t care

Fig.21 Page Write Cycle Timing

○Current Read

S

T

A

In case the previous operation is random or current read (which includes

sequential read), the internal address counter is increased by one from the

last acceseed address (n). Thus current read outputs the data of the next

word address (n+1).

R

E

A

D

S

T

O

P

SLAVE

R

DATA

ADRESS

T

SDA

LINE

1

0

1

0

D7

D0

If the last command is byte or page write, the internal address stays at the

last address(n). Thus current read outputs the data of the word address (n).

If the master does not transfer the Acknowledge, but does generate a stop

condition, the current address read operation only provides a single byte of

data.

R

A

C

K

A

C

K

/

W

Fig.22 Current Read Cycle Timing

At this point, the BU9882/F/FV-W discontinues transmission.

○Random Read

Random read operation allows the master to

S

T

A

R

T

W

R

I

S

T

A

R

T

R

E

A

D

S

T

O

P

access any location.

SLAVE

WORD

SLAVE

ADDRESS

T

E

DATA(n)

ADDRESS

If the master does not transfer the Acknowledge

but does generate a stop condition, the current

address read operation only provides a single byte

of data. (At 1Kbit all address read possible).

This communication must be terminated by a stop

condition, which is a Low to High transition of SDA

when SCL is High.

SDA

LINE

WA

0

WA

6

1

0

1

0

*

1

0

1

0

D7

D0

A

C

K

R

/

W K

A

C

A

C

K

R

/

W K

A

C

*:Don’t care

Fig.23 Random Read Cycle Timing

○Sequential Read

During the Current read operation, if an

Acknowledge is detected, and no STOP condition

is generated by the master(μ-COM), the device

will continue to transmit the data. (It can transmit

all data(1Kbit 128word)). If an Acknowledge is not

detected, the devive will terminate further data

transmissions and await a STOP condition before

returning to the standby mode. The Sequential

Read operation can be performed with both

Current Read and Random Read.

S

R

E

A

D

S

T

A

R

T

O

P

SLAVE

DATA(n)

DATA(n+x)

ADDRESS

SDA

LINE

1

0

1

0

D7

D0

D7

D0

R

/

W K

A

C

A

C

K

A

C

K

A

C

K

Fig.24 Sequential Read Cycle Timing

11/16

●Peripheral Circuits

○DUAL PORT

DUAL PORTs are used to connect two PCs to one monitor. PC0 is connected to BANK0 and PC1 to BANK1. Each bank

operates as 1Kbit EEPROM.

○ To Use DUAL PORT

PC 0

MONITOR

Start the operation of the DUAL PORT by

following the instructions below:

CC

Ｖ

SCL

1. Set the DUAL PCB to LOW with neither of

the ports being operated by commands.

2. Input the command from PC0 or PC1.

○ Simultaneous Access

SDA

VCC

SCL_PC0

BANK0

(1kbit)

SDA_PC0

WP

WPB

DUALPCB

BANKSEL

DDCENA

NC

SCL_PC1

CPU

BANK1

(1kbit)

SDA_PC1

NC

EEPROM data read allows simultaneous access

from PC0, PC1 ports.

SCL_MON

SDA_MON

PC 1

GND

SCL

SDA

Write operation is performed for either of PC0/1

even when accessed simultaneously from both.

Port selection is made by detecting the data D0

of the first byte of the WRITE command input.

Write operation is performed only for the port

where D0 of the first byte of the write data is

detected first.

Fig.25 Example of Peripheral Circuit with Dual Port

Write operation performed

Through the port.

S

T

A

R

T

S

T

A

R

T

S

T

O

P

S

T

O

P

R

/

W

R

/

W

A

C

K

A

C

K

SLAVE

ADDRESS

BANK0 WORD

ADDRESS(W)

SLAVE

ADDRESS

Output Data from BANK0

SDA-PC0

BUS

SDA-PC0

BUS

*WA6

*WA₆

WA0

WA₀

1

D₇

D₀

1

D₇

D₀

S

T

O

Output Data from BANK1

BANK1 WORD

ADDRESS(W)

SDA-PC1

BUS

P

SDA-PC1

BUS

1

D₇

D₀

SDA-PC1

BUS

*WA6

WA0

1

D₇

D₀

Fig.26¹SIMULTANEOU^DS⁷ACCESS

OF READ OPERATION

No ACK

*:Don’t care

Fig.27 Simultaneous Access

Of Write Operation

Fig.26 Simultaneous Access

of Read Operation

of White Operation

○MONITOR OUTPUT

BU9882/F/FV-W has a monitor output terminal. This allows communication between the PC and monitor CPU.

The monitor output for the use of DUAL PORT can be switched with BANKSEL input, as shown in the table below.

BANKSEL input

SCL_MON,SDA_MON connection port

PC0 PORT

Low

High

PC1 PORT

PC 0

MONITOR

○ SINGLE PORT

SINGLE PORT is for connecting one

PC to one monitor. In this case, it is

accessible only from PC0. BANK

selection is made with BANKSEL.

Switching this BANKSEL allows

access to the total of 2kbit EEPROM,

with BANK0 and BANK1, from PC0.

○ To use SINGLE PORT

ＶCC

SCL

SDA

VCC

SCL_PC0

SDA_PC0

NC

BANK0

(1kbit)

WP

DUALPCB

BANKSEL

DDCENA

SCL_PC1

SDA_PC1

CPU

BANK1

(1kbit)

Start the SINGLE PORT operation

by following the instructions below:

1. Set the DUAL PCB to High with

neither of the ports being operated

by commands.

SCL_MON

SDA_MON

NC

GND

2. Select the BANK with BANKSEL.

3. Input the command from PC0.

Fig.28 Example of Peripheral Circuit with Single Port

12/16

Common Application Note

Dummy Clock×14

Start×2

●Software Reset

Execute software reset in case the device is at

an unexpected state after power up and/or the

command input needs to be reset. The following

figures (Fig.29-(a), Fig.29-(b), Fig.29-(c))

During dummy clock, please release SDA BUS

(tied to Vcc by pull up resistor).

2

13

14

1

SCL

SDA

COMMAND

Fig.29-(a) Dummy Clock×14＋Start＋Start

During that time, the device may pull the SDA

line Low for acknowledge or outputting read

data. If the master controls the SDA line High, it

will conflict with the device output Low then it

Start

Dummy Clock×9

1

2

8

9

SCL

SDA

COMMAND

makes

a current overload. It may cause

Fig.29-(b) Start＋Dummy Clock×9＋Start

instantaneous power down and may damage

the device.

Start×9

3

7

SCL

SDA

2

8

9

1

COMMAND

Fig.29-(c) Start×9

●Acknowledge Polling

During the internal write cycle,

no ACK will be returned.

(ACK=High)

Since the device ignores all input commands

during the internal write cycle, no ACK will be

returned. When the master sends the next

command following the write command, and the

device returns the ACK, it means that the

program is completed. If no ACK is returned, it

means that the device is still busy. By using

Acknowledge polling, the waiting time is

minimized to less than tWR=5ms. To prevent

operating Write or Current Read immediately

after Write, first send the slave address (R/W is

"High" or "Low"). After the device returns the

ACK, continue word address input or data

output, respectively.

THE FIRST WRITE COMMAND

S

T

S

T

A

R

T

S

A

SLAVE

T

A

R

T

C

K

H

C

K

H

A

WRITE COMMAND

O

…

R

P

T

ADDRESS

tWR

THE SECOND WRITE COMMAND

S

T

A

R

T

S

T

A

C

K

L

A

C

K

L

A

C

K

L

WORD

T

A

R

T

SLAVE

ADDRESS

C

K

H

DATA

O

P

…

ADDRESS

tWR

After the internal write cycle

is completed ACK will be returned

(ACK=Low). Then input next

Word Address and data.

Fig.30 Successive Write Operation By Acknowledge Polling

●Command Cancellation By Start And Stop Condition

During a command input, command is canceled

by the successive inputs of start condition and

SCL

stop condition (Fig.31). However, during ACK or

data output, the device may output the SDA line

Low. In such cases, operation of start and stop

condition is impossible, making the reset

inoperable. Execute the software reset in the

cases. (Fig.29)

SDA

1

0

Start

Stop

Condition

Operating the command cancel by start and

stop condition during the command of Random

Read or Sequential Read or Current Read,

internal address counter is not confirmed.

Therefore operation of Current Read after this is

not valid. Operate a Random Read in this case.

Condition

Fig.31 Command Cancellation

13/16

●I/O Circuit

○SDA Pin Pull-up Resister

The pull up resister is needed because SDA is NMOS open drain. Choose the correct value of this resister(RPU), by

considering VIL, IL characteristics of a controller which control the device and VOH, IOL characteristics of the device. If

large RPU is chosen, clock frequency needs to be slow. In case of small RPU, the operating current increases.

○Maximum Rpu

Maximum value of RPU is determined by following factors:

①SDA rise time determined by RPU and the capacitance of bus line(CBUS) must be less than tR.

Other timing must keep the conditions of AC spec.

②When SDA bus is High, the voltage A of SDA bus determined by a total input leak(IL) of the all devices connected to

the bus. RPU must be significantly higher than the High level input of a controller and the device, including a noise

margin 0.2VCC.

MICRO

COMPUTER

VCC-ILRPU-0.2 VCC ≧ VIH

CC IH

0.8V -V

RPU

PU

R

∴

≦

IL

A

SDA PIN

Examples: When VCC=3V IL=10μA VIH=0.7VCC

According to ②

IL

0.8×3-0.7×3

10×10^-6

PU

R

≦

THE CAPACITANCE OF

BUS LINE (CBUS)

［kΩ］

300

≦

○Minimum RPU

The minimum value of RPU is determined by following factors:

①Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.

Fig.32 I/O Circuits

CC OL

V

-V

OL

≦ I

PU

R

CC OL

V

-V

PU

R

∴

≧

OL

I

② VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROM

including the recommended noise margin of 0.1VCC.

VOLMAX ≦ VIL-0.1 VCC

Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC,

3-0.4

3×10 ^-3

PU

R

According to ①

≧

［

］

Ω

≧ 867

and

VOL=0.4［V］

VIL=0.3×3

=0.9［V］

so that condition② is met

○SCL Pin Pull-up Resister

When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required.

However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended.

Several kΩ are recommended for the pull-up resistor in order to drive the output port of the microcontroller.

14/16

●Notes For Power Supply

VCC rises through the low voltage region in which the internal circuit of the IC and the controller are unstable. Therefore, the

device may not work properly due to an incomplete reset of the internal circuit. To prevent this, the device has a P.O.R. and

LVCC feature. At power up, maintain the following conditions to ensure functions of P.O.R and LVCC.

1. "SDA='H'" and "SCL='L' or 'H'".

2. Follow the recommended conditions of tR, tOFF, Vbot for the P.O.R. function during power up.

tR

Recommended conditions of tR, tOFF, Vbot

V_CC

tR

tOFF

Vbot

Below 10ms Above 10ms Below 0.3V

Below 100ms Above 10ms Below 0.2V

tOFF

Vbot

0

Fig.33 Vcc rising wave from

3. Prevent SDA and SCL from being "Hi-Z".

In case conditions 1 and/or 2 cannot be met, take following actions:

A）If unable to keep condition 1 ( SDA is "Low" during power up):

→Control SDA ,SCL to be "High" as shown in figure below.

VCC

tLOW

SCL

SDA

After Vcc becoms stable

tDH tSU:DAT

tSU:DAT

Fig.34 SCL="H" and SDA="L"

B）If unable to keep condition 2.

Fig.35 SCL="L" and SDA="L"

→After power becomes stable, execute software reset. (See Fig.29)

C）If unable to keep both conditions 1 and 2.

→Follow the instruction A first, then the instruction B.

●LVCC Circuit

LVCC circuit inhibits write operation at low voltage, and prevents an inadvertent write. Write operation is inhibited below the

LVCC voltage (Typ.=1.2V).

●Vcc NOISE

○Bypass Condenser

Noise and surges on power line may cause abnormal function. It is recommended that the bypass condensers (0.1μF) are

attached on the Vcc and GND line beside the device. It is also recommended to attach bypass condensers on the board close

to the connector.

●Caution On Use

1) Described numeric values and data are design representative values, and the values are not guaranteed.

2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further

sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in

consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.

3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI

may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear

exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions

exceeding the absolute maximum ratings should not be impressed to LSI.

4) GND electric potential

Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltages is lower than that of

GND terminal.

5) Heat design

In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.

6) Terminal to terminal shortcircuit and wrong packaging

When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct

LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign

matter, LSI may be destructed.

7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently.

15/16

●Selection of order type

BR

24

C

21

/F/FJ/FV

E2

Package type

Blank:DIP-T8

F:SOP8

FJ:SOP-J8

FV:SSOP-B8

Product

Package specifications

ROHM type

name

BUS type

24:I²C

Capacity

21=1k

type

Blank:Tube(only for DIP)

E2:Embossed carrier tape

C:2.5V Version

BU

9882

/F/FV

W

E2

Package specifications

ROHM type

name

Package type

Blank:DIP14

F:SOP14

FV:SSOP-B14

Double cell

Product

No

Blank:Tube(only for DIP)

E2:Embossed carrier tape

SOP8

DIP-T8

Tape

Embossed carrier tape

2500pcs

9.3 0.3

Container

Quantity

Tube

Quantity

8

5

2000pcs

5.0 0.2

Direction

of feed

E2

Direction

of feed

Direction of products is fixed in a container tube.

8

5

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

1

4

7.62

1

4

0.15 0.1

0.1

1.27

0.4 0.1

2.54

0.5 0.1

0° ∼ 15°

Direction of feed

1Pin

Reel

(Unit:mm)

※When you order , please order in times the amount of package quantity.

SOP-J8

<<DDimimenesnisoino>n>

SSOP-B8

Tape

Embossed carrier tape

2500pcs

Tape

Embossed carrier tape

2500pcs

4.9 0.2

Quantity

3.0 0.2

8

7

6

5

8

5

3.0 0.2

Direction

of feed

E2

Direction

of feed

8

5

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

1

4

1

4

0.15 0.1

1

2

3

4

0.2 0.1

0.1

0.22 0.1

(0.52) 0.65

0.22 0.1

(0.52) 0.65

1.27

0.42 0.1

Direction of feed

1pin

1Pin

※When you order , please order in times the amount of package quantity.

DirectioDnireocftifoeneodf feed

Reel

(Unit:mm)

（Unit:mm)

※When you order , please order in times the amount of package quantity.

SOP14

DIP14

Tape

Embossed carrier tape

Container

Quantity

Tube

19.4 0.3

Quantity

2500pcs

8.7 0.2

14

1

8

7

1000pcs

8

E2

14

1

Direction

of feed

Direction

of feed

Direction of products is fixed in a container tube.

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

7.62

7

0.15 0.1

0.1

1.27

0.4 0.1

0°

∼ 15°

2.54

0.5 0.1

1Pin

Direction of feed

Reel

(Unit:mm)

※When you order , please order in times the amount of package quantity.

SSOP-B14

Embossed carrier tape

Tape

Quantity

2500pcs

5.0 0.2

14

8

.

E2

Direction

of feed

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

1

7

0.15 0.1

0.1

0.22 0.1

0.65

1pin

Direction of feed

Reel

（Unit:mm)

※When you order , please order in times the amount of package quantity.

Catalog No.05T326Be '05.11 ROHM C 1000 TSU

16/16

Appendix

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact your nearest sales office.

THE AMERICAS / EUROPE / ASIA / JAPAN

ROHM Customer Support System

Contact us : webmaster@ rohm.co.jp

www.rohm.com

TEL : +81-75-311-2121

FAX : +81-75-315-0172

21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan

Appendix1-Rev2.0


型号：	BU9882-E2
厂家：	ROHM
描述：	EEPROM, PDIP14, DIP-14 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
文件：	总17页 (文件大小：812K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU9882-E2 [ROHM]

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