BU97601FV-M_技术文档

Datasheet

Low Duty LCD Segment Driver

for Automotive application

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

General Description

Key Specifications

The BU97601FV-M is a 1/4, 1/3, 1/2 duty or Static

general-purpose LCD driver that can be used for

automotive applications and can drive up to 116 LCD

Segments.

This product can support VA LCD displays, which has

better optical performance with higher LCD voltage

driving and higher frame frequency driving.

◼ Supply Voltage Range:

+2.7 V to +6.0 V

-40 °C to +85 °C

116 Segments

◼ Operating Temperature Range:

◼ Max Segments:

◼ Display Duty

◼ Bias:

Static, 1/2, 1/3, 1/4 Selectable

1/2, 1/3 Selectable

◼ Interface:

3wire Serial Interface

It can control up to 16 general-purpose outputs / 16

PWM output ports for LED backlighting and LED button

illumination realizing less flicker by various frequency

setting function.

Special Characteristics

◼ Electrostatic Discharge Voltage(HBM):

◼ Latch-up Current:

±2000 V

±100 mA

It can also support a key scan function that detects a

maximum of 20 key inputs to reduce PCB wiring and to

minimize microcontroller size and cost.

It can support LCD contrast adjustment by its EVR

function and TTL compatible input interface is also

available, these are well-suited for wide-voltage range of

MCUs.

Applications

◼ Instrument Clusters

◼ Climate Controls

◼ Car Audios

◼ Car Radios

◼ Metering

Features

◼ White Goods

◼ Healthcare Products

◼ Battery Operated Products

etc.

◼ AEC-Q100 Qualified ^(Note)

◼ 1/4, 1/3, 1/2 duty or Static Setting Selectable

1/4 duty: Max 116 Segments,

1/3 duty: Max 87 Segments

1/2 duty: Max 58 Segments,

Static: Max 29 Segments

Package

◼ 1/3 or 1/2 Bias Setting Selectable

◼ Support wide range of operation voltage from 2.7 V to

6.0 V, which can support TN LCD and VA LCD

display.

W (Typ) x D (Typ) x H (Max)

◼ Integrated LCD Voltage Driving Circuit

◼ Integrated Oscillation Circuit for LCD Frame

Frequency

◼ Line or Frame Inversion Driving Selectable

◼ Max 16ch External PWM Outputs

(SEG outputs/general purpose outputs selectable)

◼ Max 6ch Internal PWM Outputs

(SEG outputs/general purpose outputs/external PWM

outputs selectable)

SSOP-B40

13.6 mm x 7.8 mm x 2.0 mm

◼ Support 256 Step PWM Function to Realize Backlight

Button LED Illumination

◼ Support LCD Frame Frequency from 50 Hz to 685 Hz,

Total 128-setting

◼ Support PWM Frequency from 146 Hz to 2.34 kHz,

Total 16-setting

◼ Support 3 Wire Serial Interface + KEYOUT

◼ Support TTL Level Input to Connect 3.3 V MCU

Directly

◼ Support Max 20 Keys Input Detection

(SEG selectable)

◼ Integrated EVR Function to Adjust LCD Contrast

◼ Integrated Voltage Detected Type Power on Reset

Circuit

◼ No External Components Required

◼ Low Power Consumption Design

(Note) Grade 3

〇Product structure : Silicon monolithic integrated circuit 〇This product is not designed protection against radioactive rays.

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Typical Application Circuit

Key matrix

(P1/G1)

(P6/G6)

(Generalpurpose/PWM ports)

(For use controlof backlight)

(P16/G16)

KS1/S23

|

KS5/S27

KI1/S32

|

KI4/S35

COM1

COM2

COM3

COM4

S5/P1/G1

S6/P2/G2

VDD

+5 V

(Note)

S10/P6/G6

S11/P7/G7

LCD Panel

(Up to 116

Segments)

INHb

SCE

SCL

From

Controller

SDI

S20/P16/G16

SDO

To Controller

S21

S22

PWMIN/S36

OSCIN/S37

From

Controller

(Note) Insert capacitors between VDD and VSS C > 0.1 µF.

Figure 1. Typical Application Circuit

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Block Diagram

Figure 2. Block Diagram

Pin Arrangement

Figure 3. Pin Configuration (TOP VIEW)

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Absolute Maximum Ratings(VSS = 0.0 V)

Parameter

Symbol

Conditions

Ratings

-0.3 to +7.0

Unit

V

Maximum Supply Voltage

VDD

SCE, SCL, SDI, INHb, PWMIN^{(Note 1)}

OSCIN^{(Note 2)}

,

V_IN1

-0.3 to +7.0

V

Input Voltage

V_IN2

Pd

KI1 to KI4^{(Note 3)}

-0.3 to +7.0

0.70^{(Note 4)}

-40 to +85

-55 to +125

V

Allowable Loss

W

°C

Operating Temperature

Storage Temperature

Topr

Tstg

(Note 1) In case of External PWM setting.

(Note 2) In case of External clock mode setting.

(Note 3) In case of Key scan setting

(Note 4) Delete by 7.00 mW/°C when operating above Ta = 25 °C (when mounted in ROHM’s standard board).

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the

absolute maximum ratings.

Recommended Operating Conditions (Ta = -40 °C to +85 °C, VSS = 0.0 V)

Ratings

Typ

5.0

Parameter

Symbol

VDD

Conditions

Unit

V

Min

2.7

Max

6.0

Supply Voltage

Electrical Characteristics (Ta = -40 to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)

Limit

Typ

Parameter

Hysteresis

Symbol

V_H1

Conditions

Unit

V

Min

-

Max

-

SCE, SCL, SDI, INHb,

0.03VD

D

PWMIN^(Note1)

OSCIN^{(Note 2)}

,

V_H2

V_DET

V_IH1

KI1 to KI4^{(Note 3)}

VDD

-

0.1VDD

1.8

-

V

Power-on

1.3

2.2

Detection Voltage

“H” Level Input

Voltage

SCE, SCL, SDI, INHb,

4.5 V ≤ VDD ≤ 6.0 V

2.7 V ≤ VDD < 4.5 V

PWMIN^(Note1)

,

0.4VDD

-

VDD

V

OSCIN^{(Note 2)}

V_IH2

SCE, SCL, SDI, INHb,

PWMIN^{(Note 1)}

OSCIN^{(Note 2)}

,

0.8VDD

0.7VDD

-

VDD

V

V_IH3

V_IL1

KI1 to KI4^{(Note 3)}

“L” Level Input

Voltage

SCE,SCL,SDI,INHb,

PWMIN^{(Note 1)}

,

0

-

0.2VDD

V

OSCIN^{(Note 2)}

,

KI1 to KI4^{(Note 3)}

Input Floating

Voltage

Pull-down

Resistance

Output Off

Leakage

Current

“H” Level Input

Current

V_IF

R_PD

-

0.05VDD

250

V

KI1 to KI4^{(Note 3)}

SDO

VDD = 5.0 V

V_O= 6.0 V

V_I= 5.5 V

V_I= 0 V

50

100

kΩ

I_OFFH

-

6.0

5.0

-

µA

I_IH1

SCE, SCL, SDI, INHb,

PWMIN^{(Note 1)}

,

OSCIN^{(Note 2)}

“L” Level Input

Current

I_IL1

SCE, SCL, SDI, INHb,

PWMIN^{(Note 1)}

OSCIN^{(Note 2)}

S1 to S37

,

-5.0

“H” Level

Output Voltage

V_OH1

V_OH2

I_O= -20 µA, VLCD = 1.00*VDD VDD-0.9

I_O= -100 µA,

VLCD = 1.00*VDD

-

COM1 to COM4

VDD-0.9

V

V_OH3

P1/G1 to P16/G16^{(Note 5)}I_O= -1 mA

VDD-0.

9

-

V_OH4

V_OL1

V_OL2

V_OL3

V_OL4

V_OL5

KS1 to KS5^{(Note 3)}

S1 to S37

I_O= -500 µA

I_O= 20 µA

VDD-1.0 VDD-0.5 VDD-0.2

“L” Level

-

0.9

1.5

0.5

Output Voltage

COM1 to COM4

I_O= 100 µA

P1/G1 to P16/G16^{(Note 5)}I_O= 1 mA

KS1 to KS5^{(Note 3)}

SDO

I_O= 25 µA

I_O= 1 mA

0.2

-

0.5

0.1

(Note 5) General –purpose / PWM outputs setting.

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Electrical Characteristics – continued

Limit

Typ

Parameter

Symbol

Conditions

Unit

Max

Min

Middle Level

Output Voltage

V_MID1COM1 to COM4

1/2 bias

I_O= ±100 µA

VLCD = 1.00*VDD

1/3 bias

I_O= ±20 µA

VLCD = 1.00*VDD

1/3 bias

I_O= ±20 µA

VLCD = 1.00*VDD

1/3 bias

I_O= ±100 µA

VLCD = 1.00*VDD

1/3 bias

I_O= ±100 µA

VLCD = 1.00*VDD

Power-saving mode

VDD = 5.0 V

Output open,

1/2 bias

1/2VDD

-0.9

1/2VDD

+0.9

-

V_MID2S1 to S37

2/3VDD

-0.9

2/3VDD

+0.9

V_MID3S1 to S37

1/3VDD

-0.9

1/3VDD

V

+0.9

V_MID4COM1 to COM4

V_MID5COM1 to COM4

2/3VDD

-0.9

2/3VDD

+0.9

1/3VDD

-0.9

1/3VDD

+0.9

-

Current

Consumption

I_DD1

I_DD2

VDD

-

15

µA

-

100

120

210

Frame frequency = 80 Hz

VLCD = 1.00*VDD

VDD = 5.0 V

Output open,

1/3 bias

I_DD3

VDD

-

250

µA

Frame frequency = 80 Hz

VLCD = 1.00*VDD

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Oscillation Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)

Limit

Typ

-

Parameter

Symbol

Conditions

Unit

Max

Min

360

540

Oscillator Frequency 1

Oscillator Frequency 2

External Clock

f_OSC1

f_OSC2

f_OSC3

-

VDD = 2.7 V to 6.0 V

VDD = 5 V

720

660

kHz

600

30

-

1000

kHz

Frequency^{(Note 1)}

External clock mode

(OC = 1)

External Clock Rise Time

External Clock Fall Time

External Clock Duty

tr

tf

-

160

50

-

70

ns

%

OSCIN

tdty

30

(Note 1) Frame frequency is decided external frequency and dividing ratio of FC0, FC1, FC2, FC3, FC4, FC5, FC6 setting.

[Reference Data]

700

650

VDD = 6.0 V

600

VDD = 5.0 V

VDD = 3.3 V

550

VDD = 2.7 V

500

450

400

350

300

-40

-20

0

20

40

60

80

100

Temperature[°C]

Figure 4. Oscillator Frequency Typical Temperature Characteristics

External PWM Clock Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)

Limit

Typ

Parameter

Symbol

f_PWM

Conditions

Unit

Hz

ns

Min

30

Max

External PWM

Frequency

External PWM Input

Rise Time

External PWM Input

Fall Time

-

5000

tr_PWM

-

160

-

PWMIN

External PWM mode^{(Note 2)}

tf_PWM

ns

External PWM Pulse

Width

pw_PWM

780

ns

(Note 2) About External PWM mode setting, please refer to “Control Data Functions”.

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Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

MPU Interface Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)

Limit

Typ

Parameter

Symbol

Conditions

Unit

Max

Min

120

320

Data Setup Time

Data Hold Time

SCE Wait Time

SCE Setup Time

SCE Hold Time

Clock Cycle Time

High-level Clock Pulse

Width

Low-level Clock Pulse

Width (Write)

Low-level Clock Pulse

Width (Read)

t_DS

t_DH

t_CP

t_CS

t_CH

SCL, SDI

-

ns

SCL, SDI

SCE, SCL

SCL

t_CCYC

t_CHW

SCL

120

1.6

-

ns

µs

t_CLWW

t_CLWR

SCL

R_PU= 4.7 kΩ

C_L= 10 pF^(Note)

Rise Time

Fall Time

INH Switching Time

SDO Output Delay

Time

tr

tf

tc

SCE, SCL, SDI,

INHb, SCE

SDO

-

10

160

-

ns

µs

t_DC

R_PU= 4.7 kΩ

C_L= 10 pF^(Note)

R_PU= 4.7 kΩ

C_L= 10 pF^(Note)

-

1.5

µs

t_DR

SDO

SDO Rise Time

-

(Note) Since SDO is an open-drain output, ”t_DC” and “t_DR” depend on the resistance of the pull-up resistor R_PUand the load capacitance C_L.

R_PU: 1 kΩ ≤ R_PU≤ 10 kΩ is recommended.

C_L: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.

Power supply for I/O level

R_PU

Host

SDO

C_L

1. When SCL is stopped at the low level

V_IH1

SCE

V_IL1

t_CCYC

t_CHW

t_CLWW

t_CLWR

V_IH1

V_IL1

SCL

SDI

t_CH

t_cs

tr

tf

V_IH1

V_IL1

t_DS

t_DH

SDO

V_OL5

t_DC

t_DR

2. When SCL is stopped at the high level

V_IH1

SCE

V_IL1

t_CCYC

t_CHW

t_CLWW

t_CLWR

V_IH1

V_IL1

SCL

t_CP

t_CH

tr

tf

V_IH1

V_IL1

SDI

t_DS

t_DH

SDO

V_OL5

t_DC

t_DR

Figure 5. Serial Interface Timing

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BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Pin Description

Symbol

Handling

when

unused

Pin No.

1 to 2

Function

Active

-

I/O

O

S5/P1/G1 to

S10/P6/G6

Segment output for displaying the display data transferred by

serial data input. The S5/P1/G1 to S10/P6/G6 pins can also be

used as General –purpose / PWM outputs when set by the

control data.

OPEN

37 to 40

S11/P7/G7 to

S20/P16/G16

3 to 12

Segment output for displaying the display data transferred by

serial data input. The S11/P7/G7 to S20/P16/G16 pins can

also be used as General –purpose outputs / PWM outputs (by

External PWM only) when set by the control data.

-

O

OPEN

S21 to S22

13 to14

15 to 19

Segment output for displaying the display data transferred by

serial data input.

Key scan outputs.

Although normal key scan timing lines require diodes to be

inserted in the timing lines to prevent shorts, since these

outputs are unbalanced CMOS transistor outputs, these

outputs will not be damaged by shorting when these outputs

are used to form a key matrix. The KS1/S23 to KS5/S27 pins

can be used as segment outputs when specified by the control

data.

-

O

OPEN

KS1/S23 to

KS5/S27

KI1/S32 to

KI4/S35

20 to 23

Key scan inputs. These pins have built-in pull-down resistors.

The KI1/S32 to KI4/S35 pins can be used as segment outputs

when specified by the control data.

Common driver output pins.

The frame frequency is fo[Hz].

Segment output for displaying the display data transferred by

serial data input. The pin PWMIN/S36 can be used external

PWM input pin or segment output when set by the control

data.

Segment output for displaying the display data transferred by

serial data input. The pin OSCIN/S37 can be used as external

frequency input pin or segment output when set by the control

data.

-

I

VSS

O

OPEN

COM1 to

COM4

PWMIN/S36

24 to 27

30

-

I

VSS

OPEN

VSS

O

I

OSCIN/S37

31

-

O

OPEN

VSS

SCE

SCL

SDI

32

33

34

Serial data transfer inputs. Must be connected to the

controller.

SCE: Chip enable

H

↑

-

I

SCL: Synchronization clock

SDI: Transfer data

SDO

INHb^(Note)

35

36

Output data

Display off control input.

-

L

O

I

OPEN

VDD

When INHb = low (VSS), Display forced off

S5/P1/G1 to S10/P6/G6 = low (VSS)

S11/P7/G7 to S20/P16/G16 = low (VSS)

S21 to S22 = low (VSS)

KS1/S23 to KS5/S27 = low (VSS)

KI1/S32 to KI4/S35 = low (VSS)

PWMIN/S36 = low (VSS)

OSCIN/S37 = low (VSS)

COM1 to COM4 = low (VSS)

Stop the LCD drive bias voltage generation divider resistors.

Stop the internal oscillation circuit.

When INHb = high (VDD), Display on

However, serial data transfer is possible when the display is

forced off.

VDD

VSS

28

29

Power supply pin of the IC

A power voltage of 2.7 V to 6.0 V must be applied to this pin.

-

Power supply pin. Must be connected to ground.

(Note) Regarding the details of INHb terminal and the control of each output, refer to “INHb Pin and Display Control”.

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BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

I/O Equivalence Circuit

VDD

SCE/SDI/SCL/INHb

VSS

VDD

VSS

VDD

PWMIN/S36,

OSCIN/S37

S21 to S22,

COM1 to COM4

VSS

VDD

KI1/S32 to KI4/S35

S5/P1/G1 to S20/P16/G16,

KS1/S23 to KS5/S27

VSS

VDD

VSS

SDO

VSS

Figure 6. I/O Equivalence Circuit

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BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Serial Data Transfer Formats

1. 1/4 Duty

(1) When SCL is stopped at the low level

SCE

SCL

0

SDI

0

1

0

1

0

D1

D2

D39

D76

D113

0

KM0

FC1

FC2 FC3 FC4

FC6

0

KM1 KM2 P0

P1

P2

P3

P4

FC0

FC5

OC

SC BU0 BU1 BU2

0

1

0

1

D32 D33 D34 D35 D36 D37

FL

DR

DT0

DT1

B0

B1

B2

B3

A0

A1

A2

A3

DD

2 bits

Display Data

37bits

Control Data

33bits

Device Code

8bits

1

0

D38

0

1

0

1

D74

0

EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EP10 EP11 EP12 EP13 EP14

D69 D70 D71 D72 D73

EP15 EP16 PG1 PG2 PG3 PG4

PG5 PG6

PF1 PF2 PF3 CT0 CT1 CT2 CT3

PF0

B0

B1

B2

B3

A0

A1

A2

A3

DD

Control Data

33bits

Display Data

37bits

Device Code

8bits

2 bits

0

W10 W11 W12

W13 W14

W15 W16

1

0

D107 D108 D109

D110

W22 W23 W24

W26 W27 W28 W30 W31 W32

W35 W36 W38

W37

0

1

0

1

D75

D106

D111

W17 W18 W20

W21

W25

W34

W33

B0

B1

B2

B3

A0

A1

A2

A3

DD

Display Data

37bits

Control Data

33bits

Device Code

8bits

2 bits

1

0

D112

D144

D147

0

1

0

1

0

1

D143

D145 D146

D148

0

W40 W41 W42 W43 W44 W45 W46 W47 W48 W50

W52 W53 W54

W56 W57 W58 W60 W61 W62

W64 W65 W66

W68

W67

W51

W55

W63

B0

B1

B2

B3

A0

A1

A2

A3

(Note)

DD

2 bits

Control Data

33bits

Display Data

37bits

Device Code

8bits

Figure 7. 3-SPI Data Transfer Format

(Note) DD is direction data.

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MAX 116 Segments (29SEG x 4COM)

Serial Data Transfer Formats – continued

(2) When SCL is stopped at the high level

SCE

SCL

SDI

0

1

0

D1

0

KM0

FC2 FC3 FC4

FC6

0

1

0

1

D2

D39

D76

D113

0

KM1 KM2 P0

P1

P2

P3

P4

FC1

FC5

OC

SC BU0 BU1 BU2

0

1

0

1

D32 D33 D34 D35 D36 D37

FL

DR

DT0

DT1

FC0

B0

B1

B2

B3

A0

A1

A2

A3

DD

2 bits

Display Data

37bits

Control Data

33bits

Device Code

8bits

1

0

D38

0

1

0

1

D74

0

EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EP10 EP11 EP12 EP13 EP14

D69 D70 D71 D72 D73

EP15 EP16 PG1 PG2 PG3 PG4

0

PG5 PG6

PF1 PF2 PF3 CT0 CT1 CT2 CT3

PF0

B0

B1

B2

B3

A0

A1

A2

A3

DD

Control Data

33bits

Display Data

37bits

Device Code

8bits

2 bits

0

W10 W11 W12

1

0

D107 D108 D109

D110

W13 W14

W15 W16

W22 W23 W24

W26 W27 W28 W30 W31 W32

W35 W36 W38

W37

1

0

1

0

1

D75

D106

D111

W17 W18 W20

W21

W25

W34

W33

B0

B1

B2

B3

A0

A1

A2

A3

DD

Display Data

37bits

Control Data

33bits

Device Code

8bits

2 bits

1

0

D112

D144

D147

0

1

0

1

0

1

D143

D145 D146

D148

W40 W41 W42 W43 W44 W45 W46 W47 W48 W50

W52 W53 W54

W56 W57 W58 W60 W61 W62

W64 W65 W66

W68

W67

W51

W55

W63

B0

B1

B2

B3

A0

A1

A2

A3

(Note)

DD

2 bits

Control Data

33bits

Display Data

37bits

Device Code

8bits

Figure 8. 3-SPI Data Transfer Formatv

(Note) DD is direction data.

Device code･･････････････････“46H”

KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data

D1 to D148････････････････････Display data (D1-D16 and D109-D124 are not available)

P0 to P4･･････････････････････Segment / PWM / General Purpose output port switching control data

FL････････････････････････････Line Inversion or Frame Inversion switching control data

DR･･･････････････････････････1/3 bias drive or 1/2 bias drive switching control data

DT0 to DT1･･･････････････････1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data

FC0 to FC6･･･････････････････Common/Segment output waveform frame frequency switching control data

OC･･････････････････････････Internal oscillator operating mode/External clock operating mode switching control data

SC･･････････････････････････Segment on/off switching control data

BU0 to BU2･･････････････････Normal mode/power-saving mode switching control data

PG1 to PG6･･････････････････PWM/General Purpose Output (GPO) switching control data

EP1 to EP16･････････････････Internal PWM/External PWM switching control data (EP1 to EP6),

GPO/External PWM switching control data (EP7 to EP16)

PF0 to PF3･･･････････････････PWM output waveform frame frequency switching control data.

CT0 to CT3･･･････････････････LCD display contrast switching control data.

W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68

･････････････････････････････PWM output duty switching control data

When it is coincident with device code, BU97601FV-M capture display data and control data at falling edge of SCE.

So, please transfer the bit number of send display data and control data as specified number in the above figure.

Specified number of bits is 80bit (Device code: 8bit, Display data and Control data: 70bit, DD: 2bit).

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0P4P0D301630-1-2

05.Jan.2021 Rev.003

11/63

Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Serial Data Transfer Formats – continued

2. 1/3 Duty

(1) When SCL is stopped at the low level

SCE

SCL

SDI

0

1

0

D1

0

KM0

FC2 FC3 FC4

FC6

0

1

0

1

D2

D39

D76

0

KM1 KM2 P0

P1

P2

P3

P4

FC1

FC5

OC

SC BU0 BU1 BU2

0

1

0

1

D32 D33 D34 D35 D36 D37

FL

DR

DT0

DT1

FC0

B0

B1

B2

B3

A0

A1

A2

A3

DD

2 bits

Display Data

37bits

Control Data

33bits

Device Code

8bits

1

0

D38

0

1

0

1

D74

0

EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EP10 EP11 EP12 EP13 EP14

D69 D70 D71 D72 D73

EP15 EP16 PG1 PG2 PG3 PG4

PG5 PG6

PF1 PF2 PF3 CT0 CT1 CT2 CT3

PF0

B0

B1

B2

B3

A0

A1

A2

A3

DD

Control Data

33bits

Display Data

37bits

Device Code

8bits

2 bits

0

W10 W11 W12

1

0

D107 D108 D109

D110

W13 W14

W15 W16

W22 W23 W24

W26 W27 W28 W30 W31 W32

W35 W36 W38

W37

1

0

1

0

1

D75

D106

D111

W17 W18 W20

W21

W25

W34

W33

B0

B1

B2

B3

A0

A1

A2

A3

DD

Display Data

37bits

Control Data

33bits

Device Code

8bits

2 bits

1

0

1

0

1

0

1

0

W40 W41 W42 W43 W44 W45 W46 W47 W48 W50

W52 W53 W54

W56 W57 W58 W60 W61 W62

W64 W65 W66

W68

W67

W51

W55

W63

B0

B1

B2

B3

A0

A1

A2

A3

(Note)

DD

2 bits

Control Data

70bits

Device Code

8bits

Figure 9. 3-SPI Data Transfer Format

(Note) DD is direction data.

www.rohm.com

TSZ02201-0P4P0D301630-1-2

05.Jan.2021 Rev.003

12/63

TSZ22111 • 15 • 001

Datasheet

BU97601FV-M

MAX 116 Segments (29SEG x 4COM)

Serial Data Transfer Formats – continued

(2) When SCL is stopped at the high level

SCE

SCL

SDI

0

1

0

D1

0

KM0

FC2 FC3 FC4

FC6

0

1

0

1

D2

D39

D76

0

KM1 KM2 P0

P1

P2

P3

P4

FC1

FC5

OC

SC BU0 BU1 BU2

0

1

0

1

D32 D33 D34 D35 D36 D37

FL

DR

DT0

DT1

FC0

B0

B1

B2

B3

A0

A1

A2

A3

DD

2 bits

Display Data

37bits

Control Data

33bits

Device Code

8bits

1

0

D38

0

1

0

1

D74

0

EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EP10 EP11 EP12 EP13 EP14

D69 D70 D71 D72 D73

EP15 EP16 PG1 PG2 PG3 PG4

PG5 PG6

PF1 PF2 PF3 CT0 CT1 CT2 CT3

PF0

B0

B1

B2

B3

A0

A1

A2

A3

DD

Control Data

33bits

Display Data

37bits

Device Code

8bits

2 bits

0

W10 W11 W12

1

0

D107 D108 D109

D110

W13 W14

W15 W16

W22 W23 W24

W26 W27 W28 W30 W31 W32

W35 W36 W38

W37

1

0

1

0

1

D75

D106

D111

W17 W18 W20

W21

W25

W34

W33

B0

B1

B2

B3

A0

A1

A2

A3

DD

Display Data

37bits

Control Data

33bits

Device Code

8bits

2 bits

1

0

1

0

1

0

1

0

W40 W41 W42 W43 W44 W45 W46 W47 W48 W50

W52 W53 W54

W56 W57 W58 W60 W61 W62

W64 W65 W66

W68

W67

W51

W55

W63

B0

B1

B2

B3

A0

A1

A2

A3

(Note)

DD

2 bits

Control Data

70bits

Device Code

8bits

Figure 10. 3-SPI Data Transfer Format

(Note) DD is direction data.

Device code･･････････････････“46H”

KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data

D1 to D111････････････････････Display data (D1-D12 and D82-D93 are not available)