BU38703 [ROHM]
System control servo; 系统控制伺服
| 型号： | BU38703 |
| 厂家： | 
ROHM |
| 描述： | System control servo |
| 文件： | 总7页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Video ICs
System control servo
BU38603 / BU38703 / BU38803
The BU38603, BU38703 and BU38803 are servo controller ICs for VCRs. They contain a high-speed, 8-bit CPU and
perform the processing required for the drum, capstan, FV and PV completely in software, allowing a large reduction
in the number of external components required. They also contain high-performance linear amplifiers, eliminating the
need for interface ICs. Specialized hardware is included for items that require high-speed processing, to allow
efficient utilization of the CPU.
Applications
•
VHS VCRs and camcorders
Features
1) CPU
•
9) Head amplifier / chroma rotary
Generated from pattern generator output.
10) Built-in AGC. Five-bits used to switch the gain
control registers for the CTL amplifier.
11) CTL counter: 1 / 30 or 1 / 25
12) Data shift PLL calculation: 24 bit
13) Timer: 8 bit × 2
499 commands (69 types)
Memory-mapped I / O
Minimum command execution time: 250ns (8MHz)
2)ROM capacity
BU38603: 16384 × 8 bit
BU38703: 24576 × 8 bit
BU38803: 32768 × 8 bit
3) RAM capacity: 512 × 8bit
4) Interrupt
14) Synchronous serial input/output: 8 bit × 1
15) VH PULSE
V separeted from composite synchronous snal.
Pseudo V generated from pattern generator
output.
Pattern generator: 1
Watch-dog timer: 1
External interrupts: 1
Superimposed pseudo H synchronized with
the composite synchronous signal.
16) VISS / VASS
FG interrupts: 5
Internal interrupts: 7
Two timers, serial transmission, interrupt, VHSW,
CTL interval timer (fixed) / VISS
Multi-layer interrupts possible.
5) Free-running counter: 19 bit
6) PWM output: 12 bit × 2
7) Pattern generator
VASS 0 / 1 discrimination
VISS discrimination threshold: 3
Aspect discrimination.
D / A CTL switching.
17) Standard I / O
Parallel I / O (PIO): 32 bit
17 bits from FRC MSB used.
Output
Parallel output (PO): 6 bit
18) A / D converter: 8 bits × 8 channels
Can be masked-programmed to be parallel inputs.
19) Watch-dog timer
Internal: 3 bit
External (PO): 5 bit
External (PIO): 6 bit
Setting period: 4
8) Programmable pre-scaler
CFG: 7 bit
20) Linear circuits
DFG: amplifier / comparator
CFG: amplifier / comparator
CTL: differential amplifier / comparator
DPG: comparator
CTL: 6 bit
1
Video ICs
BU38603 / BU38703 / BU38803
Absolute maximum ratings (Ta = 25°C)
•
Parameter
Applied voltage
Symbol
Limits
Unit
2
VDD, VDDA, VDAD
0.3 ~ 7.0
V
V
VIN
Pd
VSS – 0.3 ~ VDD + 0.3
Pin applied voltage
1
mW
°C
Power dissipation
500
Tstg
– 55 ~ + 125
Storage temperature
1 Reduced by 5mW for each increase in Ta of 1°C over 25°C.
2 Use with VSS = VSSA = VSAD, and VDD = VDDA = VDAD.
Recommended operating conditions
•
Parameter
Power supply voltage
Clock frequency
Symbol
Limits
4.5 ~ 5.5
8
Unit
V
VDD, VDDA, VDDB
FCK
MHz
°C
Operating temperature
Topr
– 25 ~ + 75
Block diagram
•
CPU
Data bus
PWM0
PWM1
ROM / RAM
PWM
PO0-PO5
P1-P31
P0
PI / O
Timer
SI / O
VHSW
AHSW
PTG
HAMPSW
CHROT
ENVIN
Head amp,
chroma
SI
SO
SCK
FV
CSYNC
VH PULSE
Interrupts
Watchdog
(P0)
FRC
A / D converter
Data shift
ADC0-ADC7
Servo mode register
CFG,
CTL division
Linear time counter
COUNTP
PBCTL
VISSVASS
Gain control
Vref
RESETB
Linear
CTL + CTL – CTLAMPOUT CTLAMP – DFGIN DFGOUT DPGIN CFGINCFGOUT
2
Video ICs
BU38603 / BU38703 / BU38803
Pin descriptions
•
Pin No.
Pin name
VSAD
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
VDAD
DFGOUT
DFGIN
DPGIN
CFGIN
CFGOUT
VSSA
Vref
Function
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin name
CHROT
FV
Function
Chroma rotary switch output
Pseudo Vsync output
1
A / D convertor circuit GND.
2
3
VDD
Logic circuit power supply
4
PWM0
PWM1
P21
Can be optionally mask – programmed
to be either A / D or parallel inputs.
PWM output
5
6
7
P20
8
P19
9
P18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P17
A / D convertor circuit power supply.
Drum FG amplifier output
Drum FG amplifier input
Drum PG comparator input
Capstan FG amplifier input
Capstan FG amplifier output
Linear circuit GND
P16
Parallel I / O
P15
P14
P13
P12
P11
P10
Internal BIAS and power-on reset pin
CTL amplifier – input
CTLAMP –
CTLAMPOUT
CTL –
CTL +
VDDA
RESETB
TEST
PO5
P9
PO2
PO1
PO0
CLOCKO
CLOCKI
VSS
CTL amplifier output
CTL coil – connection
Parallel output
CTL coil + connection
Linear circuit power supply
Power supply reset
For connection of oscillator
Logic circuit GND
Test mode input (normally GND)
P8
Parallel output
Parallel I / O
PO4
P7
P31
P6
P30
P5
P29
P4
Parallel I / O
P28
P3
P27
P2
P26
P1
Parallel I / O and pattern generator
output
P25
P0
Parallel I / O and external interrupt
Serial I / O data input
P24
SI
P23
SO
Serial I / O data I / O
P22
SCK
ENVIN
CSYNC
COUNTP
PBCTL
Serial I / O clock I / O
PO3
Parallel output and pattern generator output
Pattern generator VHSW output
Pattern generator AHSW output
Head amplifier switch output
Envelope detector logic input
Composite signal logic input
CTL counter pulse output
CTL logic output
VHSW
AHSW
HAMPSW
3
Video ICs
BU38603 / BU38703 / BU38803
Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = 5V and fOSC = 8MHz)
•
Measurement
circuit
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
[Logic block]
(Logic: pins 24 to 80)
Operating supply current
Logic I / O
—
12
19
mA
No load, when reset
Fig.1
IDD
I = 2mA: except pins 66 to 73
I = 1mA: 66 to 73pin
4.0
4.5
—
V
Fig.2
Output high level voltage
VH
Output low level voltage
Max. output low level current
Input high level voltage
Input low level voltage
Input high level current
Input low level current
Serial I / O
—
10.0
4.0
0.5
16.0
—
1.0
—
V
mA
V
I = 2mA
Fig.2
Fig.2
Fig.2
Fig.2
Fig.2
Fig.2
VL
ILL
VIH
VIL
IH
66 to 73pin
—
—
—
1.0
1.0
—
V
—
0
µA
µA
VIN = VDD
VIN = 0
– 1.0
0
IL
Input data hold
Input data setup
Output data delay
0.16
0.16
—
—
—
—
—
—
µs
µs
µs
—
—
—
TSH
TSS
TD
Between CLOCK and DATA
No load
0.3
[Linear block] (Linear: pins 11 to 23)
—
10
26
mA
Fig.1
Operating supply current
[A / D block]
ILI
(A / D: pins 1 to 10)
—
– 3
4.0
—
0.6
0
2.0
3
mA
LSB
V
Fig.1
Fig.3
Fig.3
Fig.3
Fig.3
Fig.3
Operating supply current
Linearity error
IAD
EL
When P input selected
—
—
0
—
Input high level voltage
Input low level voltage
Input high level current
Input low level current
VADPH
VADPL
IADPH
IADPL
When P input selected
1.0
1.0
—
V
When P input selected, VIN = VDD
When P input selected, VIN = 0
—
µA
µA
– 1.0
0
4
Video ICs
BU38603 / BU38703 / BU38803
Measurement circuits
•
10
22
43
1k
1k
11
12
14
15
IclkI
I1in
A
A
A
V1
V4
A
B
C
63
SW1
B
TEST pin
SW4
C
xtal
A
B
C
62
V1out
V
SW2
I4
Iclko
A
24
1
10
64
V2
A
Itest
A
B
SW3
V3
Fig.1
Idad
Idda
A
Idd
A
A
10
22
43
1k
11
12
14
15
1k
A
B
63
62
SW2
SW3
xtal
SW1
A
B
A
18
B
SW4
2-9, 24, 27-36, 46-58
65-75, 77, 78
SW5
1
10
64
Fig.2
5
Video ICs
BU38603 / BU38703 / BU38803
10
22
43
Iadin
A
A
SW1
B
TEST pin (2-9)
V1
C
D / A
23
1
10
64
Fig.3
Application example
•
Capstan control
Drum control
Control
8MHz
PI / O
PWM
Interrupt
CPU
Serial bus
SI / O
ENVIN
ROM / RAM
Data shift
Head amplifier
· chroma
Head amplifier SW
Chroma rotary SW
AHSW
FRC
Timer
VHPULSE
Watchdog
Servo mode
CSYNC
Pattern generator
VHSW
Pseudo VSYNC
VISSVASS
Linear time counter
A / D
Count pulse
RESET
Amplifier gain control
CFG. CTL divider
CTL coil
REF
DFGAMP DPG CFGAMP voltage CTLAMP
DFG DPG CFG
Fig.4
6
Video ICs
BU38603 / BU38703 / BU38803
Electrical characteristic curves
•
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
18
16
14
12
10
8
6
4
2
0
– 30 – 10
10
30
50
70
– 30 – 10
10
30
50
70
– 30 – 10
10
30
50
70
TEMPERATURE: Ta (°C)
TEMPERATURE: Ta (°C)
TEMPERATURE: Ta (°C)
Fig. 7 Logic “L” output voltage.
Fig. 6 Logic “H” output voltage.
Fig. 5 Logic circuit current.
26
24
22
20
18
16
14
12
10
8
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
6
4
– 30 – 10
10
30
50
70
– 30 – 10
10
30
50
70
TEMPERATURE: Ta (°C)
TEMPERATURE: Ta (°C)
Fig. 8 Linear circuit current.
Fig. 9 A / D circuit current.
External dimensions (Units: mm)
•
24.0 ± 0.3
20.0 ± 0.2
64
41
40
25
65
80
24
1
0.15 ± 0.1
0.35 ± 0.1
0.8
0.15
QFP80
7
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