BU26156RFS_技术文档

Datasheet

24bit Audio CODEC series

3W+3W Class AB/D Speaker AMP

Stereo Audio CODEC

BU26156RFS

General Description

Important Characteristic

 Supply Voltage

SPLVDD,SPRVDD:

HVDD1:

BU26156RFS is Low Power Stereo Audio CODECs with

built-in various acoustic effects. BU26156RFS has stereo

line and monaural mic inputs that can input to 2Vrms,

stereo speaker amplifier that can change Class AB / D

and stereo Headphone Outputs.BU26156 also has

built-in voltage regulator for the stability of CODEC

characteristic that is sensitive to the outside noise.

2.7V to 5.5V

2.7V to 3.6V

1.65V to 5.5V

87[dB](Typ.)

93[dB](Typ.)

86[dB](Typ.)

95[dB](Typ.)

-20℃ to +85℃

HPVDD:

IOVDD:

 Mic-ADC SNR:

 Line-ADC SNR:

 DAC-SP SNR:

 DAC-LOUT SNR:

 Operating Temperature:

Features

 24bit Stereo ADC, DAC

 2Vrms Input available, Stereo Line Input with ALC

 Monoraul MIC Input with ALC

 Switch Class AB/D 3W Stereo Speaker Amplifier

 AM Avoidance Function

Package

W(Typ.) x D(Typ.) x H(Max.)

18.50mm x 9.50mm x 1.00mm

HTSSOP-A44R

 Stereo Headphone Output Amplifier

 Digital signal processing

 High Power Supply Rejection Ratio characteristic

Applications

 Radio cassette recorder

 PC Speaker

Figure 1. HTSSOP-A44R

Basic Block Diagram

Figure 2.

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

1/92

TSZ22111・14・001

Daattaasshheeeett

BU26156RFS

Pin Layout HTSSOP-A44R

Top View

1

2

3

4

5

44

43

42

41

40

HPOUTL

HPOUTR

HPGND

HPOUTCAP

NC

HPVDD

LIN3R

LIN3L

LIN2R

LIN2L

6

7

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

SPLVDD

SPLM

LIN1R

LIN1L

8

SPLP

VMID

9

SPLGND

SPRGND

SPRP

AGND

10

11

12

13

14

15

16

17

18

19

20

21

22

MINP

MINM

SPRM

PLLC

SPRVDD

SPMUTE

BEEPIN

MICBIASREF

MICBIAS

HVDD 1

AGND

MCLKI

BCLK

LRCLK

SDIN

SDOUT

IOVDD

IRQB

REGOUT

DGND

RESETB

CSB/SCL

SDATA/SDA

SCLK/SAD

Figure 3.

Pin Description

No

Name

I/O

I

Power

Function

Reset

(input)

No use

-

Reset pin

“L” level : Reset enable.

“H” level : Reset disable.

25

RESETB

IOVDD

3 wire interface: data input output pin

It is indicated as SDATA on the description

of AC characteristics.

SDATA

/SDA

23

22

IO

IOVDD

(input)

-

2 wire interface : data input output pin^(Note1)

It is indicated as SDA on the description

of AC characteristics.

3 wire interface : Serial clock input pin

It is indicated as SCLK on the description

of AC characteristics.

2 wire interface: Slave address pin

Future explanation indicates SAD.

Choose from the following two kinds.

SAD Pin=HGND : ”0011010”

SCLK

/SAD

I

DGND

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

2/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

SAD Pin=IOVDD : ”0011011”

3 wire interface : chip select input pin

It is indicated as CSB on the description of

AC characteristics.

CSB

24

I

IOVDD

(input)

-

/SCL

2 wire interface : Serial clock input pin ^(Note1)

It is indicated as SCL on the description of

AC characteristics.

30

31

29

28

32

26

38

39

40

41

42

43

35

34

LRCLK

BCLK

SDIN

SDOUT

MCLKI

IRQB

LIN1L

LIN1R

LIN2L

LIN2R

LIN3L

LIN3R

MINP

IO

I

O

I

O

I

IOVDD

SAI LR clock input/output pin

SAI bit clock input/output pin

SAI serial data input pin

SAI serial data output pin

Master Clock pin

(input)

DGND

(input)

IOVDD

(input)

DGND

Open

DGND

Open

Interrupt output Pin

REGOUT Line analog input Lch pin 1

REGOUT Line analog input Rch pin 1

REGOUT Line analog input Lch pin 2

REGOUT Line analog input Rch pin 2

REGOUT Line analog input Lch pin 3

REGOUT Line analog input Rch pin 3

REGOUT Analog microphone + input

REGOUT Analog microphone - input

Line input pin.

Open,

or coupling

capacitor

connected to

AGND near by

BU26156

I

MINM

The input signal for this pin can output

Headphone output pins or Speaker output

pins.

15

BEEPIN

I

REGOUT

(input)

External filter pin for microphone bias.

16

1

MICBIASREF

MICBIAS

VMID

O

HVDD1

A

capacitor is connected between

ANGD

AGND

Open

-

MICBIASREF and AGND.

Microphone bias voltage output pin

A

MICBIASCAP and AGND.

Analog reference voltage pin

capacitor is connected between

37

REGOUT A capacitor is connected between VMID

and AGND.

Regulator output pin

A

capacitor is connected between

20

REGOUT

O

HVDD1

REGOUT and HGND1.

Please put in the chip close as much as

possible.

AGND

-

8

7

11

12

SPLP

SPLM

SPRP

SPRM

O

SPLVDD speaker Lch output + pin

SPLVDD speaker Lch output - pin

SPRVDD speaker Rch output + pin

SPRVDD speaker Rch output - pin

SPLGND

SPRGND

Open

Test control pin “L” level : Release MUTE

“H” level : MUTE

14

SPMUTE

I

IOVDD

DGND

Open

1

2

32

HPOUTL

HPOUTR

LOUTCAP

O

HPVDD

HVDD1

Headphone Lch output pin

Headphone Rch output pin

Headphone Output capacitance pin

PLL filter pin

HPGND

AGND

Open

33

27

PLLC

O

P

REGOUT The width of the clock frequency to input

can be expanded.

AGND

-

Open

-

Interface Power Supply pin

IOVDD

-

A capacitor is connected between IOVDD

and HGND1.

Speaker Lch Power Supply pin

It is used on the same voltage as SPRVDD.

A capacitor is connected between SPLVDD

and SPLGND.

6

9

SPLVDD

SPLGND

SPRVDD

P

-

Speaker Lch ground pin

Speaker Rch Power Supply pin

It is used on the same voltage as SPLVDD.

A capacitor is connected between SPRVDD

and SPRGND.

13

10

18

SPRGND

HVDD1

P

-

Speaker Rch ground pin

-

High voltage power supply 1 pin

A capacitor is connected between HVDD1

and HGND1.

Analog ground pin

Digital ground pin

19, 36 AGND

21 DGND

P

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

3/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Headphone Power Supply pin.

A capacitor is connected between HPVDD

and HPGND.

44

HPVDD

P

3

5

HPGND

NC

P

-

Headphone ground pin.

No Connection pin. Set open this pin.

Open

(Note1)In case of 2 wire serial, if this pin is used with external pull-up resistor, it possibly gets noise from power. Therefore tamper noise design is required in

the noisy environment.

Application Examples

Figure 4. Application Examples1(Use internal speaker amplifier)

Figure 5. Application Examples2 (Use external speaker amplifier)

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

4/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Absolute Maximum Ratings

Parameter

Symbol

Condition

-

Rating

Unit

V

SPLVDD, SPRVDD Supply SPLVDD

Voltage

-0.3 to 7.0

SPRVDD

HPVDD Supply Voltage

HPVDD

-

-0.3 to 4.5

-0.3 to 7.0

V

HVDD1 Supply Voltage

IOVDD Supply Voltage

HVDD1

IOVDD

MCLKI, LRCLK, BCLK, SDIN,

SDATA/SDA, SCLK/SAD,

CSB/SCL, SPMUTE

-0.3 to IOVDD+0.3

-0.3 to REGOUT+0.3

-55 to +150

V

Input Voltage

V_IN

LIN1L, LIN1R, LIN2L, LIN2R,

MINL, MINR, BEEPIN

Storage Temperature

Package power dissipation

Output Current 1

Tstg

Θjc

-

°C

2

HTSSOP-A44R

℃/W

A

(Tjmax=+125℃)

SPLM, SPLP,

SPRM, SPRP

IOSP

IOLO

IOREGO

IOO

-1.0 to +1.0

-100 to +100

-30 to 0

Output Current 2

HPOUTL, HPOUTR

REGOUT

mA

Output Current 3

Output Current 4

All digital pins

-8 to +8

Do not short the output pin to another output pin, power supply pin or GND pin.

(Output pin includes an IO pin which is in output mode)

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over

the absolute maximum ratings.

Recommended Operating Condition

Parameter

Symbol

Condition

Rating

Unit

V

SPLVDD, SPRVDD Supply

Voltage

SPLVDD

SPRVDD

SPLVDD=SPRVDD

2.7 to 5.5

HPVDD Supply Voltage

HVDD1 Supply Voltage

IOVDD Supply Voltage

Operating Temperature

HPVDD

HVDD1

IOVDD

Top

-

2.7 to 3.6

1.65 to 5.5

-20 to +85

V

°C

*The radiation-proof design is not carried out.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

5/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Electrical Characteristics

DC Characteristics

(ALL GND terminals=0V, HVDD1=3.3V, IOVDD=3.3V, SPLVDD=SPRVDD=HPVDD=3.3V, Ta=25°C)

Uni

Parameter

Symbol

Condition

Min.

Typ.

Max.

Related Pin

t

RESETB,

SDATA/SDA,

SCLK/SAD,

CSB/SCL,

SPMUTE and

MCLKI pins.

LRCLK, BCLK

and SDIN

pins.

“H” Input

Voltage 1

VIH1

DGND=0V

IOVDD×0.8

-

IOVDD+0.3

V

“H” Input

Voltage 2

VIH2

DGND=0V

IOVDD×0.7

-

IOVDD+0.3

V

“L” Input

Voltage

“H” Output

Voltage

“L” Output

Voltage 1

All Digital

Input

VIL

DGND=0V

IOH=-1mA

IOL=1mA

-0.3

-

IOVDD×0.2

-

V

VOH

VOL1

IOVDD×0.85

-

Except SDA

IOVDD×0.15

IOL=3mA,

“L” Output

Voltage 2

VOL2

IIH1

IOVDD ≧2V

IOVDD <2V

-

0.4

IOVDD×0.2

V

SDA

“H” Input

Leakage

Current 1

“L” Input

Leakage

Current

Except

SPMUTE

VIH= IOVDD

VIL=DGND

-

10

-

µA

All Digital

Input

IIL

-10

-

“Z” Output

Leakage

Current

“Z” Output

Leakage

Current

IOZH

IOZL

VOH=IOVDD

VOL=DGND

10

-

SDA

-10

Stanby Current

-

HVDD1

IDDSH1

IDDSSP

0.1

10

µA

SPLVDD+SPR

VDD

-

RESETB=”L”

HPVDD

IOVDD

IDDSHP

IDDSIO

-

0.1

10

µA

Operating Current 1, DAC→mixvol→Headphone Output ( fs48kHz, No Load, No signal input, Sound effect off )

HVDD1

IDDO1H1

IDDO1SP

-

6.2

9.5

0.1

mA

Headphone Output,

No Load,

SPLVDD+SPR

VDD

0.02

No signal input,

Sound effect off

HPVDD

IOVDD

IDDO1HP

IDDO1IO

-

1.0

1.3

0.1

mA

0.03

Operating Current 2, DAC→mixvol→D-class Speaker Output ( fs48kHz, No Load, No signal input, Sound effect off )

HVDD1

IDDO2H1

IDDO2SP

-

6.2

3.3

5.0

8.2

7.4

-

mA

D-class Speaker

Output,

No Load,

No signal input,

Sound effect off

SPLVDD+SPR

VDD

SPLVDD+SPR

VDD

mA SPVDD=3.3V

IDDO2SP_5

mA

SPVDD=5V

HPVDD

IOVDD

IDDO2HP

IDDO2IO

-

0.03

0.1

mA

Operating Current 3, DAC→mixvol→AB-class Speaker Output ( fs48kHz, No Load, No signal input, Sound effect off )

HVDD1

IDDO3H1

IDDO3SP

-

6.2

5.0

8.2

9.6

mA

AB-class Speaker

Output,

No Load,

No signal input,

Sound effect off

SPLVDD+SPR

VDD

SPLVDD+SPR

VDD

mA SPVDD=3.3V

IDDO3SP_5

-

6.0

-

mA

SPVDD=5V

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

6/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

HPVDD

IOVDD

IDDO3HP

IDDO3IO

-

0.03

0.1

mA

Operating Current 4, MicIN→linemix→ADC ( fs48kHz, Sin1kHz-Full Scale input, Micbias Enable, Mic ALC off, Sound Effect

off )

HVDD1

IDDO4H1

IDDO4SP

-

12.3

0.02

16.9

0.1

mA

fs48kHz, No signal

input,,

Micbias Enable,

Mic ALC off,

SPLVDD+SPR

VDD

HPVDD

IOVDD

IDDO4HP

IDDO4IO

-

0.03

0.1

mA

Sound Effect off

Operating Current 5, LineIn→llinemix→ADC ( fs48kHz, Sin1kHz-Full Scale input, LineALC off, Sound Effect off )

HVDD1

IDDO5H1

IDDO5SP

-

11.2

0.02

13.8

0.1

mA

fs48kHz, No signal

input,

Line ALC off,

Sound Effect off

SPLVDD+SPR

VDD

HPVDD

IOVDD

IDDO5HP

IDDO5IO

-

0.03

0.1

mA

Operating Power

(ALL GND terminals=0V, IOVDD=3.3V, HVDD1=3.3V, SPLVDD=SPRVDD=5.0V, HPVDD=3.3V, Ta=25°C)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Regulator Output

REGOUT Output Level

BEEP Input

VREGOUT

-

1.7

1.8

1.9

V

Full Scale Input Signal Level

VBINFS

-

1

Vpp

Line Input ( R_LIN=22 kΩ / Line Gain=-9dB / Digital Volume=0.0dB / Line ALC=OFF )

LIN1L, LIN2L,

LIN3L, LIN1R,

Full Scale Input Signal Level

VLINFS

-

2.0

Vrms

LIN2R, LIN3R

Mic Input (MIC Gain=20.25dB / Digital Volume=0.0dB / Mic ALC=OFF)

Full Scale Input Signal Level

Input Resistance

VMINFS1

RMIN1

MINP,MINM

0.124

40

Vp-p

-

20

30

kΩ

Mic Input (MIC Gain=9.0dB / Digital Volume=0.0dB / Mic ALC=OFF)

Full Scale Input Signal Level

Input Resistance

VMINFS2

RMIN2

MINP,MINM

0.454

40

Vp-p

-

20

30

kΩ

Analog Reference Level(VMID-pin)

0.9x

1.0x

1.1x

Analog Reference Voltage

VREF

-

V

REGOUT/2 REGOUT/2 REGOUT/2

Microphone Bias(MICBIAS-pin)

IMIC = -2mA,

MICBCON=0

IMIC = -2mA,

MICBCON=1

IMIC = -2mA,

MICBCON=2

IMIC = -2mA,

MICBCON=3

1.51x

REGOUT/2 REGOUT/2 REGOUT/2

2.00x 2.22x 2.44x

REGOUT/2 REGOUT/2 REGOUT/2

2.51x 2.78x 3.05x

REGOUT/2 REGOUT/2 REGOUT/2

3.00x 3.33x 3.66x

REGOUT/2 REGOUT/2 REGOUT/2

1.67x

1.83x

V

Output Voltage

(VMIC<HVDD1*0.85)

VMIC

IMIC

V

Output Current

-

2

mA

(HGND1=0V, IOVDD=3.3V, HVDD1=3.3V, SPLVDD=SPRVDD=5.0V, HPVDD=3.3V, Ta=25°C, 1kHz signal, fs=48kHz)

Parameter Symbol Condition Min Typ Max Unit

Analog Line Input to ADC out (R_LIN=22kΩ/ Line Gain=0dB / LineMix Gain = 0dB / Digital Volume=0.0dB / Line ALC=OFF)

S/(N+D)

S/N

SND1

SNR1

-1dBFS/ A-weighted

A-weighted

-

81

93

-

dB

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

7/92

Daattaasshheeeett

BU26156RFS

HVDD1 on 100mVp-p,

1kHz ripple,

Power Supply Rejection Ratio

PSRR1

-

90

-

dB

no signal input

Analog Mic Inputs to ADC out (MIC Gain=20.25dB / Line Mix Gain = 0dB / Digital Volume=0.0dB / Mic ALC=OFF)

S/(N+D)

S/N

SND2

SNR2

-1dBFS/ A-weighted

A-weighted

-

79

81

-

dB

HVDD1 on 100mVp-p,

1kHz ripple,

Power Supply Rejection Ratio

PSRR2

-

89

-

dB

no signal input

Analog Mic Inputs to ADC out (MIC Gain=9.0dB / Digital Volume=0.0dB / Mic ALC=OFF)

S/(N+D)

S/N

SND3

SNR3

-1dBFS/ A-weighted

A-weighted

-

80

87

-

dB

HVDD1 on 100mVp-p,

1kHz ripple,

Power Supply Rejection Ratio

PSRR3

-

90

-

dB

no signal input

DAC to Headphone OUT (HPOUTL/HPOUTR, with 220µFcuppling 16Ω load)

Output Power

Po4

THD+N=1%, RL=16Ω

-

60

79

90

-

mW

dB

-6dBFS input

/ A-weighted

Total Harmonic Distortion

Signal to Noise Ratio

THD4

SNR4

A-weighted

dB

HPVDD on

100mVp-p,1kHz ripple,

no signal input

HVDD1 on

100mVp-p,1kHz ripple

-

60

80

-

dB

Power Supply Rejection Ratio

PSRR4

DAC to Class-AB Speaker OUT (SPLP/SPLM, SPRP/SPRM, with 8Ω / 50pF load )

SPMIXG=12dB,

Output Power

Po5-1

Po5-2

Po5-3

Po5-4

-

1.4

1.7

2.5

3

-

W

RL=8Ω,THD=1%

SPMIXG=12dB,

RL=8Ω,THD=10%

SPMIXG=12dB,

RL=4Ω,THD=1%

SPMIXG=12dB,

RL=4Ω,THD=10%

Po=1W, RL=8Ω

/ A-weighted

1.5

2

Total Harmonic Distortion

Signal to Noise Ratio

THD5

SNR5

-

62

91

60

-

dB

A-weighted

SPLVDD/SPRVDD on

100mVp-p,1kHz ripple

HVDD1 on

Power Supply Rejection Ratio

PSRR5

-

80

-

dB

100mVp-p,1kHz ripple

DAC to Class-D Speaker OUT (SPLVDD=SPRVDD=5V,SPLP/SPLM, SPRP/SPRM, with 8Ω / 50pF load )

SPMIXG=12dB,

Output Power

Po6-1

Po6-2

Po6-3

Po6-4

-

1.4

1.7

2.5

3

-

W

RL=8Ω,THD=1%

SPMIXG=12dB,

RL=8Ω,THD=10%

SPMIXG=12dB,

RL=4Ω,THD=1%

SPMIXG=12dB,

RL=4Ω,THD=10%

Po=1W, RL=8Ω

/ A-weighted

1.5

2

Total Harmonic Distortion

Signal to Noise Ratio

THD6

SNR6

-

62

89

72

-

dB

A-weighted

SPLVDD/SPRVDD on

100mVp-p,1kHz ripple

HVDD1 on

Power Supply Rejection Ratio

PSRR6

-

80

-

dB

100mVp-p,1kHz ripple

Class D oscillator frequency (AM Avoidance)

AM0

AMA[1:0]=0b00

AMA[1:0]=0b01

AMA[1:0]=0b10

360

450

540

400

500

600

440

550

660

kHz

Oscillator frequency

AM1

AM2

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

8/92

Daattaasshheeeett

BU26156RFS

AM3

AMA[1:0]=0b11

630

700

770

kHz

Microphone Bias (MICBIAS-pin)

22Hz to 22kHz,

VMIC =1.67 x

REGOUT/2

Output Noise Voltage

VMICN7

PSRR7

-

5

-

µV

dB

HVDD1 on

100mVp-p,1kHz ripple

Load=1mA

Power Supply Rejection Ratio

80

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

9/92

Daattaasshheeeett

BU26156RFS

AC Characteristics

Clock

PLL not use

(DGND=0V, IOVDD=3.3V, HVDD1=3.3V,Ta=25°C)

Min

2.048M

1/fC

Max.

Unit

Hz

s

Parameter

Symbol

fC

MCLKI Frequency

MCLKI Period

MCLKI Length

49.152M

tC

1/fC

tCH

tCL

tC*0.4

-

s

PLL use (External Loop back filter not used)

(DGND =0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C)

Min

2M

Max.

54M

1/fC

-

Unit

Hz

s

Parameter

MCLKI Frequency

Symbol

fC

tC

MCLKI Period

MCLKI Length

1/fC

tCH

tCL

tC*0.4

s

-

s

PLL use (External Loop back filter used)

(DGND =0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C)

Min

32k

Max.

2M

1/fC

-

Unit

Hz

s

Parameter

MCLKI Frequency

MCLKI Period

Symbol

fC

tC

1/fC

MCLKI Length

tCH

tCL

tC*0.4

s

MCLKI Length

-

s

tC, fC

MCLKI

tCH

tCL

Figure 6.

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

10/92

Daattaasshheeeett

BU26156RFS

Reset

(DGND =0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C)

Min

5

Max.

Unit

Parameter

RESETB pulse width

Symbol

tW_RST

-

µs

tW_RST

RESETB

Figure 7.

When Reset pin is made Low level, internal LDO is power down mode.

It is necessary for 1ms until REGOUT pin becomes Low level. The recommendation of tW_RST is 1ms over.

2 wire serial interface

(DGND =0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C, CL=30pF)

Standard Mode

Fast Mode

Unit

Parameter

Symbol

Min

-

Max.

Min

-

Max.

SCL Frequency

SCL “L” Length

SCL “H” Length

100

400

kHz

µs

f_SCL

t_LOW

t_HIGH

4.7

4.0

-

1.3

0.6

-

µs

Hold time under Repeat [Start] Condition

Setup Time under Repeat[Start] Condition

4.0

-

0.6

-

µs

t_HD:STA

t_SU:STA

Data Hold Time

Data Setup Time

0

3.45

-

0

0.9

-

µs

ns

t_HD:DAT

t_SU:DAT

250

100

Setup Time under [Stop] Condition

4.0

-

0.6

-

µs

t_SU:STO

t_HD:STA

SDA

t_SU:DAT

t_LOW

SCL

t_HD:DAT

t_HIGH

t_SU:STA

t_SU:STO

Figure 8.

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

11/92

Daattaasshheeeett

BU26156RFS

3 wire serial interface

(DGND=0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C, CL=30pF)

Parameter

Symbol

tSLCL

Min

Max.

Unit

SCLK Low to Chip Select enable

Chip Select enable to SCLK Low

100

-

ns

tCLSL

tCLSH

tSHCL

tSH

100

50

-

ns

Chip Select enable to SCLK High

SCLK High to Chip Select enable

SCLK High Pulse Width

-

ns

SCLK Low Pulse Width

tSL

50

-

Input Data Setup time

tIDS

30

100

-

Input Data Hold time

tIDH

-

ns

SCLK last edge to Chip Select disable

Chip Select High Pulse Width

Output Data Valid

tCHS2

tCH

-

tODV

tCHDTS

40

Chip Select High to Data Transition

-

Two kinds of timing is supported depends on the SCLK pin level at data transfer start. Read or Write is selected by LSB level

of INDEX.

CSB

SCLK

SDATA

Figure 9.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

12/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Serial Audio Interface (Slave)

(DGND=0V, IOVDD=3.3V, HVDD1=3.3V, Ta=25°C, CL=30pF)

Parameter

Symbol

Min

32fs

73

20

-

Max.

Unit

Hz

ns

SAI_BCLK Period

tC_BCLK

128fs

SAI_BCLK “H” Length

SAI_BCLK “L” Length

SAI_LRCLK Hold Time

SAI_LRCLK Setup Time

SAI_SDOUT Delay Time

SAI_SDIN Setup Time

SAI_SDIN Hold Time

tHW_BCLK

tLW_BCLK

tH_LRCLK

tSU_LRCLK

tD_SDO ^(Note1)

tSU_SDI

-

80

-

20

tH_SDI

-

(Note1) tD_SDO is the delay time from later one of SAI_BCLK transition and SAI_LRCLK transition.

LRCLK

tC_BCLK

tH_LRCLK

tSU_LRCLK

BCLK

tHW_BCLK tLW_BCLK

SDOUT

tD_SDO

SAI Transmit

Figure 10.

LRCLK

BCLK

SDIN

tC_BCLK

tH_LRCLK

tSU_LRCLK

tH_SDI

tSU_SDI

tHW_BCLK tLW_BCLK

SAI Receive

Figure 11.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

13/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Power Supply Sequence

Please power on/off the LSI with all kind of power at the same time.

Each power supply should power up/down in 50ms.Also keep all power supply in the ON state or the OFF state.

Please avoid partial ON or partial OFF states.Don’t have to keep the sequence of power on/off

Please keep RESETB pin “L” level until all power supply become ON state. The CPU I/F available when all power supply

are powered on, exceed tW_PURST, RESET are disabled and exceed tW_{_REGU}. It is regardless that turn of power on and off

of IOVDD and HVDD.

Parameter

Power On Delay Time

Symbol

Min

Typ Max Unit

t_{VDD_ON}

t_{VDD_OFF}

t_{w_PURST}

t_{w_REGU}

0

1

-

50

-

ms

µs

Power Down Delay Time

Reset Time after Power ON

Wait time for Regulator starting after reset

release

-

ms

PowerSupply*0.9

t_{VDD_ON}

IOVDD

Power

supply

PowerSupply*0.1

t_{VDD_OFF}

Other

Power

supply

PowerSupply*0.9

t_{W_PURST}t_{W_REGU}

PowerSupply*0.1

REGOUT

RESETB

CPU I/F

not available

VDD OFF

available

not available

VDD OFF

Wait

PowerDown

STATUS

Operation

Regulator

Figure 12.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

14/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Function Description

Clock control

Main modules that make up sound path of the LSI inside operate with 256fs Audio Clock.

Audio Clock can be selected whether divided clock of 256fs/512fs/1024fs from MCLKI or generated clock from Audio PLL.

In case of used external loop filter of PLL, input clock must be 2MHz to 54MHz frequency. In case of not used external filter

of PLL, input clock must be 32 kHz to 2MHz frequency. It is possible to select internal clock either MCLKI port or LRCLK port

or BCLK port.

Internal Clock is selected Clock Input/Output Control Register. These frequency mean 512fs and master clock is divided by 2

from PLL output when sampling frequency is 16 kHz to 24 kHz, and these frequency mean 1024fs and master clock is

divided by 4 from PLL output when sampling frequency is 8 kHz to 12 kHz.

･･PLL condition setting (changing) sequence

1. Stop PLL output by setting PLLOE bit to “0”

2. Disable PLL by setting PLLEN bit to “0”

3. Set FPLLM, FPPNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH

4. Set PLLEN bit to “1”

5. Wait for the PLL stabilizing time as the table “PLL Stabilizing Time”

6. Set PLLOE bit to “1”

7. Start recording or playback.

PLL Stabilizing Time

10msec

- Related Register

Sampling Rate Setting Register

FPLLM, FPPNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH Register

Clock Enable Register

Clock Input/Output Control Register

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

15/92

TSZ22111・15・001

Jul.1.2014 Rev.001

Daattaasshheeeett

BU26156RFS

When pll is used.

The LSI support audio PLL function that can generate precise audio clock from wide range of clock frequency. Then, it can

be realize audio function without external clock generator for audio. The LSI supports following cases.

■ case 1: PLLISEL=0 or 2, MST=0, MCLKOE=0

Audio PLL generate system clock as 256fs from LRCLK

BU26156

LRCLK

BCLK

SDIN

CPU

SDOUT

MCLKI

Figure 13.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

16/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

When PLL is not used.

Please generate Audio clock on the CPU and supply to the LSI when PLL is not used. Then CPU and the LSI are

synchronized.

■case 2: MST=“0”, MCLKOE=“0”

Audio Clock is generated by the CPU and supplied to MCLKI pin of the LSI. LRCLK and BCLK are also provided from the

CPU.

BU26156

LRCLK

BCLK

SDIN

CPU

SDOUT

CLOCK

MCLKI

Figure 14.

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

17/92

Daattaasshheeeett

BU26156RFS

Serial Audio Interface

The LSI supports SAI formats.

WSLI=“0”, DLYI=“0”, FMTI=“0”

SAI_

Right

Left

LRCLK

1

2

3 ……………16…………

1

2

3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

LSB

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 15.

WSLI=“1”, DLYI=“0”, FMTI=“0”

Left

Right

Left

SAI_

LRCLK

1

2

3 ……………16…………

1

2

3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

LSB

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 16.

WSLI=“0”, DLYI=“1”, FMTI=“0”

SAI_

LRCLK

Left

Right

1

2

3 ……………16…………

1

2

3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

LSB

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 17.

WSLI=“1”, DLYI=“1”, FMTI=“0”

SAI_

LRCLK

Right

Left

3SB

Left

1

2

3 ……………16…………

1

2

3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

LSB

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 18.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

18/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

DLYI=“0”, FMTI=“1”

Flame synchronous transfer mode: R channel data is transferred right after L channel data.

SAI_

LRCLK

Left

2

Right

Left

1

3 ……………16

1

2

3 ……………16…………

SAI_SDIN

SAI_SDOUT

3SB

LSB

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 19.

DLYI=“1”, FMTI=“1”

Flame synchronous transfer mode: R channel data is transferred right after L channel data.

SAI_

LRCLK

Right

Left

1

2

3 ……………16

1

2

3 …………16…………

SAI_SDIN

SAI_SDOUT

3SB

MSB 2SB

LSB

SAI_BCLK

Figure 20.

- Related Register

SAI Transmitter Control Register

SAI Receiver Control Register

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

19/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

2 wire serial interface

This LSI has 2 wire serial interfaces. The LSI operates as a slave device. The address is fixed at “0011010”.

- Format

The followings are the protocol of the LSI.

Write (MSB first)

Start Condition (Set SDA level from “H” to “L” during SCL=“H”)

Slave Address (0011010) +W (0) (8bit)

Write Address (8bit)

Write Data (8bit)

…

Stop Condition ( Set SDA level from “L” to “H” during SCL=“H”)

Read (MSB first)

Start Condition

Slave Address (0011010) +W (0) (8bit)

Read Address (8bit)

(Stop Condition) Start Condition

Slave Address (0011010) +R (1) (8bit)

Read Data (8bit)

The following shows the wave form of the LSI.

The yellow gridding shows that slave device drives the bus.

The symbol in the wave form means as following table.

Unit

W/R

Description

0: Write 1: Read

A

0: ACK(Acknowledge) 1: NAK(Not Acknowledge)

A[7-0]

D[7-0]

Address (8bit)

Data(8bit)

Write

slave address reception

Access address reception

Write data reception

Start

0

1

2

3

4

0

5

1

6

0

7

8

0

1

2

3

4

5

6

7

8

SCL

SDA

0

1

2

3

4

5

6

7

8

A

0

1

A7 A6 A5 A4 A3 A2 A1 A0

W

D7 D6

D1 D0

D5 D4 D3 D2

Write data reception

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

Stop

Continued

from the

above

A

D7 D6

D1 D0

D5 D4 D3 D2

D7 D6

D1 D0

D7 D6

D1 D0

D5 D4 D3 D2

Internal write

Figure 21.

In case there is no Stop or Start condition after internal register is written (Above figure: Internal Write), the slave device

becomes continuous write mode and the next received 8 bits of data will be written into the internal register addressed by

incremented by two to the current address.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

20/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Read

slave address reception

Access address reception

Start

SCL

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

S

SDA

A

0

1

0

1

0

W

A7 A6

A1 A0

A5 A4 A3 A2

slave address reception

Read data transmission

Start

0

1

2

1

3

1

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Continued

fromthe

above

A

D7 D6 D5 D4 D3 D2 D1 D0

0

A

D7 D6 D5 D4 D3 D2 D1 D0

R

A

0

1

Internal read

Figure 22.

If the Master device returns ACK (acknowledge) after the 8 bit data transferred from the LSI becomes continuous read mode.

The next received 8 bits of data will be read from the internal register addressed by incremented by two to the current

address.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

21/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Analog Block Gain Diagram

＜Mic input＞

MALCMXGAIN (0xbe/0xbf)

0～+35.25dB / 0.75dB step

MALC

＜BEEP input＞

0dB

ON/OFF ： MALCEN (0xba/0xbb)

Limit Level ： 0dBV ( =1Vrms)Fixed

→ ADC input full scale level

MINP

MINM

＜Speaker output＞

SPMIXG(0x52/0x53)

0 / +6 / +12 / +18dB

＜Mixvol＞

SPVOL (0x3a/0x3b)

-56～+6.0dB

LIN1L

SPLP

SPLM

LIN2L

AB/D

VOL

Σ

DAC

Σ

ADC

LIN3L

(Analog) (Digital)

0dBV → 0dBFS

(Digital) (Analog)

0dBFS → 0dBV

LIN1R

LIN2R

LIN3R

SPRP

SPRM

DAC

Σ

VOL

Σ

ADC

＜Line input＞

LALCMXGAIN (0xc8/0xc9)

-9.0～+6.0dB / 0.75dB step

LALC

ON/OFF ： LALCEN (0xc4/0xc5)

Limit Level ： 0dBV ( =1Vrms)Fixed

→ ADC input full scale level

HP

HPOUTL

HPOUTR

VOL

Σ

Serial Audio Interface

＜Line output＞

HPVOL

([mapcon1]0x36/0x37)

-6 / 0 / +3 / +6dB

Figure 23.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

22/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

State transition regarding SAI input and output control.

The following shows state transition about sound control. A change state is carried out by RECPLAY bit setup.

stop state

0x0

[ADC→SAI]

[SAI→DAC]state

state

0x1

0x2

[ADC→DAC]state

[ADC→DAC&SAI]state

0x7

0x3

Figure 24.

(1) Stop STATE (RECPLAY=0x0)

Sound activity is stopped.

(2) [ADC→SAI] STATE (RECPLAY =0x1)

Analog input signal (MIC input/LINE input) is converted to digital data and outputted from SAI terminals.

(3) [SAI→DAC] STATE (RECPLAY =0x2)

Digital signal from SAI is converted to analog data and it is outputted from speaker or line amplifier.

(4) [ADC→DAC] STATE (RECPLAY =0x7)

Analog input signal (MIC input/LINE input) is converted to digital data and outputed speaker or line amplifier through DAC.

(5) [ADC→DAC & SAI] STATE (RECPLAY =0x3)

Analog input signal (MIC input/LINE input) is converted to digital data and outputed from SAI terminals.

At one time, digital signal inputted from SAI is converted to analog data and it is outputted from speaker or line amplifier.

Set this state for using SDIN to SDOUT path when LINDACEN bit enable.

*Please don’t use “DAC output to LIMIX path” with path (4) and path (5).

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

23/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Signal Flow

ADC used signal flow

From DAC

MALC

From

Mic

VOL

DV

MUTE

Filter Block

From

Line

LIN

VOL

L/R

Balance

L/R

Select

Serial

Audio IF

RALC

VOL

LIN MIX

ADC

HPF1

HPF2 *1

Filter

RDVOL

LPF *1

*1 exclusive use

LALC

Figure 25.

Related Register

Name

Function

Setting

MIC ALC Control

MIC ALC Max Gain

Analog Input Power Management

Line ALC Control

Line ALC Max Gain

Analog Input Power Management

Mic ALC

MICVOL

0dB to +35.25dB, 0.75dB step

-15 to +0dB, 1dB step

Analog Microphone volume and ALC

Analog line input volume and ALC

LineIN ALC

LINVOL

Analog input control.from Mic, Line

and DAC.

Mixing control

Mixing the LINE input, MIC input and Line In Control

LIN MIX

outputted signal from DAC

Analog Path Control

ADC

24bit AD Converter

Analog Input Power Management

ADC Enable/Disable

[ I2SL / I2SR / MONOREC]

Record L/R Balance Volume Control

L/R Select

ADC(Lch/Rch) to Audio Bass

-6.0dB to 6.0dB(0.1step)

HPF1

DSP Filter Function Enable

HPF Enable/Disable

High path filter for DC cut

L/R balance volume control

[ RBVOLL / RBVOLR ]

Record L/R Balance Volume Control

L/R Balance

-6.0dB to 6.0dB(0.1step)

HPF Enable/DIsable setting

order setting

Cut-off frequency setting

DSP Filter Function Enable

High Pass Filter2 Cut-off Control

HPF2

Filter

High pass filter for ADC

Sound filters setting

Sound Effect Mode

Sound effect mode setting.

Each filters Enable/Disable.

Each filter gain settings.

Each sound effects characteristics

setting

DSP Filter Function Enable

EQ Band N Gain Setting

Programmable

EQ Band N Coeffeicient-a0/1

LPF Enable/DIsable setting

Order setting.

Cut-off frequency setting

Rec Programmable LPF Setting

Rec Programmable LPF Cutoff Coef

LPF

Programmable LPF setting for ADC

Digital Boost Volume for ADC

Recording Digital Boost Volume

Register

RALCVOL

-12.000d to 35.625dB(0.375Step)

Volume setting -71.5dB to 0dB

(0.5dBstep)

Fader enable/disenable setting

(working together DVMUTE)

Record Digital Attenuator Control

Digital Volume Control

Function Enable

RDVOL

Digital attenuator and fader for ADC

Mixer & Volume Control

*Filter Block can be used for either ADC path or DAC path.

For example, if Filter Block is connected to DAC, ADC is not effected by filter.

Regarding the detail of register setting, please refer to selection of [SEMODE] register.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

24/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

DAC used singal frow

From BEEPIN

From Line

From Mic

DV

MUTE

AV

MUTE

*2 Class-D only

PALC

Filter Block

Stereo

Enhancer

Soft

Clip

To

Speaker

Serial

Audio IF

Effect

VOL

PALC

VOL

L/R

MIX

SPMUTE

*2

Filter

DAC

MIX1

SPVOL

SPMIXG

LPF

PDATT

MIX2

MIX3

*1 exclusive use

To

HPVOL

Headphone

To

LIN MIX

Figure 26.

Name

Function

Related Register

Setting

L/R MIX

Lch/Rch mixer for SAI input signal

Mixer & Volume Control

Mixer setting

Effect

Vol

Stereo

Digital volume in front of sound effect

blocks.

Playback Effect Volume

Stereo Gain

-71.5dB to 0dB (0.5dBstep)

3D effect

Stereo enhancer.

Enhancer

Sound Effect Mode

Sound effect mode setting.

Each filters Enable/Disable

Each filters gain setting

Each sound effects characteristics

setting

DSP Filter Function Enable

EQ Band N Gain Setting

Programmable EQ Band

N Coeffeicient-a0/1

Each sound filters are enabled.

Filter

HPF Enable/Disable setting

Order setting

Cut-off frequency setting

Play Programmable LPF Setting

Play Programmable LPF Cutoff Coef

LPF

Programmable LPF for DAC path.

Digital Playback ALC and Volume

Playback ALC Attack Time Control

Playback ALC Decay Time Control

Playback Target Level Control

Playback ALC Min Gain Control

Playback ALC Volume Control

Playback ALC Zerocross Timeout

Playback Limiter Fast Release Setting

PALC

PALCVOL

ALC operation settings

Playback Digital Attenuator Control

Digital Volume Control Function -71.5dB to 0.5dB (0.5dBstep)

Enable

Mixer & Volume Control

Volume setting

Digital Attenuator for DAC path.

Fader for noise reduction at changing the

digital volume

PDATT

Fader ON/OFFsetting

Fade time setting

Soft Clip Enable

Soft Clip Threshold

Soft Clip Gain

Softclip Enable/Disable

Threshold level, Gain setting

Soft Clip

Softclip limiter for output suppression

DAC

24bit DA Converter

DAC Power Management

DAC Enable/Disable

Gain setting

Mixing paths setting

MIX1

Mixing DAC output and analog input.

Speaker Amplifier Output Control 2

Speaker Amplifier Volume Control

Analog Volume for DAC to analog output Amplifier Volume Fader Control

Volume setting

-54 to +6dB

SPVOL

path.

Amplifier Volume Control Function Fader ON/OFF setting

Enable

Fade time setting

SPMIXG

MIX2

Analog Volume for Speaker output path

Speaker Amplifier Output Control 1

Gain setting

SPAMP input Control

BEEPIN Amp Control

Mixing Speaker output signal and

BEEPIN input signal.

Mixing paths setting

Gain setting

SPAMP input Control

BEEPIN Amp Control

Mixing Headphone output signal and

BEEPIN input singlal.

MIX3

Analog Volume for Headphone output

path

HPVOL

Headphone output Gain Setting

*Filter Block can be used for either ADC path or DAC path.

For example, if Filter Block is connectd to DAC, ADC is not effcetd by filter.

Regadrding the detail of register setting, please refer to selection of [SEMDE] register.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

25/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Filter (5bands-Programmable IIR Filter)

A five bands equalizer features a second-order IIR type Band Pass Filter. Volume control of MUTE, -71.5dB+12dB (0.5dB

step) can be controlled at all paths.

Each channels of the filter can be selected parallel connection or serial connection

The followings are block diagrams at parallel connection and serial connection

Coefficient(a0, a1)×5ch

gain×5ch

Input

Band0-IIR

Band1-IIR

Band2-IIR

Band4-IIR

Coefficient(a0, a1)×5ch

gain×5ch

Input

Output

Band0-IIR

Band1-IIR

Band2-IIR

Band3-IIR

Band4-IIR

Output

Parallel connection

Figure 27.

Serial connection

Figure 28.

The filter coefficient is programmable. From required center frequency and band width, Programmable Equalizer

Coefficient-a0 Control Register and Programmable Notch Filter Coefficient-a1 Control Register value is decided. Followings

are the setting formula.

a0 = (1 - tanπf_b/fs) / (1 + tanπf_b/fs)

a1 = - 2cos2πf₀/fs / (1 + tanπf_b/fs)

f0: Band center frequency [Hz]

fb: -3dB band width [Hz]

fs: Sampling frequency [Hz]

* Actual setting value is an integral number that the result of above formula multiplied by 2¹⁴then round up numbers of five

and above and round down anything under five to an integer.

DSP filtering function: ON / OFF

DSP Filter Function Enable register can set ON or OFF of each filter function. Please change this register when RECPLAY

bit is 0x0. If this register is changed on playback or recording, the noise may be generated.

Stereo Enhancer

Please refer the application note “StereoEnhancerApplicationNote””.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

26/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

PALC (ALC fo DAC path)

Function outline

The PALC adjust a gain automatically from -12dB to 35.625dB in DAC path.

A small level singal is made easy listening because the small level signal is amplified to a target level and dynamic range is

compressed when the gain setting is a plus gain

Or PALC can be used for a limiter when the gain setting is a minus gain. It protects a speaker from destruction.

Fast release function makes play sound natural by it release the gain fast when a big singal is suddenly input and a volume

drops.

Operation outline

When output waveform level of ALC is under the target level, output waveform is increased. Maximum level of gain is

MALCMXGAIN or LALCMXGAIN. Maximum alc gain is PALCVOL and minimum level is PALCMINGAIN.

PALCATKC is attack time. It is a time step of decreasing waveform level. PALCDCY is decay time. It is a time step of

increasing waveform level.

These operations are the following.

*Note:When ALC is disable, output signal is also amplified to PALCVOL gain level.

Input signal

Maximum gain

(PALCVOL)

PALC gain

Minimum gain

(PALCMINGAIN)

Target level

(PALCLVL)

PALC output

Attack time cycle

(PALCATK)

Decay time cycle

(PALCDCY)

Figure 29.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

27/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

A Peak Limiter function is carried in ALC. The Peak Limitter function short attack time and prevent clipping a wave.

A threshold level is fixed at 87.5%(-1.16dBFS) and this function is priored the normal ALC operation when input level exceed

the threshold level. The attack time is a minimum step, 1/fs, when the peak limiter operates.

And this function cannot be turned off.

These operations level diagram is the following figure.

0dBFS

Peak Limiter=-1.16dBFS

ALCLVL

Output

(dB)

Input

(dB)

Figure 30. ALC Level diagram

Zero Cross

BU26156 combined Zerocross function for MALC, LALC. Zerocross is changed, when input waveform is crossed center

level. In case of Zero Cross function is not occurred, BU26156 changes gain when time set by PALCZCTM is passed

BU26156 also changes gain past that time when zerocross is enable (ZCEN=0x0). It is often caused POP noise to change

gain without zero cross.

ALC GAIN

Output Signal

ALCATK

ALCATK ALCATK

ALCZCTM

Gain changing at

zerocross

Figure 31.

Note:It is possible that a noise of changing the gain occur when ZCEN is disable.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

28/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Fast Release

In case of input impulse waveform is over target level of ALC, fast release function detects impulse waveform and LSI is

returned until normal waveform level quickly. As result of quick return, output waveform of LSI is kept natural sound.

Inpulse waveform

4

3

2

1

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

1

0

1

0

1

2

0

Input waveform

-

1

2

3

4

Waveform is low level

Output waveform

Not use fast release

Attack

Quick return from low level waveform

Output waveform

Return to normal release

Release time of fast release

Attack

Figure 32. Not Fast release waveform and Fast release waveform

PALCFREN bit is setted enable of fast release function. When impulse waveform is over threshold of PALCFRTH level, fast

release function is started and is returned waveform until detected level by fast release decay time. This decay time is

selected PALFRSP bit.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

29/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

MALC (Mic Input ALC)/LALC (Line input ALC)

Function general description

MALC can be adjusted mic input gain from 0dB to +35.25dB. LALC can be adjusted line input gain from -15dB to 0dB.

Operation general description

MALC and LALC are fixed ADC full-scale level. When output waveform level of ALC is under the target level, output

waveform is increased. Maximum level of gain is MALCMXGAIN or LALCMXGAIN. Minimum level of gain is 0dB, when

MALC is used. Minimum level of gain is -15dB, when LALC is used. MALCATK and LALCATK are attack time. It is a time

step of decreasing waveform level. MALCDCY and LALCDCY is decay time. It is a time step of increasing waveform level.

These operations are the following.

* In case of MALC, LALC are disabled, output waveform is effective MALCMXGAIN and LALCMXGAIN setting gain.

Input waveform

Maximum gain

(MALCMXGAIN

/LALCMXGAIN)

MALC/LALC

Gain

Minimum gain

(Fix to MALC=0dB

/LALC=-15dB)

Target Level

(Fix to ADC full-scale

level)

MALC/LALC

Output

Attack time period

(MALCATK/LALCATK)

Figure 33.

Zero Cross

BU26156 combined Zerocross function for MALC, LALC. Zerocross is changed, when input waveform is crossed center

level. In case of Zero Cross function is not occurred, BU26156 is changed gain after 2.7ms @Fs=48 kHz.

Clip reduction

Clip reduction function prevents clip waveform. When BU26156 is entered large waveform, BU26156 is shorted attack time.

As result of this operaiontion, output waveform is prevented clip waveform. When this function is enabled, attack time is fixed

2fs and zerocross is disabled. The difference between peak limiter and clip reduction is threshold and attacktime. Threshold

of Clip deduction is ADC full scale level. Attack time of clip reduction is 2fs. It is possible to select ON/OFF register setting.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

30/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Soft clip limiter

Soft clip function is reduced power comsumption. If ALC can not be responded to input waveform, soft clip function is

reduced input waveform. In case of input waveform is overed threshold level, soft clip reduce output waveform.

SCGAIN=2

SCGAIN=1

SCGAIN=1/2

SCGAIN=1/4

SCGAIN=1/64

Soft Clip Gain

(SCGAIN)

Soft Clip Threshold

(SCTHRH, SCHTRM, SCHTRL)

0xFFFFFF

0x000000

IN

Figure 34.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

31/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Analog block

Analog Reference Voltage (VMID) Generation Circuit

VMID is used as analog circuit reference voltage for both recording path and playback path. Therefore, both case for

recording and playback, VMID need to do power up. At the power up, the wait time in proportion to the capacitor value is

needed to charge external capacitor connected with VMID pin. If recording and playback start before completion of charge, it

may generate noise. The following is a sequence of recommendation. Refer to the Analog Reference Power Management

Register for the function of VMIDCON.

VMID Power UP/DOWN Sequence (External capacitor 1uF)

Power Up

Power Down

1/2 Regout Level

vmid

( 0V )

Power Down Charge Time

Record or Playback Power Down

0x0

VMIDCON

0x0

0x2

0x1

Min 5ms

Figure 35.

Interrupt circuit

It is possible to check BU26156 operation by IRQ port. IRQ port polarity is changed by thermal protection operation and

speaker short protection operation. IIt is possible to mask Interrupt function and select IRQ interrupt polarity.

In case of BU26156 detects protection operation, BU26156 keeps interrupt status. In case of clear interrupt status, write to

“1” to status register.

IRQB teminal outputs “L” level during RESETB equal “L” level (RESET state). Please mask IRQB signal in this period

RESETB

IRQB

Valid

Min: 1ms

Figure 36.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

32/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Detailed Description of the Registers

Register map

Note: “-” indicates a reserved bit. They return “0” for reads. Write “0” to the bit every time. If “1” is written to this bit, the

operations cannot be guaranteed.

Don't write the registers expect the map of below. If these register is written, the operations cannot be guaranteed.

About the register initial setting after starting this IC

After starting register access, according to following procedures at start-up, access register.

Address

(HEX)

Write Data

(HEX)

Read/Write

Description

1c

39

3b

3d

1c

Write

01

00

01

02

00

MAPCON 1

For ADC parameter setting

For ADC / Mic parameter setting

For ADC parameter setting

MAPCON 0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

33/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

It is available at the MAPCON=0x0(Register Map Control Register 0x1c/0x1d)

以下のレジスタはRegister Map Control レジスタ（0x1c/0x1d）のMAPCON=0x0 のときにアクセス可能です。

INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

(Initial)

SR

0x00

0x06

0x08

0x0a

0x0c

0x0e

0x10

0x12

0x14

0x1c

0x20

0x22

0x24

0x26

0x2a

0x2e

0x30

0x32

0x3a

0x3e

0x48

0x4a

0x4c

0x4e

0x50

0x52

0x54

0x58

0x5a

0x5c

0x5e

0x60

0x62

0x01

-

Sampling

Rate Setting

Stereo Gain

-

0

STEGAIN

0x07

0x09

0x0b

0x0d

0x0f

-

0

1

-

0

-

0

IRQPOLE

-

SHLIREN

SHRIREN

THRIREN

IRQ control

IRQ Status

Clock Enable

0

-

0

-

SHLSTS

SHRSTS

THRSTS

-

MCLKOE

0

PLLOE

0

MCLKEN

0

-

PLLEN

-

0

PLLISEL

CLKSEL

-

Clock Input/Output

Control

-

0

-

0

-

0

-

0

SOFTRST

0

0x11

0x13

0x15

0x1d

0x21

0x23

0x25

0x27

0x2b

0x2f

-

Software Reset

-

RECPLAY

0

-

Record/Playback

Running Control

Mic Input Charging

Time

-

0

MCTIME

-

0

-

0

-

0

MAPCON

0

-

RegisterMAP

-

Control

VMIDCON

LOREN

LOLEN

LOSEL

-

MICBEN

Analog Reference Power

Management

0

-

0

-

0

-

PGAEN

ADCREN

ADCLEN

LIEN

Analog Input Power

Management

-

0

-

DACREN

DACLEN

-

DAC Power

-

0

SPABEN

0

-

SPMVEN

0

Management

-

SPDEN

Speaker Amplifier Power

Management

-

0

AMA

TEST2

BP2SPEN MV2SPEN

TEST1

TEST0

AM avoidance Control /

SPAMP input Control

Zero Cross Cmparator

Power Management

BEEPIN Amp Control /

MICBIAS Voltage Control

Line-In Control

0

-

0

1

-

1

-

1

ZCEN

0

1

-

TEST3

1

BPINCON

MICBCON18S

0x31

0x33

0x3b

0x3f

-

MXGAIN

0

LIN2EN

0

LIN1EN

1

LINMXEN MICMXEN

LIN3EN

0

1

0

SPVOL

Speaker Amplifier Volume

Control

1

0

1

PDATT

Playback

1

-

1

-

1

-

1

-

1

AVFADE

0

Digital Attenuator Control

Amplifier Volume Control

Function Enable

Amplifier Volume

Fader Control

0x49

0x4b

0x4d

0x4f

-

AVMUTE

-

0

AVFCON

-

0

WSLO

0

PCMFO24

FMTO

MSBO

ISSCKO

AFOO

DLYO

SAI Transmitter

Control

1

0

DLYI

0

PCMFI24

FMTI

MSBI

ISSCKI

AFOI

WSLI

0

SAI Receiver

1

-

0

-

0

Control

0x51

0x53

0x55

0x59

0x5b

0x5d

0x5f

-

BSWP

-

MST

0

SAI Mode

-

0

-

select

SPMIXG

-

Speaker Amplifier

output Control1

Speaker Amplifier / Lineout Amplifier

output Control2

DAC Clock Setting

-

0

-

LINOE

MICOE

DACOE

LOMIXG

-

0

-

0

-

0

-

OSRSEL

-

0

-

0

-

MINDIF

Mic Interface

Control

-

1

SEMODE

Sound Effect Mode

0

-

0

-

0

I2SR

0

I2SL

0

Record Path

select

RDVOL

0x61

0x63

Record

1

Digital Attenuator Control

Playback

Effect VOL

1

Effect Volume Control

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

34/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

INDEX

b07

b06

b05

b04

b03

b02

b01

b00

Register Name

Note

R

W

0x67

(Initial)

HPF2OD

0x66

0x68

0x6a

0x74

0x76

0x78

0x7a

0x7c

0x7e

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0xa6

0xac

0xae

0xb0

0xb2

EQ4EN

EQ3EN

EQ2EN

EQ1EN

EQ0EN

HPF2EN

HPF1EN

DSP Filter Function

Enable

0

-

0

-

0

-

0

DVMUTE

0

DVFADE

0

-

0

-

1

PALCEN

0

0x69

0x6b

0x75

0x77

0x79

0x7b

0x7d

0x7f

Digital Volume Control

Function Enable

DVFCON

RMCON

LMCON

Mixer & Volume

0

1

0

1

0

1

0

1

0

1

0

1

0

Control

EQGAIN0

EQ Band0

0

Gain Setting

EQGAIN1

EQGAIN2

EQGAIN3

EQGAIN4

EQ Band1

Gain Setting

EQ Band2

Gain Setting

EQ Band3

Gain Setting

EQ Band4

1

-

1

-

1

-

0

-

0

-

1

HPF2CUT

0

Gain Setting

High Pass Filter2

Cut-off Control

EQ0A0L

EQ0A0H

EQ0A1L

EQ0A1H

EQ1A0L

EQ1A0H

EQ1A1L

EQ1A1H

EQ2A0L

EQ2A0H

EQ2A1L

EQ2A1H

EQ3A0L

EQ3A0H

EQ3A1L

EQ3A1H

EQ4A0L

EQ4A0H

EQ4A1L

EQ4A1H

0x81

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

Programable Equalizer Band0

Coefficient-a0 (L)

0

Programable Equalizer Band0

Coefficient-a0 (H)

Programable Equalizer Band0

Coefficient-a1 (L)

Programable Equalizer Band0

Coefficient-a1 (H)

Programable Equalizer Band1

Coefficient-a0 (L)

Programable Equalizer Band1

Coefficient-a0 (H)

Programable Equalizer Band1

Coefficient-a1 (L)

Programable Equalizer Band1

Coefficient-a1 (H)

0x91

0x93

0x95

0x97

0x99

0x9b

0x9d

0x9f

Programable Equalizer Band2

Coefficient-a0 (L)

Programable Equalizer Band2

Coefficient-a0 (H)

Programable Equalizer Band2

Coefficient-a1 (L)

Programable Equalizer Band2

Coefficient-a1 (H)

Programable Equalizer Band3

Coefficient-a0 (L)

Programable Equalizer Band3

Coefficient-a0 (H)

Programable Equalizer Band3

Coefficient-a1 (L)

Programable Equalizer Band3

Coefficient-a1 (H)

0xa1

0xa3

0xa5

0xa7

0xad

0xaf

Programable Equalizer Band4

Coefficient-a0 (L)

Programable Equalizer Band4

Coefficient-a0 (H)

Programable Equalizer Band4

Coefficient-a1 (L)

Programable Equalizer Band4

Coefficient-a1 (H)

0

-

RALCVOL

0

-

1

-

0

-

0

-

0

-

0

RPPL

0

Record ALC Volume Control

RecPlay Play Limitter Enable

-

0xb1

0xb3

-

SCEN

0

Soft Clip Enable

-

SCTHRH

0

Soft Clip Threshold H

0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

35/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

INDEX

b07

(Initial)

b06

b05

b04

b03

b02

b01

b00

Register Name

Soft Clip Threshold M

Soft Clip Threshold L

Soft Clip Gain

Note

R

W

SCTHRM

SCTHRL

0xb4

0xb6

0xb8

0xba

0xbc

0xbe

0xc4

0xc6

0xc8

0xdc

0xde

0xe0

0xe2

0xe4

0xe6

0xea

0xec

0xb5

0

0xb7

0xb9

0xbb

0xbd

0xbf

0

-

0

-

0

-

0

-

0

SCGAIN

-

0

-

0

1

MALCEN

1

-

MCLEN

MIC ALC Control

-

1

MALCATK

0

MALCDCY

0

MIC ALC Attack /Decay Time

MIC ALC Max Gain

1

-

0

1

0

MALCMXGAIN

0

1

-

0

-

0

-

0

LALCEN

0

0xc5

0xc7

0xc9

0xdd

0xdf

-

LCLEN

LINE ALC Control

-

0

LALCATK

0

LALCDCY

LINE ALC Attack /Decay Time

LINE ALC Max Gain

1

-

1

-

1

-

1

0

1

0

1

0

LALCMXGAIN

1

0

1

PALCATK

Playback ALC

Attack Time Control

Playback ALC

note1

0

PALCDCY

Decay Time Control

Playback ALC

PALCLVL

0

0xe1

0xe3

0xe5

0xe7

0xeb

0xed

1

-

1

-

1

Target Level Control

Playback ALC

PALCMINGAIN

0

Min Gain Control

Playback ALC

PALCVOL

0

-

1

-

0

-

0

-

0

Volume Control

Playback ALC ZeroCross

TimeOut

PALCZCTM

-

0

PALCFRTH

PALCFRSP

PALCFREN

0

Playback Limiter

Fast Release Setting

ＨＰＯＵＴ Power Up

Control

0

-

0

-

0

1

0

-

1

-

LOPWTIM

0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

36/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

It is available at the MAPCON=0x1(Register Map Control Register 0x1c/0x1d)

INDEX

b07

(Initial)

b06

b05

b04

b03

b02

b01

b00

Register Name

FPLL M setting

Note

R

W

0x03

0x02

0x04

0x06

0x08

0x0a

0x0c

0x0e

0x10

0x12

0x16

0x1c

0x36

0x3e

0x74

0x76

0x86

0x88

0x8a

0x8c

0x8e

0xa0

0xa2

0xa4

0xa6

0xa8

0xaa

FPLLM

0

-

0

0x05

0x07

0x09

0x0b

0x0d

0x0f

FPLLNL

FPLL N Setting(L)

FPLL N Setting(H)

FPLL D Setting

0

-

0

-

0

-

0

-

0

-

0

-

0

FPLLNH

0

-

FPLLD

0

FPLLFL

FPLLFH

FPLL F Setting(L)

FPLL F Setting(H)

FPLL F_D Setting(L)

FPLL F_D Setting(H)

FPLL V setting

0

FPLLFDL

FPLLFDH

0

0x11

0x13

0x17

0x1d

0x37

0x3f

0

-

0

-

0

-

FPLLV

-

0

-

0

-

0

-

0

-

CPMODE

-

PLL CPMODE Setting

-

0

-

MAPCON

0

-

RegisterMAP

Control

-

HPVOL

-

HP output Gain Setting

0

ADCSET

1

0

1

0

HALF

1

HPBPEN LINDACEN

Analog Path Control

0

1

0

0x75

0x77

0x87

0x89

0x8b

0x8d

0x8f

RBLVOLL

Record L Balance

Volume Control

Record R Balance

Volume Control

Stereo Enhancer

Control

1

0

RBLVOLR

1

-

0

-

0

-

0

-

0

-

0

STEEN

0

STEOD

0

STE1CUT[7:0]

Stereo Enhancer LPF1

CoefL

0

STE1CUT[15:8]

Stereo Enhancer LPF1

CoefH

0

STE2CUT[7:0]

Stereo Enhancer LPF2

CoefL

0

STE2CUT[15:8]

Stereo Enhancer LPF2

CoefH

0

-

0

-

0

-

0

-

0

-

0

-

0

PLPFOD

0

PLPFEN

0

0xa1

0xa3

0xa5

0xa7

0xa9

0xab

Play Programable LPF

Setting

PLPFC0L

PLPFC0H

Play Programable LPF

Coef (L)

0

Play Programable LPF

Coef (H)

0

-

0

-

0

-

0

-

0

-

0

-

0

RLPFOD

0

RLPFEN

0

Rec Programable LPF

Setting

RLPFC0L

RLPFC0H

Rec Programable LPF

Coef (L)

0

Rec Programable LPF

Coef (H)

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

37/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Detailed Description of the Registers

Note: “-” indicates a reserved bit. They return “0” for reads. Write “0” to the bit every time. If “1” is written to this bit, the

operations cannot be guaranteed.

Don't write the registers expect the map of below. If these register is written, the operations cannot be guaranteed.

“*” indicates that the register value is effective immediate without internal clock.

Sampling Rate Setting Register

INDEX

MAPCON

0x0

b07

(Initial)

b06

b05

b04

b03

0

b02

0

b01

0

b00

0

R

W

0x00

0x01

-

SR

This register is to set the sampling rate of recording and playback. Please change this register value at recording and

playback operation stop ($12h/$13h: RECPLAY=0h).

SR [3:0]

0x0

Description

8 kHz

0x1

0x2

11.025 kHz

12 kHz

0x3

16 kHz

0x4

0x5

22.05 kHz

24 kHz

0x6

32 kHz

0x7

0x8

44.1 kHz

48 kHz

Stereo Gain Register

INDEX

MAPCON

0x0

b07

b06

0

b05

1

b04

0

b03

b02

0

b01

0

b00

0

R

W

(Initial)

0x06

0x07

-

STEGAIN

0

This register is to set the amount of effects of stereo emphasis. Please refer to ”StereoEnhancerApplicationNote” for the

details of setting.

STEGAIN[3:0]

STEGAIN Gain[times] STEGAIN Gain[times] STEGAIN Gain[times] STEGAIN Gain[times]

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0.000

0.063

0.125

0.188

0.250

0.313

0.375

0.438

0.500

0.563

0.625

0.688

0.750

0.813

0.875

0.938

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

1.000

1.063

1.125

1.188

1.250

1.313

1.375

1.438

1.500

1.563

1.625

1.688

1.750

1.813

1.875

1.938

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

2.000

2.063

2.125

2.188

2.250

2.313

2.375

2.438

2.500

2.563

2.625

2.688

2.75

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

3.000

3.063

3.125

3.188

3.250

3.313

3.375

3.438

3.50

3.563

3.625

3.688

3.750

3.813

3.875

3.938

2.813

2.875

2.938

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

38/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

IRQ control Register

INDEX

MAPCON

0x0

b07

(Initial)

IRQPOLE(*)

0

b06

b05

b04

b03

b02

b01

b00

R

W

0x08

0x09

-

SHLIREN SHRIREN THRIREN

0

This register controls the interrupt enable or disable.

THRIREN

This bit controls thermal error interrupt.

THRIREN

Description

If thermal error occurs, interrupt is not generated.

If thermal error occurs, interrupt is generated.

0

1

SHRIREN

This bit controls interrupt of left speaker short error.

SHRIREN

Description

0

1

If left speaker short error occurs, interrupt is not generated.

If left speaker short error occurs, interrupt is generated.

SHLIREN

This bit controls interrupt of right speaker short error.

SHLIREN

Description

0

1

If right speaker short error occurs, interrupt is not generated.

If right speaker short error occurs, interrupt is generated.

IRQPOLE

This bit specifies polarity of interrupt pin (IRQB).

IRQPOLE

Description

0

1

If interrupt occur, IRQB pin output L level.

If interrupt occur, IRQB pin output H level.

IRQ Status Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x0a

0x0b

-

SHLSTS SHRSTS THRSTS

0

This register can check the interrupt status. If writing ”1”, state is clearable.

THRSTS

This bit can check thermal error interrupt state.

THRSTS

Description

0

1

No thermal error.

Thermal error occurred.

SHRSTS

This bit can check left speaker short error interrupt status.

SHRSTS

Description

0

1

No left speaker short error.

Left speaker short error occurred.

SHLSTS

This bit can check right speaker short error interrupt status.

SHLSTS

Description

0

1

No right speaker short error.

Right speaker short error occurred.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

39/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Clock Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

MCLKOE(*)

0

MCLKEN(*)

0

0x0c

0x0d

-

PLLOE(*) PLLEN(*)

0

This register controls clock operation.

MCLKEN

This bit is to set the MCLKI pin enable or disable. A clock is not transmitted to an inside in case of the disable.

MCLKEN

Description

MCLKI pin input disabled.

The clock stops at the first input buffer of the MCLKI pin.

MCLKI pin input enabled

0

1

PLLEN

This bit is to set the status of PLL.

PLLEN

Description

0

1

PLL power down

PLL power up

At the first, set PLL Setting registers. After that, set PLLEN bit to “1”.

PLLOE

This bit is to set the status of PLL output. Set this bit to “1” after PLL operation has stabilized. Also, this bit must be set to “1” if

PLL is not used, otherwise internal clock can not be provided.

PLLOE

Description

0

1

PLL output disable

PLL output enable

MCLKOE

This bit is to set the status of output signal from MCLKO pin.

MCLKOE

Description

0

1

Normally Operation

Prohibited

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

40/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Clock Input/Output Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

0

b01

b00

0

R

W

(Initial)

0x0e

0x0f

-

PLLISEL(*)

CLKSEL(*)

0

This register is to select internal clock. It is to use or not use and to create MCLKI input or internal clock divided PLL.

CLKSEL[2:0]

These bits are to select the internal clock.

CLKSEL[2:0]

Description

0x0

Use PLL output clock.(256fs)

Use PLL output clock.(512fs)

PLL output clock is divided by 2 in the LSI.

0x2

0x3

0x4

0x6

0x7

Use PLL output clock.(1024fs)

PLL output clock is divided by 4 in the LSI.

256fs external clock from MCLKI pin input.

MCLKI pin input is directly used in the LSI.

512fs external clock from MCLKI pin input.

MCLK pin input is divided by 2 in the LSI.

1024fs external clock from MCLKI pin input.

MCLK pin input is divided by 4 in the LSI.

PLLISEL[1:0]

This bit is to select the input clock to Audio PLL. If not use PLL, it is to set 0x0.

PLLISEL[1:0]

Description

0x0

0x1

0x2

Use LRCLK input pin

Use MCLKI input pin

Use BCLK input pin

Software Reset Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

SOFTRST(*)

0

0x10

0x11

-

This register is for software reset. CPU interface and this register are reset by writing SOFTRST bit to “1”. And then, write “0”

for releasing reset.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

41/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Record/Playback Running Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x12

0x13

-

RECPLAY

0

This register controls SAI input/output for ADC and DAC.

RECPLAY[2:0]

This bit controls SAI input/output for ADC and DAC. ADC and DAC can be executed at same time. ADC output data can be

directly outputed to DAC path. And about the transition of SAI input/output for ADC and DAC, please refer to Chapter “State

Transition about Sound Control”. It is prohibited the other direct transition. So it is recommended that transition may be

changed via Sound Stop (RECPLAY=0x0).

RECPLAY[2:0]

Description

0x0

SAI input/output for ADC and DAC stop state

ADC enable, SAI output state

0x1

0x2

Analog input (Microphone/Line) is converted from analog to digital, and transferred through

SAI.

DAC enable, SAI input state.

SAI received data is converted from digital to analog and output from analog output path

(Speaker/Headphone Output).

ADC enable, SAI output state and DAC enable, SAI input state.

Analog input (Microphone/Line) is converted from analog to digital, and transferred through

SAI and SAI received data is converted from digital to analog and output from analog

output path (Speaker/Headphone Output).

0x3

0x7

ADC enable, SAI output state and DAC enable state.

Analog input (Microphone/Line) input is converted from analog to digital, and transferred

through SAI and this data is converted from digital to analog and output from analog output

path (Speaker/Headphone Output).

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

42/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Mic Input Charging Time Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

0

b03

b02

MCTIME

b01

0

b00

0

R

W

(Initial)

0x14

0x15

-

0

This register is to select the wait time for microphone input load charge. The LSI work recording signal are mute when from

RECPLAY is changed from 0x0 until MCTIME. This time contains required time of initializing internal circuit that is 40/fs. It

must be waited the setting time to start recording or playback.

In addition the wait time at starting playback is always 40/fs regardless of the setting value of this register.

MCTIME[5:0]

These bits are to set the wait time for Mic input charging time at starting recording. The wait time is available 40/fs and 128/fs

to 8064/fs every 128fs. According to following table, this time is proportional to sampling frequency (fs).

MCTIME[5:0]

fs equivalent

Time(fs=48kHz)

0x00

40/fs

0.8ms

0x01

128/fs

2.7ms

0x02

256/fs

5.3ms

0x03

384/fs

8.0ms

0x04 - 0x3D

0x3E

(128/fs / step)

7936/fs

:

165.3ms

168.0ms

0x3F

8064/fs

Note) the wait time for microphone input load charge

The wait time can be optionally to set with Mic Input Charging Time register. It is a recommended value of MIN1 couppling

capacitor at the charge time.

Charge time

Capacity of

Capacitor

Charge time (minimum)

MCTIME setting time (fs=48kHz)

0.1µF

0.22µF

16ms

36ms

0x09

0x14

* Charge time is proportional to Capacity of Capacitor.

Register MAP Control Register

INDEX

MAPCON

ALL

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

MAPCON(*)

0

0x1c

0x1d

-

MAPCON

The register is to set register map. Please refer register map about the map of the changing object.

MAPCON

Description

0

1

Register MAP0 access enable

Register MAP1 access enable

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

43/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Analog Reference Power Management Register

INDEX

MAPCON

0x0

b07

(Initial)

LOREN

0

b06

b05

b04

b03

b02

b01

b00

0

R

W

0x20

0x21

LOLEN

0

LOSEL

0

-

MICBEN

0

VMIDCON(*)

0

This register controls power up and down of the Headphone Output amplifier and the analog reference voltage generation

circuit.

VMIDCON[1:0]

These bits control power up and down of the VMID generation circuit. Power up time can be reduced by using high speed

power up mode. VMID generation circuit should be changed to normal mode after power up is completed. About the timing of

setting, please refer to the section of ”Analog Reference Voltage (VMID) generation circuit”.

VMIDCON[1:0

Description

0x0

0x1

0x2

VMID generation circuit power down

VMID generation circuit power up high speed power up mode

VMID generation circuit power up normal mode

MICBEN

This bit controls power up and down of the MICBIAS generation circuit.

MICBEN

Description

MICBIAS generation circuit power down

MICBIAS generation circuit power up

0

1

LOSEL

This bit specify input path to Headphone Output amplifier. It is available DAC output or SPVOL output.

LOSEL

Description

0

1

DAC output is directly outputted from HPOUT.

DAC output is outputted from HPOUT through SPVOL block.

LOLEN

This bit controls HPOUT left output enable or disable.

LOLEN

Description

0

1

HPOUT left output disabled

HPOUT left output enabled

LOREN

This bit controls HPOUT right output enable or disable.

LOREN

Description

0

1

HPOUT right output disabled

HPOUT right output enabled

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

44/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Analog Input Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x22

0x23

-

PGAEN(*) ADCREN ADCLEN

LIEN

0

This register controls power up and down of the input part of the analog circuit.

LIEN

This bit controls power up and down of the Line input amplifier.

LIEN

0

1

Description

Line input amplifier power down

Line input amplifier power up

This LSI charge the couppling capacitor of LIN pins, when LIEN bit is changed from 0 to 1. This period’s time is counted by

master clock which is between about 97ms and about 142ms. In this period, the output path of LINVOL amplifier is open, so

input signal is muted for next part amplifier. It does n’t depend on LIN1EN,LIN2EN,LIN3EN,LINMXEN and MICMXEN

registers.

*Pleas set this register to “1” at MIC recording.

ADCLEN

This bit controls power up and down of the ADC left.

ADCLEN

Description

0

1

ADC left power down

ADC left power up

ADCREN

This bit controls power up and down of the ADC right.

ADCREN

Description

0

1

ADC right power down

ADC right power up

PGAEN

This bit controls power up and down of the MIC input amplifier.

PGAEN

Description

Mic input amplifier power down

Mic input amplifier power up

0

1

DAC Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x24

0x25

-

DACREN DACLEN

-

0

This register controls power up and down of the DAC

DACLEN

This bit controls power ON and OFF of the DAC left

DACLEN

Description

0

1

DAC left power down

DAC left power up

DACREN

This bit controls power ON and OFF of the DAC right

DACREN

Description

0

1

DAC right power down

DAC right power up

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

45/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Speaker Amplifier Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x26

0x27

-

SPDEN

0

SPABEN SPMVEN

0

This register controls power up and down of the speaker amplifier and volume amplifier.

SPMVEN

This bit controls power up and down of the MIXVOL (MIXER and SPVOL volume) block.

SPMVEN

Description

MIXVOL block power down

MIXVOL block power up

0

1

SPABEN

This bit controls power up and down of the Class-AB speaker amplifier.

SPABEN

Description

Class-AB speaker amplifier power down

Class-AB speaker amplifier power up

0

1

SPDEN

This bit controls power up and down of the Class-D speaker amplifier.

SPDEN

Description

Class-D speaker amplifier power down

0

1

*If SPABEN and SPDEN are set to 1 at once, SPABEN is effective.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

46/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

AM avoidance Control / SPAMP input Control Register

INDEX

MAPCON

0x0

b07

(Initial)

TEST2

0

b06

b05

b04

b03

b02

b01

1

b00

1

R

W

0x2a

0x2b

-

BP2SPEN MV2SPEN

TEST1

1

TEST0

1

AMA

0

1

This register controls input path of speaker amplifier, select operation frequency of Class-D speaker amplifier, and for

shipment test.

AMA

This bits control operation frequency of Class-D speaker amplifier by AM avoidance function.

AMA[1:0]

Description

0x0

0x1

0x2

0x3

700kHz

600kHz

500kHz

400kHz

TEST0

This bit is for shipment test. Don’t change from initial value.

TEST0

Description

1

Test register. Use by 1

TEST1

This bit is for shipment test. Don’t change from initial value.

TEST1

Description

1

Test register. Use by 1

MV2SPEN

This bit controls the input signal of speaker amplifier from mixer volume.

MV2SPEN

Description

0

1

Don’t input the signal from mixer volume to speaker amplifier.

Input the signal from mixer volume to speaker amplifier.

BP2SPEN

This bit controls the input signal of speaker amplifier from mixer volume.

BP2SPEN

Description

0

1

Don’t input the signal from BEEPIN amplifier to speaker amplifier.

Input the signal from BEEPIN amplifier to speaker amplifier.

TEST2

This bit is for shipment test. Don’t change from initial value.

TEST2

Description

0

Test register. Use by 0.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

47/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Zero Cross Comparator Power Management Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x2e

0x2f

-

ZCEN

0

-

This register is to set ON and OFF of zerocross function about refreshing PLAYVOL setting by PALC controller.

ZCEN

The zero cross is applied to refreshing PLAYVOL settings when zero cross detection operation is effective.

ZCEN

Description

0

Zerocross detection operation is invalid.

The gain setting of PLAYVOL is immediately reflected when the settings are changed.

1

Zerocross detection operation is effective.

The gain setting of PLAYVOL is reflected after zerocross detection.

BEEPIN Amp Control / MICBIAS Voltage Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x30

0x31

-

BPINCON

TEST3

1

MICBCON18S

0

This register controls voltage value of microphone bias, and controls BEEPIN amplifier and for shipment test.

MICBCON18S[1:0]

These bits are to set the MICBIAS. Set the MICBIAS voltage less than HVDD x 0.85.

MICBCON18S

Output Voltage (the case of REGOUT =1.8V)

0x0

0x1

0x2

0x3

1.50V

2.00V

2.50V

3.00V

TEST3

This bit is for shipment test. Don’t change from initial value.

TEST3

Description

1

Test register. Use by 1

BPINCON[1:0]

These bits

BPINCON

Output Voltage (the case of REGOUT =1.8V)

0x0

0x1

0x2

0x3

BEEPIN amplifier power down

Prohibited

BEEPIN amplifier power up at normal mode

BEEPIN amplifier power up at high speed power up mode

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

48/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Line-In Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x32

0x33

-

MXGAIN LINMXEN MICMXEN LIN3EN

LIN2EN

0

LIN1EN

1

0

1

0

This register controls the operation of Line input amplifier path and Mixer (LineMix)

LIN1EN

Description

Line input amplifier LIN1 path is OFF

Line input amplifier LIN1 path is ON

0

1

LIN2EN

Description

Line input amplifier LIN2 path is OFF

Line input amplifier LIN2 path is ON

0

1

LIN3EN

Description

Line input amplifier LIN3 path is OFF

Line input amplifier LIN3 path is ON

0

1

MICMXEN

Description

Mixing of MIC path in LineMix is OFF

Mixing of MIC path in LineMix is ON

0

1

LINMXEN

Description

Mixing of LIN path in LineMix is OFF

Mixing of LIN path in LineMix is ON

0

1

MXGAIN

Description

Mixing Gain in LineMix is 0dB

Mixing g Gain in LineMix is -6dB

0

1

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

49/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Speaker Amplifier Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

1

b03

0

b02

0

b01

1

b00

1

R

W

(Initial)

0x3a

0x3b

-

SPVOL

This register is to set the Mixvol volume Gain.

SPVOL[5:0]

Gain[dB)

MEMO

↓0.5dB

step

Value

0x1F

Gain[dB]

-14.0

MEMO

0x3F

6.0

0x3E

0x3D

0x3C

0x3B

0x3A

0x39

0x38

0x37

0x36

0x35

0x34

0x33

0x32

0x31

0x30

0x2F

0x2E

0x2D

0x2C

0x2B

0x2A

0x29

0x28

0x27

0x26

0x25

0x24

0x23

0x22

0x21

0x20

5.5

5.0

0x1E

0x1D

0x1C

0x1B

0x1A

0x19

0x18

0x17

0x16

0x15

0x14

0x13

0x12

0x11

0x10

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

-15.0

-16.0

-17.0

-18.0

-19.0

-20.0

-21.0

-22.0

-23.0

-24.0

-25.0

-26.0

-27.0

-28.0

-29.0

-30.0

-31.0

-32.0

-34.0

-36.0

-38.0

-40.0

-42.0

-44.0

-46.0

-48.0

-50.0

-52.0

-54.0

-56.0

MUTE

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

-5.5

-6.0

-7.0

-8.0

-9.0

-10.0

-11.0

-12.0

-13.0

↓2dB step

↓1dB step

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

50/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback Digital Attenuator Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

1

b03

1

b02

1

b01

1

b00

1

R

W

(Initial)

0x3e

0x3f

PDATT

1

This register is to set the digital VolumeGain on DAC path.

It is available MUTE and -71.5dB to 0.5dB every 0.5dB.

PDATT[7:0]

These bits are to set PLAYDATT : digital VolumeGain.

PDATT[7:0]

Gain[dB]

Prohibited

Value

Gain[dB]

Value

Gain[dB]

-35.5

Value

Gain[dB]

0x00 to

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x93

-54.0

0xB8

0xDD

-17.0

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

Prohibited

0x90

-55.5

0xB5

-37.0

0xDA

-18.5

0xFF

0x91

0x92

-55.0

-54.5

0xB6

0xB7

-36.5

-36.0

0xDB

0xDC

-18.0

-17.5

*Set 0xFF is prohibited. It has possibilities that DAC output waveform has distorted.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

51/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Amplifier Volume Control Function Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x48

0x49

-

AVMUTE AVFADE

0

This register is to set the Mixvol volume fade function and mute function.

AVFADE

This bit is to set the ON and OFF of the Mixvol volume fade function.

AVFADE

Description

Fade function OFF

0

The register setting value of SPVOL is used actual volume value as it is. Therefore the

value is effective immediate.

Fade function ON

1

The volume is changing to the register setting value of SPVOL with 1 step per

AVFCON register step time.

AVMUTE

This bit is to set the volume to the mute state. The fade function by AVFADE is effective against the volume change by this bit.

And MixVol Volume value by SPVOL is held and return to setting Volume on release AVMUTE

Value

Description

MixVol volume is set to MUTE OFF.

Register value of SPVOL is effective for MixVol volume.

MixVol volume is set to MUTE.

0

1

Register value of SPVOL cannot be changed by this bit, the volume is resumed by

releasing this bit (AVMUTE=0) to the original setting value of SPVOL.

* Related Register

SPVOL: MixVolVolume Control Register (0x3a/0x3b)

AVFCON: MixVol Volume Fader Control Register (0x4a/0x4b)

Amplifier Volume Fader Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x4a

0x4b

-

AVFCON

0

This register controls the MixVol volume fade function.

AVFCON[2:0]

These bits are to set the volume change step time of the MixVol volume fade function. The volume changes step by step with

this setting period. Step time is in proportion to sampling frequency (fs) as following table.

AVFCON[2:0]

fs equivalent

Time(fs=48kHz)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

1/fs

4/fs

16/fs

20.8µs

83.3µs

333µs

1.33ms

5.33ms

21.3ms

85.3ms

341.ms

64/fs

256/fs

1024/fs

4096/fs

16384/fs

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

52/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

SAI Transmitter Control Register

INDEX

MAPCON

0x0

b07

b06

1

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x4c

0x4d

PCMFO24

FMTO

0

MSBO

0

ISSCKO

0

AFOO

0

DLYO

0

WSLO

0

1

This register controls the SAI transmit format setting. This register setting must not be changed during SAI operation. Set this

register as same as SAI Receiver Control Register.

WSLO

This bit specifies the LRCLK polarity at this LSI’s transmission. This bit must be set at “1” when the Flame synchronous

transfer mode (FMTO is “1”).

WSLO

Description

Left channel transmission at LRCLK is “L” level; right channel transmission at

LRCLK is “H” level.

Left channel transmission at LRCLK is “H” level; right channel transmission at

LRCLK is “L” level.

0

1

DLYO

This bit specifies the existence for serial output data one clock delay of master device.

DLYO Description

0

1

Serial data delay exists

No serial data delay

AFOO

This bit specifies left-justify or right-justify. In case of the slave mode, this bit is ignored and fixed at left-justify. This bit must

be set at “0” when the Flame synchronous transfer mode (FMTO is “1”).

AFOO

Description

0

1

Left-justify

Right-justify

ISSCKO

This bit specifies 32fs or 64fs.

ISSCKO

Description

0

1

32fs

64fs

MSBO

This bit specifies MSB-first or LSB-first of the SAI transmission data.

MSBO

Description

0

1

MSB-first

LSB-first

FMTO

This bit specifies transmission mode.

FMTO

Description

0

1

SAI_LRCLK transfer mode

Flame synchronous transfer mode

PCMFO24

This bit specifies PCM format of SAI transmission data.

PCMFO24

Description

0x2

0x3

Other

16bit PCM

24bit PCM

Prohibited

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

53/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

SAI Receiver Control Register

INDEX

MAPCON

0x0

b07

b06

1

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x4e

0x4f

PCMFI24

FMTI

0

MSBI

0

ISSCKI

0

AFOI

0

DLYI

0

WSLI

0

1

This register controls the setting for the SAI receive format. Do not change this register during operation of the SAI. Set this

register as same as SAI Transmitter Control Register.

WSLI

This bit is to select LRCLK polarity of this LSI. This bit must be set at “1” when the Flame synchronous transfer mode (FMTI

is “1”).

WSLI

Description

LEFT channel is received when LRCLK is “L” level, right channel is

received at LRCLK is “H” level.

0

LEFT channel is received when LRCLK is “H” level, right channel is

received at LRCLK is “L” level.

1

DLYI

This bit specifies the existence for serial input data one clock delay of master device.

DLYI

Description

0

1

Serial data delay exists

No serial data delay

AFOI

This bit specifies the receiving data of Left-justify or Right-justify. This bit must be set at “0” when the Flame synchronous

transfer mode (FMTI is “1”).

AFOI

Description

0

1

Left-justify

Right-justify

ISSCKI

This bit specifies the sampling frequency of SAI_BCLK pin.

ISSCKI

Description

0

1

32fs

64fs

MSBI

This bit specifies the SAI receiving data of MSB-first or LSB-first.

Value

0

1

Description

MSB-first

LSB-first

FMTI

This bit specifies the receiving mode

FMTI

0

1

LRCLK transfer mode

Flame synchronous transfer mode

PCMFI24

This bit specifies the PCM format of SAI receiving.

Value

Description

0x2

0x3

other

16bit PCM

24bit PCM

Prohibited

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

54/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

SAI Mode select Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x50

0x51

-

BSWP

0

-

MST(*)

0

This register is to set master mode or slave mode of the SAI. Do not change this register during SAI operation.

MST

This bit use by 0.

MST

Description

0

Slave mode

BSWP

This bit is selected of the SAI output data format.

Description

SAI output data format

0

1

(16bit Audio Data:15bit-8bit,7bit-0bit)

(24bit Audio Data:23bit-16bit,15bit-8bit,7bit-0bit)

SAI output data format

(16bit Audio Data:7bit-0bit,15bit-8bit)

(24bit Audio Data:7bit-0bit,15bit-8bit 23bit-16bit)

Speaker Amplifier output Control1 Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

0

b00

0

R

W

(Initial)

0x52

0x53

-

SPMIXG

This register sets the gain of the speaker amplifier.

SPMIXG[1:0]

This bits sets the gain of the speaker amplifier.

SPMIXG

Description

0

1

2

3

0dB

6dB

12dB

18dB

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

55/92

Daattaasshheeeett

BU26156RFS

Speaker Amplifier / Lineout Amplifier output Control2 Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x54

0x55

-

LINOE

0

MICOE

0

DACOE

0

LOMIXG

0

This register sets the input signal path to a MixVol part mixer

LOMXG

This sets a mixing gain of the DAC output and the MIC output.

The Line-input is 0dB fix.

LOMXG

Description

The amplitude of a DAC output and the MIC output is added to

MIXVOL in 0dB.

0

The amplitude of a DAC output and the MIC output is added to

MIXVOL in -6dB.

1

DACOE

Description

0

1

The connection of DAC and MIXVOL is disable

The connection of DAC and MIXVOL is enable

MICOE

Description

0

1

The connection of MIC-input and MIXVOL is disable

The connection of MIC-input and MIXVOL is enable

LINOE

Description

0

1

The connection of Line-input and MIXVOL is disable

The connection of Line-input and MIXVOL is enable

DAC Clock Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

0

b03

b02

b01

b00

R

W

(Initial)

0x58

0x59

-

OSRSEL

-

0

This register performs clock setting to use in DAC

OSRSEL[1:0]

Sampling Frequency

16kHz 32kHz

11.025kHz 22.05kHz

PLL use

or nonuse

CLKSEL

8kHz

44.1kHz

48kHz

12kHz

24kHz

Prohibited

0x10

Prohibited

0x10

PLL use

0x0

0x2

0x3

0x4

0x6

0x7

Prohibited

0xe0

Prohibited

0xa0

0x00

Prohibited

0x00

PLL not use

(MCLKI input)

0x10

0x00

0xe0

0x10

0x00

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

56/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Mic Interface Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x5a

0x5b

-

MINDIF(*)

1

-

This register controls microphone input interface.

MINDIF

Description

0

1

Use analog microphone as single-ended input.

Use analog microphone as differential input.

Sound Effect Mode Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x5c

0x5d SEMODE

0

-

SEMODE

0

This register sets the filter block

SEMODE[7]

BU26156 can use the filter block in ADC path or DAC path.Filter Block can set on only ADC path or DAC path.

Please refer “Single flow section on Function Description about Filter Block.

SEMODE[7]

Description

use Filter Block in Recording

use Filter Block in Playback

0

1

SEMODE[2:0]

This chooses the number of the Filter bands

SEMODE[2:0]

Description

0x0

0x1

0x2

0x3

0x4

0x5

Notch5 band

Notch4 band

Notch3 band

Notch2 band

Notch1 band

Notch0 band

/ EQ0 band

/ EQ1 band

/ EQ2 band

/ EQ3 band

/ EQ4 band

/ EQ5 band

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

57/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Record Path select Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

MONOREC

0

0x5e

0x5f

-

I2SR

0

I2SL

0

This register is to control recording path.

In case of changing this register setting, you must stop this LSI by RECPLAY bit in Record/Playback Running Control

A setup of I2SL=1 and I2SR=1 is prohibition.

Register.

I2SL

This bit is to select the path to Left channel of SAI transmit data.

I2SL

Description

0

1

SAI left channel data is from left channel analog microphone input.

SAI left channel data is from right channel analog microphone input.

I2SR

This bit is to select the path to Right channel of SAI transmit data.

Description

I2SR

0

1

SAI right channel data is from right channel analog microphone input.

SAI right channel data is from left channel analog microphone input.

I2SL

ADC

Lch

From left channel

microphone input

1

To SAI left channel

To SAI right channel

0

ADC

Rch

From right channel

microphone input

1

I2SR

Figure 37

MONOREC

This bit chooses whether ADC output data connects in stereo, or it changes and connects in monaural.

MONOREC Description

ADC output data connects in stereo

0

1

Lch Output is Lch-ADC data

Rch Output is Rch-ADC data

ADC output data changes and connects in monaural.

Lch Output is ( Lch-ADC data + Rch-ADC data ) / 2

Rch Output is ( Lch-ADC data + Rch-ADC data ) / 2

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

58/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Record Digital Attenuator Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

1

b03

1

b02

1

b01

1

b00

1

R

W

(Initial)

0x60

0x61

RDVOL

1

This register is to set the digital volume of the recording path.

Their values are 0.5dB step from -71.5dB to 0.0dB, and mute.

RDVOL[7:0]

RDVOL

Gain(dB)

RDVOL

0x93

Gain(dB)

-54.0

RDVOL

0xB8

Gain(dB)

-35.5

RDVOL

0xDD

Gain(dB)

0x00 to

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

Write

prohibit

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

-17.0

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

-18.5

-18.0

-17.5

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

59/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback Effect Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

1

b04

b03

1

b02

1

b01

1

b00

1

R

W

(Initial)

0x62

0x63

Effect VOL

1

This register is to set the digital volume of the playback path.

Their values are 0.5dB step from -71.5dB to 0.0dB, and mute.

Effect Vol[7:0]

Effect Vol

Gain(dB)

Effect Vol

0x93

Gain(dB)

-54.0

Effect Vol

0xB8

Gain(dB)

-35.5

Effect Vol

0xDD

Gain(dB)

0x00 to

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

Write

prohibit

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

-17.0

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

-18.5

-18.0

-17.5

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

-9.0

-8.5

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

60/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

DSP Filter Function Enable Register

INDEX

MAPCON

0x0

b07

(Initial)

HPF2OD

0

b06

b05

b04

b03

b02

b01

b00

R

W

0x66

0x67

EQ4EN

0

EQ3EN

0

EQ2EN

0

EQ1EN

0

EQ0EN

0

HPF2EN HPF1EN

0

1

This register is to set ON or OFF for DSP filtering function.

HPF1EN

This bit is to set ON or OFF of a first-order high pass filter for DC cut. Do not change this bit during operation of the recording

(0x13/0x14: RECPLAY=0x1, 0x3, or 0x7). If this bit is changed, the noise may be generated.

HPF1EN

Description

DC cut first-order high pass filter OFF

DC cut first-order high pass filter ON

0

1

HPF2EN

This bit is to set ON or OFF of a second-order high pass filter for noise cut. ($13h/$14h: RECPLAY=1 or 2). If this bit is

changed, the noise may be generated.

HPF2EN

Description

0

1

Noise cut second-order high pass filter OFF

Noise cut second-order high pass filter ON

EQ0EN

This bit is to set ON or OFF of equalizer band 0. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ0EN

Description

equalizer band 0 disable

equalizer band 0 enable

0

1

EQ1EN

This bit is to set ON or OFF of equalizer band 1. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ1EN

Description

equalizer band 1 disable

equalizer band 1 enable

0

1

EQ2EN

This bit is to set ON or OFF of equalizer band 2. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ2EN

Description

equalizer band 2 disable

equalizer band 2 enable

0

1

EQ3EN

This bit is to set ON or OFF of equalizer band 3. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ3EN

Description

equalizer band 3 disable

equalizer band 3 enable

0

1

EQ4EN

This bit is to set ON or OFF of equalizer band 4. In case of changing this bit during recording and playback operation

(0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then

change the gain to 0dB.

EQ4EN

Description

equalizer band 4 disable

equalizer band 4 enable

0

1

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

61/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

HPF2OD

This bit is to set number of high pass filter order(HPF2EN bit) for noise cut. In recording or

playback operation(RECPLAY≠0x0 ), do not change this bit. If this bit is changed, the noise may be generated.

HPF2OD

Description

second-order high pass filter

first-order high pass filter

0

1

Digital Volume Control Function Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x68

0x69

-

DVMUTE DVFADE

-

PALCEN

0

This register is to set ON or OFF for digital volume control function.

PALCEN

This bit is to set ON or OFF of limiter at playback.

Set this register at stop state. (RECPLAY=0x0)

Set PALCEN register’ value same as RPPL register (0xae/0xaf)

setting

Description

0

1

PALC OFF at playback

PALC ON at playback

DVFADE

This bit is to set ON or OFF of digital volume fade function. The fade function is effective for the recording and playback

digital volume and the equalizer gain.

setting

Description

Fade function OFF: The register setting value of RDATT, PDATT and EQGAIN0

to 3 is used actual volume value as it is. Therefore the value is effective

immediate.

0

Fade function ON: The volume is changing to the register setting value of

RDATT, PDATT and EQGAIN0 to 3 with 1 step per DVFCON register step time.

1

DVMUTE

This bit is to set MUTE of the digital volume. This mute function is effective for the recording digital volume at recording and

effective for playback digital volume at playback. The fade function by DVFADE is effective against the volume change by

this bit.

setting

Description

0

Register value of RDVOL and PDATT is effective.

Digital volume is set to MUTE.

Register value of RDVOL and PDATT cannot be changed by this bit, the

volume is resumed by releasing this bit(DVMUTE=0) to the original setting

value of RDVOL and PDVOL.

1

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

62/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Mixer & Volume Control Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

0

b03

0

b02

0

b01

0

b00

0

R

W

(Initial)

0x6a

0x6b

DVFCON

RMCON

LMCON

0

This register is to control the SAI receive data L channel plus R channel mixer and the digital volume fade control.

LMCON[1:0]

These bits are to control the SAI receive data L channel plus R channel mixer

LMCON

Description

0x0

0x1

0x2

Use L Discard R

Use R Discard L

Use (L+R)

0x3

Use (L+R)/2

RMCON[1:0]

These bits are to control the SAI receive data R channel plus L channel mixer

RMCON

Description

0x0

Use R Discard L

0x1

0x2

0x3

Use L Discard R

Use (L+R)

Use (L+R)/2

DVFCON[3:0]

These bits are to set the volume change step time of the digital volume fade function. The volume changes step by step

(0.5dB) with this setting period. Step time is in proportion to sampling frequency (fs) as following table.

DVFCON

fs equivalent

Time(fs=48kHz)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

1/fs

2/fs

4/fs

8/fs

16/fs

20.8µs

41.7µs

83.3µs

167µs

333µs

667µs

1.33ms

2.67ms

5.33ms

10.7ms

21.3ms

42.7ms

85.3ms

171ms

341ms

32/fs

64/fs

128/fs

256/fs

512/fs

1024/fs

2048/fs

4096/fs

8192/fs

16384/fs

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

63/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

EQ Band0 Gain Setting Register

EQ Band1 Gain Setting Register

EQ Band2 Gain Setting Register

EQ Band3 Gain Setting Register

EQ Band4 Gain Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0x74

0x76

0x78

0x7a

0x7c

0x75

EQGAIN0

1

0

1

EQGAIN1

0x0

0x77

0x79

0x7b

0x7d

0

EQGAIN2

EQGAIN3

EQGAIN4

0x0

These registers are to set the gain of each band equalizer.

(*)Index values are different by setting sound effect mode register. See Sound Effect Mode register description.

EQGAIN

0 to 4[7:0]

Gain

(0dB)

EQGAIN

0 to 4[7:0]

Gain

(0dB)

EQGAIN

0 to 4[7:0]

Gain

(dB)

EQGAIN

0 to 4[7:0]

Gain

(dB)

0x00 to 0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

MUTE

-71.5

-71.0

-70.5

-70.0

-69.5

-69.0

-68.5

-68.0

-67.5

-67.0

-66.5

-66.0

-65.5

-65.0

-64.5

-64.0

-63.5

-63.0

-62.5

-62.0

-61.5

-61.0

-60.5

-60.0

-59.5

-59.0

-58.5

-58.0

-57.5

-57.0

-56.5

-56.0

-55.5

-55.0

-54.5

-54.0

-53.5

-53.0

-52.5

-52.0

-51.5

-51.0

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

-50.5

-50.0

-49.5

-49.0

-48.5

-48.0

-47.5

-47.0

-46.5

-46.0

-45.5

-45.0

-44.5

-44.0

-43.5

-43.0

-42.5

-42.0

-41.5

-41.0

-40.5

-40.0

-39.5

-39.0

-38.5

-38.0

-37.5

-37.0

-36.5

-36.0

-35.5

-35.0

-34.5

-34.0

-33.5

-33.0

-32.5

-32.0

-31.5

-31.0

-30.5

-30.0

-29.5

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

-29.0

-28.5

-28.0

-27.5

-27.0

-26.5

-26.0

-25.5

-25.0

-24.5

-24.0

-23.5

-23.0

-22.5

-22.0

-21.5

-21.0

-20.5

-20.0

-19.5

-19.0

-18.5

-18.0

-17.5

-17.0

-16.5

-16.0

-15.5

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

-10.0

-9.5

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA

0xFB

0xFC

0xFD

0xFE

0xFF

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

-9.0

-8.5

-8.0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

64/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

High Pass Filter2 Cut-off Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x7e

0x7f

-

HPF2CUT

0

HPF2CUT[2:0]

This register is to set the cut off frequency of the high pass filter for noise reduction. Do not change this register setting at

filtering operation.

These bits are to set the cut-off frequency of noise reduction high pass filter.

The following table shows that the frequency decreases 3dB at second order filter selected (HPF2OD=0)

and decreases 1.5dB at first order filter selected (HPF2OD=1).

Cut-off Frequency(Hz)

fs=8kHz,

16kHz,

32kHz

fs=11.025kHz,

22.05kHz,

44.1kHz

fs=12kHz,

24kHz,

48kHz

setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

80

110

138

179

221

276

358

441

551

120

150

195

240

300

390

480

600

100

130

160

200

260

320

400

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

65/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Programable Equalizer Band0 Coefficient-a0 (L) Register

Programable Equalizer Band0 Coefficient-a0 (H) Register

Programable Equalizer Band0 Coefficient-a1 (L) Register

Programable Equalizer Band0 Coefficient-a1 (H) Register

Programable Equalizer Band1 Coefficient-a0 (L) Register

Programable Equalizer Band1 Coefficient-a0 (H) Register

Programable Equalizer Band1 Coefficient-a1 (L) Register

Programable Equalizer Band1 Coefficient-a1 (H) Register

Programable Equalizer Band2 Coefficient-a0 (L) Register

Programable Equalizer Band2 Coefficient-a0 (H) Register

Programable Equalizer Band2 Coefficient-a1 (L) Register

Programable Equalizer Band2 Coefficient-a1 (H) Register

Programable Equalizer Band3 Coefficient-a0 (L) Register

Programable Equalizer Band3 Coefficient-a0 (H) Register

Programable Equalizer Band3 Coefficient-a1 (L) Register

Programable Equalizer Band3 Coefficient-a1 (H) Register

Programable Equalizer Band4 Coefficient-a0 (L) Register

Programable Equalizer Band4 Coefficient-a0 (H) Register

Programable Equalizer Band4 Coefficient-a1 (L) Register

Programable Equalizer Band4 Coefficient-a1 (H) Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

0

b03

0

b02

b01

b00

R

W

(Initial)

0x80

0x82

0x84

0x86

0x88

0x8a

0x8c

0x8e

0x90

0x92

0x94

0x96

0x98

0x9a

0x9c

0x9e

0xa0

0xa2

0xa4

0xa6

0x81

EQ0A0L

0

EQ0A0H

EQ0A1L

EQ0A1H

EQ1A0L

EQ1A0H

EQ1A1L

EQ1A1H

EQ2A0L

EQ2A0H

EQ2A1L

EQ2A1H

EQ3A0L

EQ3A0H

EQ3A1L

EQ3A1H

EQ4A0L

EQ4A0H

EQ4A1L

EQ4A1H

0x83

0x85

0x87

0x89

0x8b

0x8d

0x8f

0

0x91

0x93

0x95

0x97

0x99

0x9b

0x9d

0x9f

0xa1

0xa3

0xa5

0xa7

These registers are to set the coefficients a0 and a1 of each five band programmable equalizer. One coefficients value is

specified by two bytes data. The centre frequency and band width of the filter can be set by changing these register value.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

66/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Please do not change the register setting during corresponding filter operation (*).The detailed setting value is described in

the Filter function.

(*) (RECPLAY is not 0x0) and (EQ0EN=1 or EQ1EN=1 or EQ2EN=1 or EQ3EN=1)

RecPlay Play Limitter Enable Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xae

0xaf

-

RPPL

0

RPPL

This bit is to set ON or OFF of limiter at playback.

Set this register at stop state. (RECPLAY=0x0)

Set RPPL register’ value same as PLACEN register (0x68/0x69)

setting

Description

0

1

PALC OFF at playback

PALC ON at playback

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

67/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Soft Clip Enable Register

Soft Clip Threshold H Register

Soft Clip Threshold M Register

Soft Clip Threshold L Register

Soft Clip Gain Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xb0

0xb2

0xb4

0xb6

0xb8

0xb1

-

SCEN

0

-

SCTHRH

0

0x0

0xb3

0xb5

0xb7

0xb9

0

1

SCTHRM

0x0

0

SCTHRL

0x0

0

-

0

-

0

-

0

-

0

-

0

SCGAIN

0

0x0

-

This register is setting of the "SoftClip" block.

SCEN

setting

Description

0

1

SoftClip Function OFF

SoftClip Function ON

SCTHRH

SCTHRM

SCTHRL

This register sets a soft clip threshold level.

When PCM signal with more than of this bit is input, the LSI clips it according to a value of SCGAIN and works.

The value of threshold level is 23bit(SCTHRM[6:0], SCTHRM[7:0], SCTHRL[7:0])

Please do not change the value of this bit during SoftClip function movement.

SCGAIN[2:0]

This register is setting the gain at SoftClip. This register setting must not be changed during SoftClip function is active.

setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Description

2 time

1 time(default)

1/2 time

1/4 time

1/8 time

1/16 time

1/32 time

1/64 time

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

68/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

MIC ALC Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xba

0xbb

-

MCLEN

1

MALCEN

1

This register sets the ALC for MIC input

Please refer to function explanation for the details of this function

MALCEN

This sets the MIC ALC.

In the case of OFF, MIC ALC suffers from Gain of MICAMP with a value of MALCMXGAIN

setting

Description

0

1

MALC Function OFF

MALC Function ON (default)

MCLEN

This sets the MIC Clip reduction.

setting

Description

0

MIC Clip reduction OFF

1

MIC Clip reduction ON (default)

MIC ALC Attack /Decay Time Register

INDEX

MAPCON

0x0

b07

b06

1

b05

b04

b03

b02

1

b01

b00

0

R

W

(Initial)

0xbc

0xbd

-

MALCDCY

0

-

MALCATK

0

This register sets Decay Time in Attack Time of the MIC ALC.

MALCATK[2:0]

MIC ALC Attack Time

setting

8kHz

11.025k

12kHz

16kHz

22.05kH

z

24kHz

32kHz

44.1kHz

48kHz

Unit

Hz

0

1

2

3

4

5

6

7

0.25

0.5

1.0

2.0

4.0

8.0

16.0

32.0

0.18

0.36

0.73

1.45

2.9

5.8

11.61

23.22

0.17

0.33

0.67

1.33

2.67

5.33

10.67

21.33

0.13

0.25

0.5

1.0

2.0

4.0

8.0

16.0

0.09

0.18

0.36

0.73

1.45

2.9

0.08

0.17

0.33

0.67

1.33

2.67

5.33

10.67

0.06

0.13

0.25

0.5

1.0

2.0

0.05

0.09

0.18

0.36

0.73

1.45

2.9

0.04

0.08

0.17

0.33

0.67

1.33

2.67

5.33

ms

5.8

11.61

4.0

8.0

5.8

MALCDCY[2:0]

MIC ALC Decay Time

setting

8kHz

11.025k

Hz

12kHz

16kHz

22.05kH

z

24kHz

32kHz

44.1kHz

48kHz

Unit

0

1

2

3

4

5

6

7

64

128

256

512

1024

2048

4096

8192

46

93

43

85

32

64

23

46

93

186

372

743

1486

2972

21

43

85

171

341

683

1365

2731

16

32

64

128

256

512

1024

2048

12

23

46

11

21

43

ms

186

372

743

1486

2972

5944

171

341

683

1365

2731

5461

128

256

512

1024

2048

4096

93

85

186

372

743

1486

171

341

683

1365

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

69/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

MIC ALC Max Gain Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

1

b03

b02

b01

0

b00

0

R

W

(Initial)

0xbe

0xbf

-

MALCMXGAIN

0

This register sets the ALC MAX GAIN for MIC input

MALCGAIN[5:0]

MIC ALC Max Gain.

setting

0x3F

Description

35.25dB

0x3E

:

0x28

:

0x11

0x10

:

34.50dB

(0.75dB/step)

18.00dB

(0.75dB/step)

0.75dB

0.00dB

Prohibited

0x00

LINE ALC Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xc4

0xc5

-

LCLEN

0

LALCEN

0

This register sets the ALC for Line input

Please refer to function explanation for the details of this function

LALCEN

This sets the Line ALC.

setting

Description

0

1

LALC Function OFF (default)

LALC Function ON

LCLEN

This sets the Line Clip reduction.

setting

0

1

Line Clip reduction OFF (default)

Line Clip reduction ON

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

70/92

Daattaasshheeeett

BU26156RFS

LINE ALC Attack /Decay Time Register

INDEX

MAPCON

0x0

b07

b06

1

b05

b04

1

b03

b02

1

b01

b00

0

R

W

(Initial)

0xc6

0xc7

-

LALCDCY

1

-

LALCATK

0

This register sets Decay Time in Attack Time of the Line ALC.

LALCATK[2:0]

Line ALC Attack Time

setting

8kHz

11.025k

Hz

12kHz

16kHz

22.05kH

z

24kHz

32kHz

44.1kHz

48kHz

Unit

0

1

2

3

4

5

6

7

0.5

1.0

2.0

4.0

8.0

16.0

32.0

64.0

0.4

0.7

1.5

2.9

5.8

11.6

23.2

46.4

0.3

0.7

1.3

2.7

5.3

10.7

21.3

42.7

0.3

0.5

1.0

2.0

4.0

8.0

16.0

32.0

0.2

0.4

0.7

1.5

2.9

5.8

11.6

23.2

0.2

0.3

0.7

1.3

2.7

5.3

10.7

21.3

0.1

0.3

0.5

1.0

2.0

4.0

8.0

16.0

0.1

0.2

0.4

0.7

1.5

2.9

5.8

11.6

0.1

0.2

0.3

0.7

1.3

2.7

5.3

10.7

ms

LALCDCY[2:0]

Line ALC Decay Time

setting

8kHz

11.025k

12kHz

16kHz

22.05kH

z

24kHz

32kHz

44.1kHz

48kHz

Unit

Hz

0

1

2

3

4

5

6

7

64

128

256

512

1024

2048

4096

∞

46

93

43

85

32

64

23

46

93

186

372

743

1486

∞

21

43

85

171

341

683

1365

∞

16

32

64

128

256

512

1024

∞

12

23

46

11

21

43

ms

186

372

743

1486

2972

∞

171

341

683

1365

2731

∞

128

256

512

1024

2048

∞

93

85

186

372

743

∞

171

341

683

∞

LINE ALC Max Gain Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

1

b02

b01

b00

1

R

W

(Initial)

0xc8

0xc9

-

LALCMXGAIN

1

This register sets the ALC MAX GAIN for Line input

LALCGAIN[3:0]

Line ALC Max Gain.

setting

0xF

Description

6dB

0xE

:

0x1

0x0

5dB

(1dB/step)

-8dB

-9dB

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

71/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback ALC Attack Time Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

0

b00

0

R

W

(Initial)

0xdc

0xdd

-

PALCATK

1

This register is to set the attack time that is the step period for the playback ALC volume down.

PALCATK[3:0]

These bits are to set the playback ALC attack time. The playback ALC volume downs step by step per this attack time period.

Attack time is in proportion to sampling frequency(fs) as following table.

setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

fs equivalent

1/fs

Time(fs=48kHz)

20.8us

2/fs

4/fs

8/fs

16/fs

32/fs

64/fs

128/fs

256/fs

512/fs

1024/fs

2048/fs

4096/fs

8192/fs

16384/fs

32768/fs

41.7us

83.3us

167us

333us

667us

1.33ms

2.67ms

5.33ms

10.7ms

21.3ms

42.7ms

85.3ms

171ms

341ms

683ms

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

72/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback ALC Decay Time Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

0

b02

b01

0

b00

1

R

W

(Initial)

0xde

0xdf

-

PALCDCY

1

This register is to set the decay time that is the step period for the playback ALC volume up.

PALCDCY[3:0]

These bits are to set the playback ALC decay time. The playback ALC volume ups step by step per this decay time period.

Decay time is in proportion to sampling frequency(fs) as following table.

setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

fs equivalent

Time(fs=48kHz)

83.3us

167us

4/fs

8/fs

16/fs

32/fs

64/fs

128/fs

256/fs

512/fs

1024/fs

2048/fs

4096/fs

8192/fs

16384/fs

32768/fs

65536/fs

131072/fs

333us

667us

1.33ms

2.67ms

5.33ms

10.7ms

21.3ms

42.7ms

85.3ms

171ms

341ms

683ms

1.37s

2.73s

Playback ALC Target Level Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

1

b03

1

b02

b01

1

b00

1

R

W

(Initial)

0xe0

0xe1

-

PALCLVL

0

This register is to set the target level of the playback ALC.

PALCLVL[4:0]

These bits are to set the target level of the playback ALC.

Target Level

(dBFS)

setting

(dBFS)

-23.25

-22.50

-21.75

-21.00

-20.25

-19.50

-18.75

-18.00

-17.25

-16.50

-15.75

-15.00

-14.25

-13.50

-12.75

-12.00

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

-11.25

-10.50

-9.75

-9.00

-8.25

-7.50

-6.75

-6.00

-5.25

-4.50

-3.75

-3.00

-2.25

-1.50

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

73/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback ALC Min Gain Control Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0xe2

0xe3

-

PALCMINGAIN

0

This register is to set the upper limit and the lower limit at the playback ALC operation.

PALCMINGAIN[2:0]

These bits are to set the lower limit at the playback ALC operation.

Min Gain

setting

(dB)

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

-12.0

-6.0

0.0

+6.0

+12.0

+18.0

+24.0

+30.0

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

74/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback ALC Volume Control Register

INDEX

MAPCON

0x0

b07

b06

0

b05

1

b04

0

b03

b02

0

b01

0

b00

0

R

W

(Initial)

0xe4

0xe5

-

PALCVOL

0

This register is to set the volume that is used in the PALC. It can be set the volume up to +35.625dB. Also this volume can be

used as a playback path boost volume when the PALC is not used.

PALCVOL[6:0]

PALCVOL becomes a fixed gain at the time of “PALCEN=0”.

PALCVOL becomes a PALC Maximum gain at the time of “PALCEN=1”.

Gain

(dB)

Gain

(dB)

Gain

(dB)

Gain

(dB)

PALCVOL

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

-12.000

-11.625

-11.250

-10.875

-10.500

-10.125

-9.750

-9.375

-9.000

-8.625

-8.250

-7.875

-7.500

-7.125

-6.750

-6.375

-6.000

-5.625

-5.250

-4.875

-4.500

-4.125

-3.750

-3.375

-3.000

-2.625

-2.250

-1.875

-1.500

-1.125

-0.750

-0.375

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0.000

0.375

0.750

1.125

1.500

1.875

2.250

2.625

3.000

3.375

3.750

4.125

4.500

4.875

5.250

5.625

6.000

6.375

6.750

7.125

7.500

7.875

8.250

8.625

9.000

9.375

9.750

10.125

10.500

10.875

11.250

11.625

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

12.000

12.375

12.750

13.125

13.500

13.875

14.250

14.625

15.000

15.375

15.750

16.125

16.500

16.875

17.250

17.625

18.000

18.375

18.750

19.125

19.500

19.875

20.250

20.625

21.000

21.375

21.750

22.125

22.500

22.875

23.250

23.625

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

24.000

24.375

24.750

25.125

25.500

25.875

26.250

26.625

27.000

27.375

27.750

28.125

28.500

28.875

29.250

29.625

30.000

30.375

30.750

31.125

31.500

31.875

32.250

32.625

33.000

33.375

33.750

34.125

34.500

34.875

35.250

35.625

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

75/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Playback ALC ZeroCross TimeOut Register

INDEX

MAPCON

0x0

b07

b06

b05

b04

b03

b02

b01

b00

0

R

W

(Initial)

0xe6

0xe7

-

PALCZCTM

0

PALCZCTM[1:0]

This register is to set the value of Zero Cross time out in Playback ALC.

setting

fs equivalent

Time(fs=48kHz)

0x0

128/fs

2.67ms

0x1

256/fs

5.33ms

0x2

512/fs

10.7ms

0x3

1024/fs

21.3ms

Playback Limiter Fast Release Setting Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

1

b03

b02

b01

0

b00

R

W

(Initial)

PALCFREN

0

0xea

0xeb

PALCFRTH

-

PALCFRSP

0

1

This register is to set the fast release in Playback ALC.

PALCFREN

This is to set the Fast Release enable in Playback ALC.

setting

Description

0

1

Disable

Enable

PALCFRSP[1:0]

These bits are to set the release speed in Playback ALC.

Release speed is expressed with PALCDCY.

setting

Release Speed

0x0

0x1

0x2

0x3

(1 / 4) * PALCDCY

(1 / 8) * PALCDCY

(1 / 16) * PALCDCY

(1 / 32) * PALCDCY

PALCFRTH[3:0]

This bit can set the threshold in Fast Release (Playback ALC).

Whether to make Fast Release effective by the gain down in which extent.

Threshold

(1Step=0.375dB)

Threshold

(1Step=0.375dB)

setting

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

13step = 4.875dB

15step = 5.625dB

16step = 6.000dB

17step = 6.375dB

19step = 7.125dB

20step = 7.500dB

21step = 7.875dB

23step = 8.625dB

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

24step = 9.000dB

25step = 9.375dB

27step = 10.125dB

28step = 10.500dB

29step = 10.875dB

31step = 11.625dB

32step = 12.000dB

33step = 12.375dB

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

76/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

LOUT Power Up Control Register

INDEX

MAPCON

0x0

b07

b06

b05

0

b04

b03

0

b02

0

b01

b00

R

W

(Initial)

0xec

0xed

-

LOPWTIM

-

0

This register controls function for pop noise reducer of line amplifier power up and down.

LOPWTIM [3:0]

It is the setting for start/stop time of pop noise reducer. This register setting must not be changed during line amplifier

active.

According to LOPWTIM setting and sampling frequency, the start/stop time of lineamp is changed as below.

Please change LOPWTIM when it changes sampling frequency.

Evaluate it enough for the decision of the value.

Start-up/shut-down time [ms]

fs=8kHz

/ 16kHz

/ 32kHz

fs=11.025kHz

/ 22.05kHz

/ 44.1kHz

fs=12kHz

/ 24kHz

/ 48kHz

0x0

0x1

0.2

0.4

0.3

0.6

0.3

0.5

0x2

0.8

1.1

1.0

0x3

1.6

2.3

2.1

0x4

3.1

4.6

4.2

0x5

6.3

9.1

8.4

0x6

0x7

0x8

0x9

0xA

0xB

to 0xF

12.6

25.1

50.3

100.5

201.1

18.2

36.5

72.9

145.9

291.8

16.8

33.5

67.0

134.0

268.1

Write prohibit

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

77/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

FPLL M setting Register

FPLL N Setting(L) Register

FPLL N Setting(H) Register

FPLL D Setting Register

FPLL F Setting(L) Register

FPLL F Setting(H) Register

FPLL F_D Setting(L) Register

FPLL F_D Setting(H) Register

FPLL V setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

0

b01

b00

0

R

W

(Initial)

0x02

0x04

0x06

0x08

0x0a

0x0c

0x0e

0x10

0x12

0x03

-

FPLLM(*)

0

FPLLNL(*)

0x1

0x05

0x07

0x09

0x0b

0x0d

0x0f

0

-

0

-

0

-

0

-

0

-

0

-

0

FPLLNH(*)

0

0x1

-

FPLLD(*)

0

-

0x1

-

0

FPLLFL(*)

0x1

0

FPLLFH(*)

0x1

FPLLFDL(*)

0x1

0

FPLLFDH(*)

0x1

0x11

0x13

0

-

0

-

0

-

0

FPLLV(*)

0x1

-

0

This register is to set PLL output clock frequency.

Please use PLL Setting Calculation program. The program outputs PLL register setting values.

PLL output frequency gets decided by FPLL Registers as the following expression.

PLL output frequency (Hz)=PLL input frequency / FPLLM × (FPLLN+FPLLD/16+FPLLF/FPLLF_D/16) × 2 / FPLLV

PLL CPMODE setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

0

b03

0

b02

b01

1

b00

0

R

W

(Initial)

0x16

0x17

-

CPMODE(*)

1

CPMODE[4:0]

This bit is to set the ON and OFF of the PLL external loop-filter function.

If PLL is used on condition input frequency is lower than 2MHz, the external loop-filter is necessary.

Set this bit ,if the external loop-filter is necessary.

Recommended external circuit of the loop-filter is decided by PLL frequency. Please ask recommended circuit, if you need.

Setting

0x00110

0x10110

Description

Not use PLL chip external loop-filter (Default)

Use PLL chip external loop-filter

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

78/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Headphone Output Gain Setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

0

b00

0

R

W

(Initial)

0x36

0x37

-

HPVOL

This register is to set the gain of Headphone Output.

HPVOL[1:0]

This bit is to set the gain of Headphone Output. When beep input is used, please set data to 0x3.

Setting

0x0

0x1

0x2

Description

-6dB (It is prohibition to use with beep input)

0dB (It is prohibition to use with beep input)

3dB (It is prohibition to use with beep input)

6dB

0x3

Analog Path Control Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

1

b01

b00

1

R

W

(Initial)

0x3e

0x3f

-

HALF

1

HPBPEN LINDACEN

ADCSET

1

0

This register adjusts ADC characteristics, and set signal path of analog section.

ADCSET

This register adjust ADC characteristics. Use by 0x7

ADCSET

Description

0x7

Use by 0x7

LINDACEN

Set signal path about from DAC to LINMIX amplifier.

*Please set to “0” with recording monitor mode (0x13=0x07)

LINDACEN

Description

0

1

Don’t connect DAC output to LINMIX amplifier.

Connect DAC output to LINMIX amplifier.

HPBPEN

Set signal path about from BEEPIN amplifier to Head phone amplifier.

HPBPIN

Description

0

1

Don’t connect BEEPIN amplifier output to Head phone amplifier.

Connect BEEPIN amplifier output to Head phone amplifier.

HALF

Set the gain of MIC amplifier on input block.

HALF

Description

0

1

0dB

-6dB

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

79/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Record L Balance Volume Control Register

Record R Balance Volume Control Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x74

0x75

-

RBLVOLL

1

0

RBLVOLR

0

0x1

0x76

0x77

This register is to set “L/R Balance” block in digital signal flow, when ADC-path is used.

Left and Right volume are available to be set from -6.0dB to 6.0dB at 0.1dB step each.

RBLVOLL, RBLVOLR[6:0]

Setting

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

Gain(dB)

-6.0

-5.9

-5.8

-5.7

-5.6

-5.5

-5.4

-5.3

-5.2

-5.1

-5.0

-4.9

-4.8

-4.7

-4.6

-4.5

-4.4

-4.3

-4.2

-4.1

-4.0

-3.9

-3.8

-3.7

-3.6

-3.5

-3.4

-3.3

-3.2

-3.1

-3.0

-2.9

Setting

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

Gain(dB)

-2.8

-2.7

-2.6

-2.5

-2.4

-2.3

-2.2

-2.1

-2.0

-1.9

-1.8

-1.7

-1.6

-1.5

-1.4

-1.3

-1.2

-1.1

-1.0

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

Setting

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

Gain(dB)

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Setting

Gain(dB)

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0.1

0.2

0.3

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

80/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Stereo Enhancer Control Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x86

0x87

-

STEEN

0

STEOD

0

This register is to set “Stereo Enhancer” block in digital signal flow. This is to control Stereo enhancer function.

This function is effective for DAC-path(playback) at “STEEN=1” and “SEMODE[7]=1”.

STEOD

This bit is to set number of low pass filter order for Stereo enhancer.

setting

Description

second-order , LPF1and LPF2 are effective.

first-order , only LPF1 is effective.

0

1

STEEN

This bit is to set Enable/Disable of low pass filter for Stereo enhancer.

setting

Description

Stereo enhancer Disable

Stereo enhancer Enable

0

1

Stereo Enhancer LPF1 CoefL Register

Stereo Enhancer LPF1 CoefH Register

Stereo Enhancer LPF2 CoefL Register

Stereo Enhancer LPF2 CoefH Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0x88

0x8a

0x8c

0x8e

0x89

STE1CUT[7:0]

0

STE1CUT[15:8]

0x1

0x8b

0x8d

0x8f

0

STE2CUT[7:0]

0x1

0

STE2CUT[15:8]

0x1

0

This register is to set “Stereo Enhancer” block in digital signal flow. This is to set LPF of Stereo enhancer function.

STE1CUT[15:0]

This bit is to set the first low pass filter cut off frequency for Stereo enhancer.

STE2CUT[15:0]

This bit is to set the second low pass filter cut off frequency for Stereo enhancer.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

81/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Play Programable LPF Setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xa0

0xa1

-

PLPFOD PLPFEN

0

This register is to set “LPF” block for DAC-path(playback) in digital signal flow. This is to set Enable/Disable and filter order.

This function is effective for DAC-path(playback) at “PLPFEN=1” and “SEMODE[7]=1”.

PLPFEN

This bit is to set Enable/Disable of low pass filter for DAC-path.

setting

Description

0

1

LPF for DAC-path is Disable

LPF for DAC-path is Enable

PLPFOD

This bit is to set number of low pass filter order for DAC-path.

setting

Description

0

1

LPF for DAC-path is second-order

LPF for DAC-path is first-order

Play Programable LPF Coef (L) Register

Play Programable LPF Coef (H) Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0xa2

0xa3

PLPFC0L

0

PLPFC0H

0x1

0xa4

0xa5

0

This register is to set “LPF” block for DAC-path(playback) in digital signal flow. This is to set Enable/Disable and filter order.

PLPFC0L [7:0] / PLPFCOH [7:0]

This bit is to set low pass filter cut off frequency for DAC-path.

This value has to change by Sampling frequency.

Please use Filter Setting Calculation program for *PLPFC0L / PLPFC0H setting.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

82/92

TSZ22111・15・001

Jul.1.2014 Rev.001

Daattaasshheeeett

BU26156RFS

Rec Programable LPF Setting Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

b02

b01

b00

R

W

(Initial)

0xa6

0xa7

-

RLPFOD RLPFEN

0

This register is to set “LPF” block for ADC-path(record) in digital signal flow. This is to set Enable/Disable and filter order.

This function is exclusive to “HPF2” controlled by HPF2EN of DSP Filter Function Enable register.

This function is effective for ADC-path(record) at “RLPFEN=1” and “SEMODE[7]=1”.

RLPFEN

This bit is to set Enable/Disable of low pass filter for ADC-path.

RLPFEN

Description

0

1

LPF for DAC-path is Disable (HPF2 is available)

LPF for DAC-path is Enable(HPF2 is not available. HPF2EN-bit is not valid)

RLPFOD

This bit is to set number of low pass filter order for ADC-path.

RLPFOD

Description

0

1

LPF for ADC-path is second-order

LPF for ADC-path is first-order

Rec Programable LPF Coef (L) Register

Rec Programable LPF Coef (H) Register

INDEX

MAPCON

0x1

b07

b06

b05

b04

b03

0

b02

b01

b00

R

W

(Initial)

0xa8

0xa9

RLPFC0L

0

RLPFC0H

0x1

0xaa

0xab

0

This register is to set “LPF” block for ADC-path(playback) in digital signal flow.

RLPFC0L [7:0] / RLPFCOH [7:0]

This bit is to set low pass filter cut off frequency for ADC-path.

This value has to change by Sampling frequency.

Please use Filter Setting Calculation program for *RLPFC0L / RLPFC0H setting.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

83/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Typical Performance Curves (Reference data)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

MALCMXGAIN=20.25dB

LALCMXGAIN=6.0dB

-10

MALCMXGAIN=9.0dB

-20

-30

-40

-50

-60

LALCMXGAIN=-9.0dB

-70

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃,

-80

-90

-80

-60

-40

-20

0

-80

-60

-40

-20

0

Input Level [dBV]

Figure 38.

Input Level [dBV]

Figure 39.

Input Level [dBV] vs Output Level [dBFS]

Analog Mic Input tot ADC out, MALCEN=0

Input Level [dBV] vs Output Level [dBFS]

Analog Line Input tot ADC out, LALCEN=0

0

10

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

SPLVDD=SPRVDD=5V, 25℃,

-20

-30

-40

-50

-60

-70

-80

-90

LALCMXGAIN=6.0dB

MALCMXGAIN=9.0dB

LALCMXGAIN=-9.0dB

MALCMXGAIN=20.25dB

-80

-60

-40

-20

0

-80

-60

-40

-20

0

Input Level [dBV]

Figure 40.

Input Level [dBV]

Figure 41.

Input Level [dBV] vs THD+N [dB]

Analog Line Input tot ADC out, LALCEN=0

Input Level [dBV] vs THD+N[dB]

Analog Mic Input tot ADC out, MALCEN=0

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

84/92

Daattaasshheeeett

BU26156RFS

0

-10

-20

-30

-40

-50

SPMIXG=18dB

-10

-20

-30

-40

-50

SPMIXG=12dB

SPMIXG=6dB

SPMIXG=0dB

SPMIXG=6dB

SPMIXG=0dB

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃,

SPVOL=DSP Gain=0dB

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃,

SPVOL=DSP Gain=0dB

-50

-40

-30

-20

-10

0

-50

-40

-30

-20

-10

0

Input Level [dBFS]

Figure 43.

Input Level [dBFS]

Figure 42.

Input Level [dBFS] vs Output Level [dBV]

Digital DAC Input to Class-D Speaker output

Input Level [dBFS] vs Output Level [dBV]

Digital DAC Input to Class-AB Speaker output

0

-10

-20

-30

-40

-50

-60

-70

0

HVDD1=IOVDD=HPVDD =3.3V

SPLVDD=SPRVDD=5V, 25℃,

SPVOL=DSP Gain=0dB

HVDD1=IOVDD=HPVDD=3.3V

SPLVDD=SPRVDD=5V, 25℃,

SPVOL=DSP Gain=0dB

-10

SPMIXG=18dB

SPMIXG=12dB

SPMIXG=6dB

SPMIXG=0dB

SPMIXG=18dB

SPMIXG=12dB

SPMIXG=6dB

-20

-30

-40

-50

-60

-70

SPMIXG=0dB

-50

-40

-30

-20

-10

0

-50

-40

-30

-20

-10

0

Input Level [dBFS]

Figure 44.

Figure 45.

Input Level [dBFS] vs THD+N [dB]

Digital DAC Input to Class-D Speaker output

Input Level [dBFS] vs THD+N [dB]

Digital DAC Input to Class-AB Speaker output

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

85/92

Daattaasshheeeett

BU26156RFS

I/O equivalence circuits

No.

Name

I/O

Power

I/O equivalence circuits

HVDD1

17

MICBIAS

O

HVDD1

ＡGND

REGOUT

37

VMID

O

REGOUT

ＡGND

REGOUT

33

PLLC

O

REGOUT

HVDD1

ＡGND

REGOUT

15

BEEPIN

I

AGND

HVDD1

16

MICBIASREF

O

AGND

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

86/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

No.

Name

I/O

Power

I/O equivalence circuits

IOVDD

32

29

24

22

MCLKI

SDIN

CSB/SCL

SCLK/SAD

I

IOVDD

DGND

IOVDD

DGND

31

30

26

23

28

BCLK

LRCLK

IRQB

IO

IOVDD

SDATA/SDA

SDOUT

IOVDD

25

RESETB

I

IOVDD

DGND

HVDD1

20

REGOUT

O

HVDD1

AGND

SPRVDD

11

12

SPRP

SPRM

O

SPRVDD

SPRGND

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

87/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

No.

Name

I/O

Power

I/O equivalence circuits

IOVDD

14

SPMUTE

I

IOVDD

DGND

SPLVDD

8

7

SPLP

SPLM

O

SPLVDD

SPLGND

HPVDD

2

1

HPOUTR

HPOUTL

O

HPVDD

HPGND

REGOUT

HPVDD

4

HPOUTCAP

O

HPVDD

HPGND

AGND

REGOUT

38

40

42

39

41

43

LIN1L

LIN2L

LIN3L

LIN1R

LIN2R

LIN3R

I

REGOUT

AGND

REGOUT

35

34

MINP

MINM

I

REGOUT

AGND

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

88/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Cautions on use

1) Absolute Maximum Ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,

can break down devices, thus don’t exceed the absolute maximum ratings of supply voltage, temperature. If any special

mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety

measures including the use of fuses, etc.

2) GND voltage

Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.

3) Short circuit between terminals and erroneous mounting

In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting

can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or

between the terminal and the power supply or the GND terminal, the ICs can break down.

4) Operation in strong electromagnetic field

Be noted that using ICs in the strong electromagnetic field can malfunction them.

5) Thermal design

If use speaker amplifier function, please consider power dissipation by an actual using status, and perform the thermal

design which have a margin enough. If an input signal is made excessive in the state with insufficient heat dissipation,

desired output power may not only be securable, but the thermal shutdown may operate.

6) Thermal shutdown

This IC has the thermal shutdown circuit. If the thermal shutdown operates, speaker output terminal and Headphone

Output terminal will stop in the open state(high impedance state).The thermal shutdown is only a function for

suspending the output operation of IC to the last at the time of the thermal run-away under the abnormal condition in

which chip temperature(Tjmax) exceeded 170 degrees. It is a circuit to protect IC, and the purpose is not offering

protection and a guarantee of the set.

7) Short protection of output terminals

This IC has the short protect function for output terminals. If the short protect function operates, output terminal will be

latched and stop in the open state(high impedance state).After a stop, even if a short state is removed, it does not return

to normal operation automatically. Please once write speaker amplifier enable register to make it return.

8) Operating condition

Operating voltage and operating temperature are ranges which perform basic function. Electrical characteristics and

absolute maximum rating are not guaranteed in full voltage range or full temperature range.

9) Electrical characteristics specification

Each audio characteristic specification, such as limit output power, total harmonic distortion, the maximum gain, an ALC

limit level, and an ALC release level, shows the standard performance of the device, and depends for it on board layout /

use parts / power supply part greatly.

Typical specification value is a value when a device and each parts are directly mounted in the board of Rohm's

standard.

10) Power supply

Since the speaker L power supply (SPLVDD) and the speaker R power supply (SPRVDD) are shorted inside IC, please

use them as a same power supply.

Moreover, large peak current rushes into a power supply line at the time of ClassD speaker amplifier use.

The audio characteristic is affected by the value of a power supply decoupling capacitor, and layout.

The power supply decoupling capacitor should be layouted (1uF or more) with sufficiently low ESR (equivalent series

resistance) to most close of IC terminal.

Moreover, in the design of a board pattern, the wiring of a power supply / GND line should become low impedance. In

that case, even if digital power supply and analog power supply are same potential, please devide the digital power

pattern and the analog power pattern and reduce a surroundings lump of the digital noise to the analog power supply by

the common impedance of a wiring pattern.

Please take the same pattern design into consideration also about a GND line. Moreover, while inserting a capacitor

between power supply-GND terminals about all the power supply terminals of LSI, and please determine the value of

capacitor after sufficient confirmation that there is no problem in the characteristics of capacitors to be used (a capacity

omission happens at low temperature) in the case of electrolytic capacitors use.

11) External capacitor

In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a

degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

89/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

12) Status of this document

The Japanese version of this document is formal specification. A customer may use this translation version only for a

reference to help reading the formal version.

If there are any differences in translation version of this document formal version takes priority.

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

90/92

TSZ22111・15・001

Daattaasshheeeett

BU26156RFS

Ordering Information

B U 2 6 1 5 6 R

F

S

E 2

Package

RFS:HTSSOP-A44R

Packaging and forming specification

E2: Embossed tape and reel

Physical Dimension Tape and Reel Information

Package Name

VQFN040V6060

Marking Diagram

HTSSOP-A44R (TOP VIEW)

Part Number Marking

LOT Number

1PIN MARK

www.rohm.co.jp

TSZ22111・15・001

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

91/92

Daattaasshheeeett

BU26156RFS

Revision History

Date

Revision

Rev.001

Page

Item

Changes

-

Rev.001. Release.

Jun.24.2014

www.rohm.co.jp

TSZ02201-0V1V0E502570-1-2

Jul.1.2014 Rev.001

92/92

TSZ22111・15・001

Daattaasshheeeett

General Precaution

1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.

ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny

ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s

representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.

Notice – WE

Rev.001


型号：	BU26156RFS
厂家：	ROHM
描述：	BU26156RFS是内置丰富的音响处理功能的低功耗立体声Audio CODEC。输入方面具备最大可输入2Vrms振幅的立体声线路和单声道麦克风输入，输出方面具备可进行AB类/D类切换的2.5W级立体声扬声器放大器和立体声耳机输出。通过内置稳压器向对噪声敏感的CODEC部供电，实现了不受电源电路特性影响的稳定的Audio性能。放大器电源电路稳压器
文件：	总95页 (文件大小：1819K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU26156RFS [ROHM]

相关型号：

BU2615F

BU2615F-DX

BU2615F-DXE1

BU2615F-DXE2

BU2615F-DXT1

BU2615F-DXT2

BU2615F-E1

BU2615F-E2

BU2615F-T1

BU2615F-T2

BU2615FE1

BU2615FE2