BU1850MUV_技术文档

GPIO ICs Series

GPIO Expander IC

BU1850MUV

No.09098EAT02

●Description

GPIO expander is useful especially for the application that is in short of IO ports.

It can

1. Control GPIO output states by I²C write protocol.

2. Know GPIO input states by I²C read protocol.

Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander.

GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output.

●Features

1) An 8-Port General purpose input/output interface 150kΩPull-down resistance.

2) NMOS Open-drain output interrupt controller with up to 1us pulse noise filter and bit mask function for

individual GPIO port.

3) 3volt tolerant Input

4) Built-in Power On Reset

5) 3mmx3mm small package

●Absolute maximum ratings

(Ta=25 ^oC)

Parameter

Supply Voltage^*1

Symbol

VDD

VDDIO

VI

Rating

-0.3 ~ +4.5

Unit

V

comment

VDD≦VDDIO

-0.3 ~ +4.5

V

-0.3 ~ VDD +0.3^*1

V

XRST, ADR

Input voltage

VIT

-0.3 ~ 4.5

V

XINT, SCL, SDA, GPIO[7:0]

Storage temperature range

Tstg

PD

-55 ~ +125

272^*2

℃

Package power

mW

This IC is not designed to be X-ray proof.

*1 It is prohibited to exceed the absolute maximum ratings even including +0.3 V.

*2 Package dissipation will be reduced each 2.72mW/ ^oC when the ambient temperature increases beyond 25 ^oC.

●Operating conditions

Parameter

Symbol

V_VDD

Min

Typ

Max

3.6

Unit

V

Conditions

Core, XINT, XRST,

SCL, SDA, ADR,

Power On Reset

Supply voltage range (VDD)

Supply voltage range (VDDIO)

1.65

1.80

V_VDDIO

V_IN

1.65

-0.2

1.80

3.6

V_VDD+0.2

3.6

V

GPIO[7:0]

-

XRST, ADR

Input voltage range

XINT, SCL, SDA,

GPIO[7:0]

V_INT

Operating temperature range

I²C operating frequency

Topr

F_I2C

-30

-

+85

400

℃

kHz

Slave

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2009.09 - Rev.A

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Technical Note

BU1850MUV

●Package Specification

B U 1

8 5 0

Lot No.

(UNIT: mm)

Fig.1 Package Specification (VQFN016V3030)

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2009.09 - Rev.A

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Technical Note

BU1850MUV

●Pin Assignment

13 GPIO4

14 GPIO5

15 GPIO6

16 GPIO7

8 VSS

7 VDDIO

6 VDD

5 SDA

Fig.2 Pin Diagram (Top View)

●Block Diagram

Functional Block Diagram

Interrupt

Filter

Interrupt

Logic

XINT

VDD

INT_MASK

IN/OUT

Control

ADR

VDDIO

GPIO

[7:0]

Shift

Register

8bit

GPIO[7:0]

Input

Filter

I²C Bus

Control

SCL

SDA

Power

On

Reset

Write Pulse

Read Pulse

Reset

Gen

XRST

VSS

Fig.3 Functional Block Diagram

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Technical Note

BU1850MUV

●Pin-out Functional Descriptions

Power source

system

Cell

Type

PIN name

No.

I/O

O

Function

Init

Interrupt signal (1s pulse cut)^*1

1

XINT

VDD

Hi-Z

B

(NMOS Open-drain)

2

3

4

XRST

SCL

I

VDD

Reset（Low Active）

Clock for I²C

I

E

A

E

ADR

Select device address of I²C

Serial data inout for I²C

(NMOS Open-drain)

Power supply (Core, I/O, Power On

Reset)

5

6

SDA

VDD

I/O

-

VDD

-

Hi-Z

-

C

-

7

VDDIO

VSS

-

Power supply (I/O)

GND

-

8

-

9

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

I/O

VDDIO

10

11

12

13

14

15

16

General purpose input/output.

(NMOS Open-drain^*2/CMOS Output,

150kΩPull-down^*3)

I

D

Pull-down

*1 Specific bit mask control is decided by internal register value.

*2 Pull-up more than VDDIO voltage.

*3 It is possible to select Pull-down ON or OFF with register.

B

C

D

A

E

Fig.4 Equivalent IO circuit diagram

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Technical Note

BU1850MUV

●Functional Description

1. Power Modes

The device enters the state of Power Down when XRST=”Low” or enters the operation state when XRST=High after

powered.

Refer to “Electrical Specification” section 5 for a detailed startup sequence.

1-1 Power supply

A single supply to Core power supply (VDD) and IO power supply (VDDIO) is prohibited.

Supply the power supply to the Core power supply and the IO power supply at the same time.

1-2 Power On Reset

A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is

not used. In this case, the XRST port must be connected to high(VDD).

1-3 State of Power Down

The device enters the state of Power Down by XRST=”Low”. An internal circuit is initialized and I²C interface is

invalid is input. Power On Reset becomes inactive during this state.

1-4 State of operation

The device enters the operation state by setting XRST to "High". The I²C interface starts communication is

the START condition. It becomes standby by the STOP condition. Power On Reset is active in this state.

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Technical Note

BU1850MUV

2. I²C Bus Interface

Each function of GPIO is controlled by an internal register. The I²C Slave interface is used to write or read this internal

register. The device supports up to 400kHz Fast-mode data transfer rate.

2-1 Slave address

Two device addresses (Slave address) can be selected by ADR port.

A7

0

A6

0

A5

0

A4

1

A3

0

A2

0

A1

1

R/W

1/0

ADR=0

ADR=1

0

1

0

2-2 Data transfer

One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should

keep the value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted

as a control signal.

SDA

SCL

Data is valid

SDA is

when SDA is variable

stable

Fig.5 Data transfer

2-3 START-STOP-Repeated START conditions

When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers

from “1” to “0”, it means a “Start condition” is occurred and access is started.

If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is

stopped.

It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not

done.

SDA

SCL

S

Sr

P

STOP Condition

START Condition

Repeated START Condition

Fig.6 START-STOP-Repeated START conditions

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Technical Note

BU1850MUV

2-4 Acknowledge

After start condition is occurred, 8 bits data will be transferred. SDA is latched by the rising edge of SCL.

Then the “Master” opens SDA to “1” and “Slave” de-asserts SDA to “0” as an “Acknowledge” returned.

Fig.7 Acknowledge

2-5 Writing protocol

Register address is transferred after one byte of slave address with R/W bit. The 3^rdbyte data is written to internal

register which defined by the 2^ndbyte. However, when the register address increased to the final address (13h), it

will be reset to (00h) after the byte transfer.

S

X

0

A

X

X A4 A3 A2 A1 A0 A D7D6D5D4D3D2D1D0 A

D7D6D5D4D3D2D1D0 A

data

P

Slave address

Register address

data

R/W=0(write)

Register address

increment

Register address

increment

Transmit from master

A=acknowledge

A=not acknowledge

S=Start condition

P=Stop condition

Transmit from slave

Fig.8 Writing protocol

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Technical Note

BU1850MUV

2-6 Reading protocol

After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address

is next of previous accessed address. Therefore, the data is read with address increment. When the address in

increased to the last, the following read address will be reset to (00h).

Fig.9 Readout protocol

2-7 Complex reading protocol

After the specifying the internal register address, a repeated START condition occurs and the direction of data

transfer is changed then reading access is done. Therefore, the data is read followed by address increment. If the

address is increased to the last, it will be reset to (00h).

S

X

0

A

X

X A4 A3 A2 A1 A0 A Sr X

Register address

X X X X X X 1 A

Slave address

R/W=0(write)

R/W=1(read)

D7D6D5D4D3D2D1D0 A

data

D7D6D5D4D3D2D1D0 A

data

P

Register address

increment

Register address

increment

A=acknowledge

A=not aclnowledge

S=Start condition

P=Stop condition

Transmit from master

Transmit from slave

Sr=Repeated Start condition

Fig.10 Complex reading protocol

2-8 Illegal access of I²C

The data accessed at that time is annulled, and access it again.

The illegal accesses are as follows.



The START condition and the STOP condition are continuously generated.

When the Slave address and the R/W bit is written, repeated START condition and the STOP

condition are generated.



Repeated START condition and the STOP condition are generated while writing data.

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Technical Note

BU1850MUV

3. Register configuration

The address is increased one by one when data is continuously written.

When the final address is set to 13h, then the next address 00h will be written.

By making XRST “Low”, the setting register value will be initialed shown in following register map.

3-1 Register map

Addr

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

Init

Type

D7

D6

D5

D4

D3

D2

D1

D0

reserved

RESET

reserved

INTEN7

reserved

GPI7

reserved

INTEN6

reserved

GPI6

reserved

INTEN5

reserved

GPI5

reserved

INTEN4

reserved

GPI4

reserved

INTEN3

reserved

GPI3

reserved

INTEN2

reserved

GPI2

reserved

INTEN1

reserved

GPI1

reserved

INTEN0

reserved

GPI0

-

00h

R/W

-

00h

R/W

-

00h

R

GPO7

GPO6

GPO5

GPO4

GPO3

GPO2

GPO1

GPO0

R/W

WRSEL7

XPD7

WRSEL6

XPD6

WRSEL5

XPD5

WRSEL4

XPD4

WRSEL3

XPD3

WRSEL2

XPD2

WRSEL1

XPD1

WRSEL0

XPD0

※

Do not write reserved resisters excluding "0". 10h address register is disregarded even if it is written.

3-2 Resister function

※

n is the number of GPIO[7:0] ports.

Symbol

RESET

INTENn

GPIn

Addr

04h

08h

10h

11h

12h

13h

Description

The register is returned to an initial value by writing "1". This register value is returned to "0".

GPIn register is not initialized.

Interrupt of GPIOn port is enabled by "1". It is masked by "0".

Read GPIOn port. Writing is disregarded.

GPOn

Output value of GPIOn port.

WRSELn

XPDn

GPIOn port is input by "0" and output by "1".

Pull-down of GPIOn port is on by "0" and off by "1". GPIOn should be input.

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Technical Note

BU1850MUV

4. GPIO-Interrupt

4-1 GPIO configuration

As the default value, GPIO[7:0] ports are input and Pull-down.

At this time, WRSELn is "0" and XPDn is "0". (n is the number of GPIO[7:0] ports.)

Refer to the following for the configuration of GPIO.

Register

State of GPIO

GPOn

WRSELn

XPDn

Input, Pull-down ON

Input, Pull-down OFF

Output, H drive

*

0

1

0

1

*

1

0

Output, L drive

*

1

Output, Hi-Z -1^※

1

※

Make external Pull-up the terminal potential which is the potential of V_VDDIOor more.



About GPIO port not used

When making it to the output, open it.

When making it to the input, do not open it. It is forced by "0" or Pull-down on.

When interrupt is enabled, mask INTEN register in which the port is not used to "0".

4-2 Interrupt configuration

When interrupt is generated, L is output from XINT port. The default value is Hi-Z. Make it Pull-up.

For the default value, interrupt is masked with INTEN register "0".

The bit to be used is made "1", and the mask is released. WRSEL register should be "0"(input).

4-3 Write to GPIO port

After setting the internal register address, the data from master is written from MSB.

After Acknowledge is returned, the value of each GPIO port will be changed.

When the register is written, Write Configuration Pulse is generated according to the timing of Acknowledge.

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

0

Ack MSB

Reg Address

LSB Ack MSB

Data1 (GPO[7:0])

LSB Ack

P

Acknowledge From Slave

Stop Condition

Start Condition

Write

Acknowledge From Slave

Write Configuration

Pulse

Data1

Valid

GPIO[7:0]

tDV

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

0

Ack MSB

Reg Address

LSB Ack MSB

Data1 (GPO[7:0])

LSB Ack MSB

WRSEL = Write Mode

LSB Ack

P

Acknowledge From Slave

Stop Condition

Start Condition

Write

Acknowledge From Slave

Write Configuration

Pulse

Data1

Valid

GPIO[7:0]

tDV

Fig.11 Write to GPIO port

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Technical Note

BU1850MUV

4-4 Read from GPIO port

After writing of the Slave address and R/W bits, reading GPIO port is begun from the following byte.

The data that had been being fixed between the following Acknowledge after Acknowledge is taken into the GPI

register, and it is transmitted to Master.

All ports that are the input by WRSEL register are read to the GPI register according to the timing of Read

Configuration Pulse. Therefore, the data of each bit that SDA transmits is the GPI register value taken immediately

before that.

SCL

SDA

1

2

3

4

5

6

7

8

9

D1 D1 D1 D1 D2 D2 D2 D2

[7] [6] [5] [4] [3] [2] [1] [0]

S

X

1

Ack

NA

P

Stop Condition

Start Condition

Read

Acknowledge From Slave

No Acknowledge From Master

Read Configuration

Pulse

GPI[7:0] Reg

GPIO[7:0]

D1

D2

D1

D2

t

DS

tDH

t

DS

t

DH

Fig.12 Read from GPIO port

4-5 Interrupt Valid/Reset

If GPIO port becomes different from the GPIn register (default is "0"), XINT port is changed from "1" into "0".

It becomes "1" to release "0" of XINT port after acknowledge by reading GPI register. Because the value of GPIO

port is reflected in the output as it is and is not latched, XINT becomes "1" again if the port returns to the same

value.

If the ports with INTEN register "1" are different even by one, XINT becomes "0".

If it is distinguished which GPIO port changes, it is necessary to keep the GPI register value on the master side

and compare with the value that is read after XINT is asserted.

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

1

Ack MSB

Data2 (GPI[7:0])

LSB NA

P

Stop Condition

Start Condition

Read

Acknowledge From Slave

No Acknowledge From Master

Data3

GPIOn

GPIn Reg

XINT

Data1

Data2

Data1

Data2

tIV

tIR

tIV

tIR

Fig.13 Interrupt Valid/Reset

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Technical Note

BU1850MUV

●Electrical Specification

1. DC characteristics

V_VDD=1.8V，V_VDDIO=1.8V，Topr=25℃

Specification

Typ

Parameter

Symbol

Unit

Conditions

Min

Max

3.6

0.7xV_VDDIO

Input H Voltage1

Input L Voltage1

Input H Voltage2

Input L Voltage2

Input H Voltage3

V_IH1

V_IL1

V_IH2

V_IL2

V_IH3

-

V

GPIO[7:0]

0.3xV_VDDIO

3.6

-0.2

0.7xV_VDD

-0.2

SCL, SDA,

0.3xV_VDD

V_VDD+0.2

SCL, SDA, XRST, ADR

XRST, ADR

0.7xV_VDD

Input H Current1

(3V Tolerant)

I_IH1

-1

-

1

V_IN=3.6V^*1

A

Input H Current2

Input L Current

I_IH2

I_IL

-1

-

1

V_IN=1.8V, XRST,ADR

V_IN=0V^*1, XRST,ADR

I_OH=-2mA, GPIO[7:0]

I_OL=2mA, GPIO[7:0]

I_OH=-0.2mA, GPIO[7:0]

I_OL=0.2mA, GPIO[7:0]

I_OL=3mA, SDA, XINT

A

V

-1

1

0.75xV_VDDIO

Output H Voltage1

Output L Voltage1

Output H Voltage2

Output L Voltage2

Output L Voltage3

V_OH

V_OL

V_OH

1

-

0.25xV_VDDIO

1

-

V

V_VDDIO-0.25

2

-

V

0.25

0.3

V_OL

2

3

-

V

V_OL

V

*1 XINT(Hi-Z), XRST, SCL, SDA(IN), ADR, GPIO[7:0](IN, Pull-down OFF)

2. Circuit Current

_VDD=1.8V，V_VDDIO=1.8V，Topr=25℃

V

Specification

Typ

Parameter

Symbol

Unit

Condition

Min

-

Max

1.0

Power Down Current

I_PD1

-

XRST=VSS

A

(VDD)

Power Down Current

I

_PD2

-

1.0

3.0

1.0

25

8

(VDDIO)

Standby Current

XRST=VDD,

SCL=VDD, SDA=VDD

I_STBY1

-

(VDD)

Standby Current

I

_STBY2

-

(VDDIO)

Operating Current1

I²C 400kHz

I_OP1

14

2

(VDD)

100% traffic density^*1

Operating Current1

I²C 400kHz

I

_OP2

(VDD)

1% traffic density^*2

*1 All GPIO ports are output, and they repeat 01010101 and 10101010.

*2 The period when I²C did not operate was inserted in *1 pattern by 99%.

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2009.09 - Rev.A

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Technical Note

BU1850MUV

3. I²C AC characteristics

State

（Repeated）

START

BIT 7

BIT 6

Ack

STOP

tSU;STA

1/fSCLK

tHIGH

tLOW

SCL

SDA

tSU;STO

tSU;DAT

tHD;DAT

tBUF

tHD;STA

Fig.14 I²C AC Timing

V_VDD=1.8V，V_VDDIO=1.8V，Topr=25℃

Specification

Parameter

Symbol

Unit

Conditions

Min

Typ

-

Max

SCL Clock Frequency

Bus free time

f_SCLK

-

400

kHz

s

ns

s

t_BUF

1.3

0.6

1.3

0.6

100

0

-

(Repeated)START Condition

Setup Time

t_SU;STA

t_HD;STA

t_LOW

(Repeated)START Condition

Hold Time

SCL Low Time

SCL High Time

t_HIGH

Data Setup Time

Data Hold Time

t_SU;DAT

t_HD;DAT

t_SU;STO

STOP Condition Setup Time

0.6

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Technical Note

BU1850MUV

4. GPIO AC Characteristics

State

BIT 1

BIT 0

Ack

BIT 1

BIT 0

Ack

SCL

GPIO[7:0](Output)

GPIO[7:0](Input)

XINT

tDV

tDS

tDH

tIV

tIR

Fig.15 GPIO AC timing

Specification

V

_VDD=1.8V，V_VDDIO=1.8V，Topr=25℃

Parameter

Symbol

Unit

Conditions

Min

Typ

-

Max

Output Data Valid Time

Input Data Setup Time

Input Data Hold Time

Interrupt Valid Time

Interrupt Reset Time

t_DV

t_DS

t_DH

t_IV

-

100

0.8

-

0.8

-

See Fig.11

s

ns

s

-

See Fig.12

See Fig.13

-

5

t_IR

-

5

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Technical Note

BU1850MUV

5. Startup sequence

t_VDD

VDD,

VDDIO

t_RV

t_RWAIT

t_VDD

XRST

SCL

t_I2CWAIT

SDA

Fig.16 Start Sequence timing

Specification

V_VDD=1.8V，V_VDDIO=1.8V，Topr=25℃

Parameter

Symbol

Unit

Conditions

Min

Typ

-

Max

5

VDD and VDDIO are ON at the

same time.

VDD Stable Time

Reset Wait Time

Reset Valid Time

I²C Wait Time

t_VDD

t_RWAIT

t_RV

-

ms

s

XRST controlling ^*1

0

-

10

t_I2CWAIT

*1 Even if XRST port is not used, it operates because Power On Reset is built in.

In this case, connect XRST port with VDD on the set PCB.

Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT,

and GPIO[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of GPIO[7:0] ports)

VDD

0V

3V

Port

(2kΩ Pull-Up)

0V

0.1～1mA

Port

Pull Current

2～3ms

Fig.17 Port operating at VDD=0V

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Technical Note

BU1850MUV

●Application circuit example

1.8V

3.0V

0.1uF

MPU

ADR

GPIO7

IN

XINT

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

XINT

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

SCL

SDA

SCL

SDA

SCL

SDA

Other I²C Devices

Fig.18 Application circuit example

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Technical Note

BU1850MUV

●Ordering part number

B U

1

8

5

0

M U V

-

E

2

Part No.

Package

Packaging and forming specification

E2: Embossed tape and reel

MUV:

VQFN016V3030

3.0 0.1

Tape

Embossed carrier tape

3000pcs

Quantity

E2

Direction

of feed

1PIN MARK

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

S

(

)

0.08

S

1.4 0.1

C0.2

0.5

1

4

16

13

5

8

12

9

+0.05

–0.04

Direction of feed

1pin

0.25

0.75

Reel

Order quantity needs to be multiple of the minimum quantity.

(Unit : mm)

∗

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Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

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型号：	BU1850MUV
厂家：	ROHM
描述：	GPIO Expander IC GPIO扩展器IC 并行IO端口微控制器和处理器外围集成电路
文件：	总18页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU1850MUV [ROHM]

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