BR9080ARFV-WE1 [ROHM]
EEPROM, 512X16, Serial, CMOS, PDSO8;
| 型号： | BR9080ARFV-WE1 |
| 厂家： | 
ROHM |
| 描述： | EEPROM, 512X16, Serial, CMOS, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
8k, 16k bit EEPROMs for direct
connection to serial ports
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
The BR9080A and BR9016A series are serial EEPROMs that can be connected directly to a serial port and can be
erased and written electrically. Writing and reading is performed in word units, using four types of operation commands.
Communication occurs though CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling
these EEPROMs to be used as one-time ROMs. During writing, operation is checked via the internal status check.
!Applications
Movie, camera, cordless telephones, car stereos, VCRs, TVs, DIP switches, and other battery-powered equipment
requiring low voltage and low current
!Features
1) BR9080AF-W / ARFV-W / ARFVM-W (8k bit) : 512 words ×16 bits
BR9016AF-W / ARFV-W / ARFVM-W (16k bit) : 1024 words × 16bits
2) Single power supply operation
3) Serial data input and output
4) Automatic erase-before-write
5) Low current consumption
Active (5V) : 5mA (max.)
Standby (5V) : 3µA (max.)
6) Noise filter built into SK pin
7) Write protection when VCC is low
Inhibition on inadvertant write with the WC pin.
8) SOP8 / SSOP-B8 / MSOP8
9) High reliability CMOS process
10) 100,000 ERASE / WRITE cycles
11) 10 years Data Retention
1/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Block diagram
R / B
INSTRUCTION DECODE
CS
CONTROL
DETECT
SUPPLY
VOLTAGE
CLOCK GENERATION
HIGH
WRITE
DISABLE
VOLTAGE
WC
SK
GENERATOR
∗
9bit
ADD
ADD
∗
9bit
BUFFER
DECORDER
INSTRACTION
REGISTER
∗
DI
8,192 bit
EEPROM
DATA
R / W
16bit
REGISTER
AMPS
16bit
DO
∗ BR9016A is 10bit, 16,384bit
BR9080A is 9bit, 8,192bit
!Pin descriptions
VCC R / B WC GND
WC
GND DO
DI
VCC
GND
R / B WC
DI
DO
CS SK
DI
CS
SK
DO
R / B
V
CC
CS
SK
BR9080ARFVM
BR9016ARFVM
BR9080AF
BR9016AF
BR9080ARFV
BR9016ARFV
: MSOP8
: SOP8
: SSOP-B8
Fig.1
Pin No.
Pin name
Function
SOP
MSOP / SSOP
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
Chip Select Control
CS
SK
Serial Data Clock Input
Op code, address, Serial Data Input
Serial Data Output
Ground 0V
DI
DO
GND
Write Control Input
READY / BUSY Output
Power supply
WC
R / B
VCC
2/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Absolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Unit
V
Supply voltage
V
CC
−0.3∼+7.0
1
∗
2
∗
3
∗
450
SOP8
SSOP-B8
MSOP8
Power dissipation
Pd
300
310
mW
Storage temperature
Operation temperature
Input voltage
Tstg
Topr
−
−65∼+125
°C
°C
V
−40∼+85
−0.3∼VCC+0.3
∗
1 Reduced by 4.5mW for each increase in Ta of 1
∗2 Reduced by 3.0mW for each increase in Ta of 1
∗3 Reduced by 3.1mW for each increase in Ta of 1
°
°
°
C over 25
C over 25
C over 25
°C.
°C.
°C.
!Recommended operating conditions (Ta=25°C)
Min.
Parameter
Power supply voltage
Input voltage
Symbol
Typ.
Max.
5.5
Unit
2.7
2.7
0
−
−
−
V
V
V
WRITE
READ
V
CC
5.5
V
IN
V
CC
3/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Electrical characteristics
BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W : 5V
(Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼5.5V)
Parameter
Symbol Min. Typ.
Max.
Unit
Conditions
DI pin
V
IL1
IH1
IL2
IH2
OL
−
−
−
−
−
−
−
−
−
−
−
−
−
0.3×VCC
V
V
Input low level voltage 1
Input high level voltage 1
Input low level voltage 2
Input high level voltage 2
Output low level voltage
Output high level voltage
Input leak current
V
0.7×VCC
DI pin
−
0.2×VCC
−
V
V
CS, SK, WC pin
CS, SK, WC pin
−
0.8×VCC
0
V
V
V
V
0.4
I
I
OL=2.1mA
V
V
OH
VCC
V
CC−0.4
OH=−0.4mA
µA
1
I
LI
−1
−1
−
VIN=0V∼VCC
1
5
3
3
2
I
LO
µA
mA
mA
µA
V
OUT=0V∼VCC, CS=VCC
Output leak current
I
I
CC1
f
f
SK=2MHz tE / W=10ms (WRITE)
SK=2MHz (READ)
Operating current
CC2
−
Standby current
SK frequency
I
SB
SK
−
CS / SK / DI / WC=VCC DO, R / B=OPEN
MHz
−
f
−
BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W : 3V
(Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼3.3V)
Parameter
Symbol Min. Typ.
Max.
Unit
Conditions
DI pin
V
IL1
IH1
IL2
IH2
OL
−
−
−
−
−
−
−
−
−
−
−
−
−
0.3×VCC
V
V
Input low level voltage 1
Input high level voltage 1
Input low level voltage 2
Input high level voltage 2
Output low level voltage
Output high level voltage
Input leak current
V
0.7×VCC
DI pin
−
0.2×VCC
−
V
V
CS, SK, WC pin
CS, SK, WC pin
−
0.8×VCC
0
V
V
V
V
0.4
I
I
OL=100µA
V
VOH
VCC
V
CC−0.4
OH=−100µA
µA
1
I
LI
−1
−1
−
VIN=0V∼VCC
1
3
I
LO
µA
mA
mA
µA
VOUT=0V∼VCC, CS=VCC
Output leak current
I
I
CC1
f
f
SK=2MHz tE / W=10ms (WRITE)
SK=2MHz (READ)
Operating current
0.75
2
CC2
−
Standby current
SK frequency
I
SB
SK
−
CS / SK / DI / WC=VCC DO, R / B=OPEN
MHz
−
f
−
2
Not designed for radiation resistance
4/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Operating timing characteristics
BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W
(Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼5.5V)
Parameter
Symbol Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
f
CSS
100
100
100
100
−
−
−
CS setup time
t
CSH
−
−
CS hold time
Data setup time
−
−
t
DIS
DIH
PD1
PD0
Data hold time
−
−
t
DO rise delay time
−
150
150
10
−
t
t
DO fall delay time
−
−
Self-timing programming cycle
−
−
t
E / W
CS
SV
250
−
−
t
CS minimum high level time
−
150
150
−
t
READY / BUSY display valid time
Time when DO goes HIGH-Z (via CS)
Data clock high level time
Data clock low level time
0
−
t
OH
230
230
0
−
t
WH
−
−
t
WL
WCS
WCH
Write control setup time
−
−
t
t
0
−
−
Write control hold time
!Timing chart
Synchronous Data Input Output Timing
CS
t
CS
t
WH
t
CSS
tCSH
t
DIH
SK
t
WL
t
DIS
DI
t
PD
t
PD
tOH
DO
WC
Fig.2
· Input data are clocked in to DI at the rising edge of the clock (SK).
· Output data will toggle on the falling edge of the SK clock.
· The WC pin does not have any effect on the READ, EWEN and EWDS operations.
5/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Circuit operation
(1) Command mode
BR9080A
Instruction
Read (READ)
Start Bit
1010
Op Code
100 A0
010 A0
0011
Address
Data
A1 A2 A3 A4 A5 A6 A7 A8
A1 A2 A3 A4 A5 A6 A7 A8
D0 D1 − D14 D15
1010
Write (WRITE)
1010
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
Write enable (WEN)
Write disable (WDS)
1010
0000
∗ : Means either VIH or VIL
Address and data are transferred from LSB.
BR9016A
Instruction
Read (READ)
Start Bit
1010
Op Code
10 A0 A1
01 A0 A1
0011
Address
Data
A2 A3 A4 A5 A6 A7 A8 A9
A2 A3 A4 A5 A6 A7 A8 A9
D0 D1 − D14 D15
1010
Write (WRITE)
1010
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
Write enable (WEN)
Write disable (WDS)
1010
0000
∗ : Means either VIH or VIL
Address and data are transferred from LSB.
(2) Writing enabled / disabled
H
SK
1
4
8
12
16
L
ENABLE = 11
DISABLE = 00
H
CS
L
H
1
0
1
0
0
0
DI
L
HIGH-Z
DO
H
R / B
WC
High or LOW
Fig.3
1) When CS is “HIGH” during power up, BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W
comes up in the write disabled (WDS) state. In order to be programmable, it must receive a write enable (WEN)
instruction.
The device remains programmable until a disable (WDS) instruction is entered, or until it is powered down.
2) It is unnecessary to add the clock after 16th clock.
6/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
(3) Read cycle
BR9080AF-W / ARFV-W / ARFVM-W
H
SK
4
1
8
16
32
48
L
t
CS
H
CS
L
STANDBY
H
1
0
1
0
1
0
0
A1
A7
A8
A0
DI
L
HIGH-Z
HIGH-Z
D0
D15 D0
D15
DO
t
OH
H
Read Data (n)
Read Data (n+1)
R / B
WC
High or LOW
Fig.4 BR9080AF-W / ARFV-W / ARFVM-W
BR9016 AF-W / ARFV-W / ARFVM-W
H
SK
4
1
8
16
32
48
L
t
CS
H
CS
L
STANDBY
H
1
0
1
0
1
0
A0
A2
A8
A9
A1
DI
L
HIGH-Z
HIGH-Z
D0
D15 D0
D15
DO
t
OH
H
Read Data (n)
Read Data (n+1)
R / B
WC
High or LOW
Fig.5 BR9016AF-W / ARFV-W / ARFVM-W
1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the
SK signal.
(DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal.
During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost.
See the synchronized data input / output timing chart in Fig.2.)
2) The data stored in the next address is clocked out of the device on the falling edge of 32nd clock. The data stored in
the upper address every 16 clocks is output sequentially by the continual SK input. Also the read operation is reset by
CS High.
7/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
(4) Write cycle
BR9080AF-W / ARFV-W / ARFVM-W
H
SK
1
4
8
16
32
L
H
CS
L
t
CS
H
1
0
1
0
0
1
0
A0
A1
A7
A8
D0
D15
DI
L
HIGH-Z
HIGH-Z
DO
t
SV
tE-W
H
R / B
WC
t
WCS
t
WCH
Fig.6 BR9080AF-W / ARFV-W / ARFVM-W
BR9016 AF-W / ARFV-W / ARFVM-W
H
SK
1
4
8
16
32
L
H
CS
L
t
CS
H
1
0
1
0
0
1
A0
A1
A2
A8
A9
D0
D15
DI
L
HIGH-Z
HIGH-Z
DO
t
SV
tE-W
H
R / B
WC
t
WCS
t
WCH
Fig.7 BR9016AF-W / ARFV-W / ARFVM-W
1) At the rising edge of 32nd clock, R / B pin will be come out “LOW” after the specified time delay (tSV).
2) From above edge R / B will indicate the ready / busy status of the chip: “LOW” indicated programming is all in
progress: “HIGH” indicates the write cycle is complete and this part is ready for another instruction.
3) During the input of Write command, CS must be “LOW”. However, once the write operation started, CS could be either
“HIGH” or “LOW”.
4) If WC becomes “HIGH” during Write Cycle, the write operation is halted. In this case, the address data in writing is no
guaranteed. It is necessary to rewrite it.
8/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
(5) READY / BUSY display
(R / B pin and DO pin: BR9080AF-W / ARFV-W / ARFVM-W, BR9016AF-W / ARFV-W / ARFVM-W)
1) This display outputs the internal status signal; the R / B pin outputs the HIGH or LOW status at all times. The display
can also be output from the DO pin. Following completion of the writing command, if CS falls while SK is LOW, either
HIGH or LOW is output. (The display can also be output without using the R / B pin, leaving it open.)
2) When writing data to a memory cell, the READY / BUSY display is output from the rise of the 32nd clock pulse of the
SK signal after tSV, from the R / B pin.
R / B display = LOW: writing in progress
(The internal timer circuit is activated, and after the tE / W timing has been created, the timer circuit stops automatically.
Writing of data to the memory cell is done during the tE / W timing, during which time other commands cannot be
received.)
R / B display = HIGH: command standby state
(Writing of data to the memory cell has been completed and the next command can be received.)
CS
SK
Clock
DI
Write command
t
PD
tOH
HIGH-Z
HIGH-Z
READY
READY
DO
BUSY
BUSY
R / B
READY
Fig.8 R / B Status Output timing chart
1) DO will output R / B status after CS is held low during SK=L, until CS is held high.
Note : The document may be strategic technical data subject to COCOM regulations.
9/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!Operation notes
(1) Turning the power supply on and off
1) When the power supply is turned on and off, CS should be set to HIGH (=VCC).
2) When CS is LOW, the command input reception state (active) is entered. If the power supply is turned on in this state,
erroneous operations and erroneous writing can occur because of noise and other factors. To avoid this, make sure
CS is set to HIGH (=VCC) before turning on the power supply.
(Good example) Here, the CS pin is pulled up to VCC.
When turning off the power supply, wait at least 10msec before turning it on again. Failing to
observe this condition can result in the internal circuit failing to be reset when the power supply is
turned on.
(Bad example) CS is LOW when the power supply is turned on or off.
In this case, because CS remains LOW, the EEPROM may perform erroneous operations or
write erroneous data because of noise or other factors.
* Please be aware that the case shown in this example can also occur if CS input is HIGH-Z.
VCC
VCC
GND
VCC
CS
GND
Good example
Bad example
Fig.9
(2) Noise countermeasures
1) SK noise
If noise occurs at the rise of the SK clock input, the clock is assumed to be excessive, and this can cause malfunction
because the bits are out of alignment.
2) WC noise
During a writing operation, noise at the WC pin can be erroneously judged to be data, and this can cause writing to be
forcibly interrupted.
3) VCC noise
Noise and surges on the power supply line can cause malfunction. We recommend installing a bypass capacitor
between the power supply and ground to eliminate this problem.
10/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
(3) Canceling modes
1) Read commands
32 Clock
SK
CS
DI
Start bit
4 bits
Operating code
4 bits
Address
8 bits
16 bits
DO
Data
D15
DO
Cancel can be performed for the entire read mode space
WC
HIGH or LOW
Fig.10
Cancellation method: CS HIGH
2) Write commands
32 Clock
SK
CS
DI
DO
D15
Start bit
Operating code
4 bits
Address
8 bits
Data
16 bits
4 bits
tE / W
R / B
a
b
c
d
WC
Fig.11
Canceling methods
a : Canceled by setting CS HIGH. The WC pin is not involved.
b : If the WC pin goes HIGH for even a second, writing is forcibly interrupted. Cancellation occurs even if the CS pin is
HIGH. At this point, data has not been written to the memory, so the data in the designated address has not yet
been changed.
c : The operation is forcibly canceled by setting the WC pin to HIGH or turning off the power supply (although we do
not recommend using this method). The data in the designated address is not guaranteed and should be written
once again.
d : If CS is set to HIGH while the R / B signal is HIGH (following the tE / W timing), the IC is reset internally, and waits
for the next command to be input.
11/12
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
Memory ICs
!External dimension (Units : mm)
BR9080ARFVM-W
BR9016ARFVM-W
BR9080AF
BR9016AF
5.0 ± 0.2
2.9 0.1
8
5
8
5
1
4
1
4
0.145+−00..0035
0.475
0.22+−00..0054
0.08
1.27 0.4 ± 0.1
0.3Min.
M
0.65
0.08 S
0.15
MSOP8
SOP8
BR9080ARFV
BR9016ARFV
3.0 0.2
8
5
1
4
0.22 0.1
0.65
0.3Min.
(0.52)
0.1
SSOP-B8
12/12
相关型号：
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