BR9040RFVM-WTR [ROHM]
EEPROM, 256X16, Serial, CMOS, PDSO8;
| 型号： | BR9040RFVM-WTR |
| 厂家： | 
ROHM |
| 描述： | EEPROM, 256X16, Serial, CMOS, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC
RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
1k, 2k, 4k, bit EEPROMs for direct
connection to serial ports
BR9010-W / BR9010F-W / BR9010FV-W /
BR9010RFV-W / BR9010RFVM-W
BR9020-W / BR9020F-W / BR9020FV-W /
BR9020RFV-W / BR9020RFVM-W
BR9040-W / BR9040F-W / BR9040FV-W /
BR9040RFV-W / BR9040RFVM-W
The BR90XX series are serial EEPROMs that can be connected directly to a serial port and can be erased and written
electrically. Writing and reading is perfomed in word units, using four types of operation commands. Communication
occurs through CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling these
EEPROMs to be used as one-time ROMs. During writing operation is checked via the internal status check.
zApplication
General-Purpose
zFeatures
1) BR9010-W / F-W / FV-W / RFV-W / RFVM-W (1k bit) : 64 words×16bit
BR9020-W / F-W / FV-W / RFV-W / RFVM-W (2k bit) : 128words×16bit
BR9040-W / F-W / FV-W / RFV-W / RFVM-W (4k bit) : 256words×16bit
2) Single power supply.
3) Serial data I/O.
4) Self-timed programming cycle with auto-erase.
5) Low supply current.
Active (5V) : 2mA (max.)
Standby (5V) : 3µA (max.) (CMOS INPUT)
6) Noise filter on the SK pin. Write protection when the supply is low.
7) Write protection by WC pin.
8) Space Saving DIP8/SOP8/SSOP-B8/MSOP8pin Packages.
9) 100,000 erase/ write cycles endurance.
10) Provide 10 years of date retention.
11) Easy connection to serial port.
12) “FFFFh” stored in all address on shipped.
1/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC
RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
zBlock diagram
R / B
CS
Command decode
Power supply
voltage detector
Control
Clock generation
High voltage
generator
WC
Write disable
SK
6bitBR9010
7bitBR9020
8bitBR9040
6bitBR9010
7bitBR9020
8bitBR9040
Address
buffer
Address
decoder
1,024bit BR9010
2,048bit BR9020
4,096bit BR9040
Command
register
DI
EEPROM
array
Data
R / W
16bit
register
amplifier
16bit
DO
zTerminal Function
Pin No.
Pin name
Function
BR90xxF-W/FV-W
BR90xx-W/RFV-W/RFVM-W
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
Chip Select Input
CS
SK
Serial Date Clock Input
Serial Date Input (Op code, address)
Serial Date Output
DI
DO
GND
Ground (0V)
Write Control Input
WC
READY/ BUSY Status Output
Power Supply
R / B
V
CC
2/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
zAbsolute Maximum Ratings (Ta=25°C)
Parameter
Supply Voltage
Symbol
Limits
Unit
V
V
CC
−0.3 +7.0
BR9010-W,
BR9020-W,
BR9040-W
1
2
3
4
800
DIP8
SOP8
BR9010F-W,
BR9020F-W,
BR9040F-W
450
300
310
Power
Pd
mW
BR9010FV-W, BR9010RFV-W,
BR9020FV-W, BR9020RFV-W,
BR9040FV-W, BR9040RFV-W
dissipation
SSOP-B8
MSOP8
BR9010RFVM-W,
BR9020RFVM-W,
BR9040RFVM-W
Storage Temperature
Operating Temperature
Terminal Voltage
−65 +125
Tstg
Topr
−
°C
°C
V
−40 +85
−0.3 VCC+0.3
1 Degradation is done at 8.0mW/
2 Degradation is done at 4.5mW/
3 Degradation is done at 3.0mW/
4 Degradation is done at 3.1mW/
˚
˚
˚
˚
C for operation above Ta=25
C for operation above Ta=25
C for operation above Ta=25
C for operation above Ta=25
˚C
˚C
˚C
˚C
zRecommended Operating Condition (Ta=25°C)
Parameter
Symbol
Min.
2.7
2.0
0
Typ.
Max.
5.5
Unit
V
−
−
−
Write
Read
Supply voltage
Input voltage
VCC
5.5
V
V
IN
VCC
V
3/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
zElectrical Characteristics
Unless otherwise specified ( Ta=−40~+85°C, V
CC=
2.7V~5.5V)
Symbol
Min.
Typ.
Max.
Unit
V
Conditions
Parameter
V
IL1
IH1
IL2
IH2
OL
−
0.7×VCC
−
−
−
−
−
−
−
−
−
−
−
−
−
0.3×VCC
DI pin
Input LOW Voltage 1
Input HIGH Voltage 1
Input LOW Voltage 2
Input HIGH Voltage 2
Output LOW Voltage
Output HIGH Voltage
Input Leakage Current
Output Leakage Current
V
−
0.2×VCC
−
V
DI pin
V
V
CS, SK, WC pin
CS, SK, WC pin
V
0.8×VCC
0
V
V
0.4
V
I
I
OL=2.1mA
V
OH
V
CC−0.4
VCC
V
OH=−0.4mA
I
LI
−1
−1
−
1
µA
µA
mA
mA
µA
MHz
V
V
IN=0V VCC
OUT=0V VCC, CS=VCC
I
LO
1
2
1
3
2
I
I
CC1
CC2
f
f
SK=2MHz, tE / W=10ms (WRITE)
SK=2MHz (READ)
Operating Current
−
I
SB
SK
−
CS, SK, DI, WC=VCC, DO, R / B=OPEN
Standby Current
Clock Frequency
f
−
−
CC=
Unless otherwise specified ( Ta=−40~+85°C, V
2.7V~3.3V)
Symbol
Min.
Typ.
Max.
Unit
V
Conditions
DI pin
Parameter
Input LOW Voltage 1
Input HIGH Voltage 1
Input LOW Voltage 2
Input HIGH Voltage 2
Output LOW Voltage
Output HIGH Voltage
Input Leakage Current
Output Leakage Current
V
IL1
IH1
IL2
IH2
OL
−
0.7×VCC
−
−
−
−
−
−
−
−
−
−
−
−
−
0.3×VCC
V
−
0.2×VCC
−
V
DI pin
V
V
CS, SK, WC pin
CS, SK, WC pin
V
0.8×VCC
0
V
V
0.4
V
I
I
OL=100µA
V
OH
V
CC−0.4
VCC
V
OH=−100µA
I
LI
−1
−1
−
1
µA
µA
mA
mA
µA
MHz
V
V
IN=0V VCC
I
LO
1
1.5
0.5
2
OUT=0V VCC, CS=VCC
I
I
CC1
f
f
SK=2MHz, tE / W=10ms (WRITE)
SK=2MHz (READ)
Operating Current
CC2
−
Standby Current
Clock Frequency
I
SB
SK
−
CS, SK, DI, WC=VCC, DO, R / B=OPEN
f
−
2
−
4/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
zAC Operation Characteristics
CC=
( Ta=−40~+85°C, V
2.7~5.5V)
Parameter
Chip Select Setup Time
Symbol Min.
Typ.
−
Max.
−
Unit
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
t
CSS
100
100
100
100
−
Chip Select Hold Time
t
CSH
−
−
Data In Setup Time
t
DIS
DIH
PD1
PD0
−
−
Data In Hold Time
t
−
−
Delay to Output High
t
t
−
150
150
10
−
Delay to Output Low
−
−
Self-Timed Program Cycle
Minimum Chip Select High Time
Data Output Disable Time( From CS)
Clock High Time
t
E / W
−
−
t
CS
250
0
−
t
OH
−
150
−
t
WH
230
230
0
−
Clock Low Time
t
WL
WCS
WCH
SV
−
−
Write Control Setup Time
Write Control Hold Time
Clock High to Output READY/BUSY Status
t
−
−
t
0
−
−
t
−
−
150
5/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC
RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
z I / O Circuit
(1) Input Circuit
CS int.
RESET int.
SK
CS
CS int.
WC
DI
(2) Output Circuit
DO
OE int.
R/B
6/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
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zOperating
(1) Instruction Code
Instruction
Start Bit
1010
Op Code
1000
Address
Data
A0 A1 A2 A3 A4 A5 (A6) 2 (A7) 1
A0 A1 A2 A3 A4 A5 (A6) 2 (A7) 1
READ
D0 D1−D14 D15 (READ DATA)
D0 D1−D14 D15 (WRITE DATA)
1010
0100
WRITE
1010
0011
Write Enable (WEN)
Write Disable (WDS)
1010
0000
Address and data must be transferred from LSB.
Means either VIH or VIL
BR9020-W/F-W/FV-W/RFV-W/RFVM-W
BR9010-W/F-W/FV-W/RFV-W/RFVM-W
1= "0"
1, 2= "0"
Synchronous Data Input Output Timing
CS
t
CS
t
WH
t
CSS
tCSH
t
DIH
SK
t
WL
t
DIS
DI
t
PD
t
PD
tOH
DO
WC
Fig.1
Input Data is clocked into the DI pin on the rising edge of the clock SK
Output data is clocked out on the falling edge of the SK clock.
The WC pin does not have any affect on the READ, WEN and WDS operations.
Between instructions, CS must be brought High for greater than the minimum of
tCS. If CS is maintained Low, the next instruction isn't detected.
7/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
(2) WRITE Enable / Disable
H
SK
CS
1
4
8
12
16
L
ENABLE = 11
DISABLE = 00
H
L
H
L
1
0
1
0
0
0
DI
High-Z
DO
H
R / B
WC
HIGH or LOW
Fig.2
1) When power is first applied, the device has been held in a reset status, with respect to the write enable, in the same
way the write disable (WDS) instruction is executed. Before the write instruction is executed, the device must be
received the write enable (WEN) instruction. Once the device is done, the device remains programmable until the
write disable (WDS) instruction is executed or the supply is removed from the device.
2) It is unnecessary to add the clock after 16th clock. If the device is recieved the clock, the device ignores the clock.
3) As both of the enable and disable instructions don’t depend on the status of the WC pin, the state of WC isn’t cared
during the instruction.
4) The instruction is recognized after the rising edge of 8 th clock for the address following 8 clocks for the opcode, but
the specified address isn’t cared during the instructions.
8/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
(3) Read Cycle
H
L
SK
4
1
8
16
32
t
CS
H
CS
L
H
L
STANDBY
1
0
1
0
1
0
0
0
A0
A5
0
0
DI
HIGH-Z
HIGH-Z
D0
D15 D0
D15
DO
t
OH
H
Read Data (n)
Read Data (n+1)
R / B
WC
HIGH or LOW
Fig.3 BR9010-W / F--W / FV-W / RFV-W / RFVM-W
H
SK
4
1
8
16
32
48
L
t
CS
H
CS
L
H
L
STANDBY
1
0
1
0
1
0
0
0
A0
A6
0
DI
HIGH-Z
HIGH-Z
D0
D15 D0
D15
DO
t
OH
H
Read Data (n)
Read Data (n+1)
R / B
WC
HIGH or LOW
Fig.4 BR9020-W / F-W / FV-W / RFV-W / RFVM-W
H
SK
CS
4
1
8
16
32
L
t
CS
H
L
H
L
STANDBY
HIGH-Z
1
0
1
0
1
0
0
0
A0
A6
A7
DI
HIGH-Z
D0
D15 D0
D15
DO
t
OH
H
Read Data (n)
Read Data (n+1)
R / B
WC
HIGH or LOW
Fig.5 BR9040-W / F-W / FV-W / RFV-W / RFVM-W
1) On the falling edge of 16 th clock, the data stored in the specified address (n) is clocked out of the DO pin.
PDO
PD1
PD0
PD1,
The Output DO is toggled after the internal propagation t ort on the falling edge of SK. During t or t the data
PD
is the previous data or unstable, and to take in the data, t is needed. (Refer to Fig.1 Synchronous data input output
timing.)
2) The data stored in the next address is clocked out of the device on the falling edge of 32nd clock. The data stored in
the upper address every 16 clocks is output sequentially by the continual SK input. Also the read operation is reset by
CS High.
9/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
(4) Write Cycle
H
L
SK
1
4
8
16
32
H
L
CS
DI
t
CS
H
L
1
0
1
0
0
1
0
0
A0
A5
0
0
D0
D15
High-Z
High-Z
DO
t
E/W
t
SV
H
R / B
WC
H
L
t
WCS
t
WCH
Fig.6 BR9010-W / F-W / FV-W / RFV-W / RFVM-W
H
L
SK
1
4
8
16
32
H
L
CS
DI
t
CS
H
L
1
0
1
0
0
1
0
0
A0
A6
0
D0
D15
High-Z
High-Z
DO
t
E/W
t
SV
H
R / B
WC
H
L
t
WCS
t
WCH
Fig.7 BR9020-W / F-W / FV-W / RFV-W / RFVM-W
H
L
SK
1
4
8
16
32
H
L
CS
DI
t
CS
H
L
1
0
1
0
0
1
0
0
A0
A6
A7
D0
D15
High-Z
High-Z
DO
t
E/W
t
SV
H
R / B
WC
H
L
t
WCS
t
WCH
Fig.8 BR9040-W / F-W / FV-W / RFV-W / RFVM-W
10/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC
RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
1) During the write instruction , CS must be brought Low. However once the write operation started, CS may be either
High or Low. But in the case of connecting the WC pin to the CS pin. CS and WC must be brought Low during
programming cycle.(If the WC pin is brought High during the write cycle, the write operation is halted. In that case, the
data of the specified address is not guaranteed. It is necessary to rewrite it.)
2) After the R / B pin changed Busy to Ready, once CS is brought High, then CS keep Low ,which means the status of
being able to accept an instruction. The device can take in the input from SK and DI, but in the case of keeping CS
Low without being brought High once, the input is canceled until being CS High once.
3) At the rising edge of 32 nd clock, the R / B pin will be driven Low after the specified time delay (tSV).
4) During programming, R / B is tied to Low by the device (On the rising edge of SK taken in the last data (D15), internal
timer starts and automatically finished after the data of memory cell is written spending tE / W. SK could be either High
or Low at the time.
5) After input write instruction, also the DO pin will be able to show the status of R / B, in the case that CS is falling from
High to Low while SK is tied to Low. (Refer to READY / BUSY STATUS in the next page.)
(5) READY / BUSY STATUS (on the R / B pin, the DO pin)
1)The DO pin outputs the READY / BUSY status of the internal part, which shows whether the device is ready to receive
the next instruction or not. (High or Low)
After the write instruction is completed, if CS is brought from high to low while SK is Low, the DO pin outputs the
internal status. (The R / B pin may be no connection.
2) When written to the memory cell, R / B status is output after tSV spent from the rising edge of 32 th clock on SK.
R / B =Low : under writing
After spending tE / W operating the internal timer, the device automatically finishes writing.
During tE / W, the memory array is accessed and any instruction is not received.
R / B=High : ready
Auto programming has been completed. The device is ready to receive the next Instruction.
SK
CLOCK
CS
DI
WRITE INSTRUCTION
t
PD
tOH
HIGH-Z
HIGH-Z
READY
READY
DO
BUSY
R / B
READY
BUSY
Fig.9 R / B Status Output Timing
11/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
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(6) About the direct connection between the DI and DO pins
The device can be used with the DI pin connected to the DO pin directly.
But when the READY / BUSY status is output, be careful about the bus conflict on the port of the controller.
zAttention to Use
(1) Power ON / OFF
1) The CS is brought High during power–up and power–down.
2) This device is in active state while CS is Low.
3) The extraordinary function or data collapse may occur in that condition because of noise etc, if power–up and power–
down is done with CS brought Low.
In order to prevent above errors from happening, keep CS High during power-up and power-down.
(Good example) CS is brought High during power–up and power-down.
Please take more than 10ms between power–up and power-off, or the internal circuit is not always
reset.
(Bad example) CS is brought Low during power–up and power-down.
The CS pin is always Low in this case, the noise may force the device to make malfunction or
inadvertent write.
It sometimes occurs in the case that the CS pin is Hi-Z.
VCC
VCC
GND
VCC
CS
GND
Good
Bad
Fig.10
(2) Noise Rejection
1) SK NOISE
If SK line has a lot of noise for rising time of SK, the device may recognize the noise as a clock and then clock will be
shifted.
2) WC NOISE
If WC line has noise during write cycle (tE / W), there may be a chance to deny the programming.
3) VCC NOISE
It recommended that capacitor is put between VCC and GND to prevent these case, since it is possible to occur
malfunction by the effect of noise or surge on power line.
12/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
(3) Instruction Mode Cancel
1) Read instruction
32 clocks
SK
CS
DI
START BIT
4 bit
OPCODE
4 bit
ADDRESS
8 bit
16 bit
DO
DATA
D15
DO
It is possible to be canceled for any timing.
WC
HIGH or LOW
Fig.11
How to cancel : CS is brought High.
2) Write instruction
32 clocks
SK
CS
DI
DO
D15
START BIT OPECODE ADDRESS
4 bit 4 bit 8 bit
DATA
16 bit
tE / W
R / B
WC
a
b
c
d
Fig.12
How to cancel
a：CS is brought High to cancel the instruction, and WC may be either High or Low.
b：In case that WC is brought High for a moment, or CS is brought High, the write instruction is canceled, the data of the
specified address is not changed.
c：When WC is brought High, or the device is powered down (But the latter way is not recommended), the instruction is
canceled but the specified data is not guaranteed. Send the instruction again.
d：When CS is brought High during R/B High, the device is reset and ready to receive a next instruction.
NOTE : The document may be strategic technical data subject to COCOM regulations.
13/14
BR9010-W / F-W / FV-W / RFV-W / RFVM-W / BR9020-W / F-W / FV-W /
Memory IC RFV-W / RFVM-W / BR9040-W / F-W / FV-W / RFV-W / RFVM-W
zExternal dimensions (Units : mm)
BR9010-W, BR9020-W, BR9040-W
BR9010FV-W, BR9010RFV-W
BR9020FV-W, BR9020RFV-W
BR9040FV-W, BR9040RFV-W
9.3±0.3
8
5
4
3.0±0.2
8
5
1
1
4
0.15±0.1
7.62
0.1
0.22±0.1
(0.52) 0.65
2.54
0.5±
0.1
0° ~ 15°
DIP8
SSOP-B8
BR9010F-W, BR9020F-W, BR9040F-W
BR9010RFVM-W, BR9020RFVM-W, BR9040RFVM-W
2.9±0.1
5.0±0.2
8
5
8
5
1
4
0.145+−00..0035
0.475
1
4
0.15±0.1
0.1
0.22+−00..0054
0.08
M
1.27
0.65
0.08 S
0.4±0.1
SOP8
MSOP8
14/14
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