BR25H320-WC [ROHM]
125C Operating tempter; 125C操作试探型号: | BR25H320-WC |
厂家: | ROHM |
描述: | 125C Operating tempter |
文件: | 总20页 (文件大小:491K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Automotive Series Serial EEPROM
125℃ Operating tempter
SPI BUS BR25□□□□Family
No.09001ECT01
BR25H□□□-WC series
●Description
BR25H□□□-WC series is a serial EEPROM of SPI BUS interface method.
●Features
1) High speed clock action up to 5MHz (Max.)
2) Wait function by HOLDB terminal.
3) Part or whole of memory arrays settable as read only memory area by program.
4) 2.5~5.5V single power source action most suitable for battery use.
5) Page write mode useful for initial value write at factory shipment.
6) Highly reliable connection by Au pad and Au wire.
7) For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
8) Auto erase and auto end function at data rewrite.
9) Low current consumption
At write action (5V)
At read action (5V)
: 1.5mA (Typ.)
: 1.0mA (Typ.)
At standby action (5V) : 0.1μA (Typ.)
10) Address auto increment function at read action
11) Write mistake prevention function
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage.
12) SOP8, SOP-J8, TSSOP-B8 Package
13) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
14) Data kept for 40 years.
15) Data rewrite up to 1,000,000times.
●Page write
Number of pages
16 Byte
32 Byte
BR25H080-WC
BR25H160-WC
BR25H320-WC
BR25H010-WC
BR25H020-WC
BR25H040-WC
Product number
●BR25H series
Capacity
1Kbit
Bit format
128×8
256×8
512×8
1K×8
Type
Power source voltage
2.5~5.5V
SOP8
●
SOP-J8
●
TSSOP-B8
BR25H010-WC
2Kbit
BR25H020-WC
BR25H040-WC
BR25H080-WC
BR25H160-WC
BR25H320-WC
2.5~5.5V
●
●
4Kbit
2.5~5.5V
●
●
8Kbit
2.5~5.5V
●
●
●
●
16Kbit
32Kbit
2K×8
2.5~5.5V
●
●
4Kx8
2.5~5.5V
●
●
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2009.08 - Rev.C
1/19
© 2009 ROHM Co., Ltd. All rights reserved.
Technical Note
BR25H□□□-WC series
●Absolute maximum ratings (Ta=25°C)
Parameter
Symbol
VCC
Limits
-0.3~+6.5
Unit
V
Impressed voltage
560(SOP8) *1
560(SOP-J8) *2
410(TSSOP-B8) *3
-65~+150
Permissible
dissipation
Pd
mW
Storage temperature range
Operating temperature range
Terminal voltage
Tstg
Topr
-
°C
°C
V
-40~+125
-0.3~VCC+0.3
・When using at Ta=25℃ or higher, 4.5mW (*1,*2), 3.3mW(*3) to be reduced per 1℃
●Memory cell characteristics (VCC=2.5V~5.5V)
Limits
Parameter
Unit
Condition
Min.
1,000,000
500,000
300,000
40
Typ.
Max.
-
-
-
-
-
-
-
-
-
-
Times
Times
Times
Years
Years
Ta≤85°C
Ta≤105°C
Ta≤125°C
Ta≤25°C
Ta≤85°C
*1
Number of data rewrite times
Data hold years*1
20
*1:Not 100% TESTED
●Recommended action conditions
Parameter
Symbol
VCC
Vin
Limits
2.5~5.5
0~VCC
Unit
V
Power source voltage
Input voltage
●Input / output capacity (Ta=25°C, frequency=5MHz)
Parameter
Input capacity*1
Symbol
CIN
Conditions
VIN=GND
Min
Max
8
Unit
pF
-
-
Output capacity*1
COUT
VOUT=GND
8
*1: Not 100% TESTED
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
2/19
Technical Note
BR25H□□□-WC series
●Electrical characteristics (Unless otherwise specified, Ta=-40~+125°C, VCC=2.5~5.5V)
Limits
Parameter
Symbol
VIH 0.7xVCC
Unit Conditions
Min.
Typ.
Max.
VCC
+0.3
“H” input voltage
“L” input voltage
“L” output voltage
“H” output voltage
Input leak current
Output leak current
-
V
V
V
V
2.5≦VCC≦5.5V
0.3x
VCC
VIL
-0.3
0
-
-
-
-
-
2.5≦VCC≦5.5V
IOL=2.1mA
VOL
0.4
VCC
10
VOH VCC-0.5
IOH=-0.4mA
ILI
-10
-10
μA VIN=0~VCC
ILO
10
μA VOUT=0~VCC, CSB=VCC
VCC=2.5V,fSCK=5MHz, tE/W=5ms
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write Write status register
VCC=5.5V,fSCK=5MHz, tE/W=5ms
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write Write status register
VCC=2.5V,fSCK=5MHz
ICC1
ICC2
ICC3
-
-
-
-
-
-
2.0
3.0
1.5
Current consumption
at write action
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
Current consumption
at read action
VCC=5.5V,fSCK=5MHz
ICC4
ISB
-
-
-
-
2.0
10
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V
Standby current
μA
CSB=HOLDB=WPB=VCC, SCK=SI=VCC or =GND, SO=OPEN
*Radiation resistance design is not made
●Block diagram
VOLTAGE
DETECTION
CSB
SCK
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
HIGH VOLTAGE
WRITE
INHIBITION
GENERATOR
*1 7bit: BR25H010-WC
SI
INSTRUCTION
REGISTER
8bit: BR25H020-WC
9bit: BR25H040-WC
STATUS REGISTER
10bit: BR25H080-WC
11bit: BR25H160-WC
12bit: BR25H320-WC
ADDRESS
HOLDB
ADDRESS
7~12bit *1
7~12bit *1
REGISTER
DECODER
1~32K
EEPROM
DATA
READ/WRITE
AMP
WPB
SO
8bit
8bit
REGISTER
Fig.1 Block diagram
●Pin assignment and description
Terminal name
Input/Output
Function
Vcc
HOLDB SCK
SI
VCC
GND
CSB
SCK
SI
-
Power source to be connected
All input / output reference voltage, 0V
Chip select input
-
Input
Input
Input
Output
BR25H010-WC
BR25H020-WC
BR25H040-WC
BR25H080-WC
BR25H160-WC
BR25H320-WC
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output
SO
Hold input
HOLDB
Input
Input
Command communications may be suspended
temporarily (HOLD status)
CSB
SO
WPB
GND
Write protect input
WPB
Write command is prohibited *1
Write status register command is prohibited.
Fig.2 Pin assignment diagram
*1:BR25H010/020/040-WC
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2009.08 - Rev.C
3/19
© 2009 ROHM Co., Ltd. All rights reserved.
Technical Note
BR25H□□□-WC series
●Operating timing characteristics
●Sync data input / output timing
(Ta=-40~+125°C, unless otherwise specified, load capacity CL1=100pF)
tCSS
tCS
CSB
SCK
2.5≤VCC≤5.5V
tSCKS
tRC
tFC
tSCKWH
tSCKWL
tDIS
Parameter
Symbol
Unit
Min. Typ. Max.
tDIH
SCK frequency
SCK high time
SCK low time
fSCK
tSCKWH
tSCKWL
tCS
-
-
-
-
-
-
-
-
-
-
-
-
5
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SI
85
85
85
90
85
90
90
20
30
-
High-Z
SO
-
Fig.3 Input timing
CSB high time
CSB setup time
CSB hold time
SCK setup time
SCK hold time
SI setup time
-
SI is taken into IC inside in sync with data rise
edge of SCK. Input address and data from the
most significant bit MSB.
tCSS
-
tCSH
-
tSCKS
tSCKH
tDIS
-
tCS
-
tSCKH
CSB
tCSH
-
SCK
SI
SI hold time
tDIH
-
tPD
tRO,tFO
tOZ
tOH
High-Z
Data output delay time1
tPD1
70
SO
Data output delay time2
(CL2=30pF)
tPD2
-
-
55
ns
Fig.4 Input / Output timing
Output hold time
tOH
tOZ
0
-
-
-
-
ns
ns
SO is output in sync with data fall edge of SCK.
Data is output from the most significant bit MSB.
Output disable time
100
HOLDB setting
setup time
HOLDB setting
hold time
HOLDB release
setup time
HOLDB release
hold time
Time from HOLDB
to output High-Z
Time from HOLDB
To output change
SCK rise time*1
SCK fall time*1
tHFS
tHFH
tHRS
tHRH
tHOZ
tHPD
0
40
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CSB "H"
"L"
-
tHFS tHFH
tHRS tHRH
SCK
SI
70
-
-
tDIS
n
n+1
n-1
tHOZ
Dn
tHPD
100
70
High-Z
SO
Dn+1
Dn
Dn-1
-
HOLDB
tRC
tFC
-
-
-
-
-
-
-
-
-
-
1
1
μs
μs
ns
ns
ms
Fig.5 HOLD timing
OUTPUT rise time*1
OUTPUT fall time*1
tRO
tFO
tE/W
50
50
5
Write time
*1 NOT 100% TESTED
●AC measurement conditions
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Load capacity 1
Load capacity 2
Input rise time
CL1
-
-
-
-
-
100
30
pF
pF
ns
ns
V
CL2
-
-
-
-
-
-
50
Input fall time
-
50
Input voltage
0.2VCC/0.8VCC
0.3VCC/0.7VCC
Input / Output judgment voltage
V
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2009.08 - Rev.C
4/19
© 2009 ROHM Co., Ltd. All rights reserved.
Technical Note
BR25H□□□-WC series
●Characteristic data (The following characteristic data are Typ. Value.)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
SPEC
4
0
1
2
3
Vcc[V]
Fig.6 "H" input voltage VIH(CSB,SCK,SI,HOLDB,WPB)
4
5
6
0
1
2
3
5
6
0
1
2
3
4
5
6
IOL[mA]
Vcc[V]
Fig.7 ꢀ"L" input voltageꢀVIL(CSB,SCK,SI,HOLDB,WPB)
Fig.8ꢀ"L" output voltageꢀVOL-IOL(Vcc=2.5V)
ꢀ
ꢀ
12
10
8
12
2.6
2.5
2.4
2.3
2.2
2.1
2
SPEC
SPEC
10
8
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
6
6
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
4
4
2
2
1.9
1.8
0
0
0
0.4
0.8
1.2
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
VOUT[V]
IOH[mA]
Fig.11ꢀOutput leak current ILO(SO)(Vcc=5.5V)
Fig.10ꢀInput leak current ILI(CSB,SCK,SI,HOLDB,WPB)
Fig.9ꢀ"H" output voltage VOH-IOH(Vcc=2.5V)
12
10
8
4
3
2
1
0
2.5
2
fSCK=5MHz
DATA=AAh
fSCK=5MHz
SPEC
SPEC
SPEC
DATA=00h
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
1.5
1
SPEC
6
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
4
0.5
0
2
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.12ꢀCurrent consumption at WRITE operation
Fig.14ꢀConsumption current at standby operation ISB
Fig.13ꢀConsumption Current at READ operation
ICC1,2
ICC3,4
100
100
80
60
40
20
0
100
80
60
40
20
0
SPEC
SPEC
10
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
1
0.1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.15ꢀSCK frequency fSCK
Fig.16 SCK high timeꢀtSCKWH
Fig.17 SCK low timeꢀtSCKWL
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
SPEC
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.19ꢀCSB setup timeꢀtCSS
Fig.20ꢀCSB hold timeꢀtCSH
Fig.18 CSB high timeꢀtCS
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
5/19
Technical Note
BR25H□□□-WC series
●Characteristic data (The following characteristic data are Typ. Value.)
50
100
80
60
40
20
0
30
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
40
30
20
10
0
SPEC
20
10
SPEC
SPEC
0
Ta=-40℃
Ta=25℃
Ta=125℃
-10
-20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Fig.21ꢀSI setup timeꢀtDIS
Vcc[V]
Fig.22ꢀSI hold timeꢀtDIH
Fig.23ꢀData output delay timeꢀtPD1(CL=100pF)
80
120
100
80
60
40
20
0
100
80
60
40
20
0
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
60
40
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
20
0
-20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.25ꢀOutput disable time tOZ
Fig.26ꢀHOLDB setting hold time tHFH
Fig.24ꢀData output delay time tPD2(CL-30pF)
120
100
80
60
40
20
0
80
60
40
20
0
80
60
40
20
0
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
-20
-20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.27ꢀHOLDB release hold time tHRH
Fig.28ꢀTime from HOLDB to output High-Z tHOZ
Fig.29ꢀTime from HOLDB to output change tHPD
100
80
60
40
20
0
100
80
60
40
20
0
8
6
4
2
0
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
SPEC
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.32 Write cycle time tE/W
Fig.31 Output fall time tFO
Fig.30 Output rise time tRO
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
6/19
Technical Note
BR25H□□□-WC series
●Features
○Status registers
This IC has status registers. The status registers are of 8 bits and express the following parameters.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status command.
●Status registers
Product number
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
BP1
bit 2
BP0
bit 1
bit 0
BR25H010-WC
BR25H020-WC
BR25H040-WC
BR25H080-WC
BR25H160-WC
BR25H320-WC
―
WEN
R/B
―
WPEN
0
0
0
BP1
BP0
WEN
R/B
Memory
bit
Function
Contents
location
WPB pin enable / disable designation bit
WPEN=0=invalid
This enables / disables the functions
of WPB pin.
WPEN EEPROM
WPEN=1=valid
This designates the write disable area
of EEPROM. Write designation areas
of product numbers are shown below.
BP1
EEPROM
BP0
EEPROM write disable block designation bit
Write and write status register write enable
/ disable status confirmation bit
WEN=0=prohibited
WEN
Register
Register
WEN=1=permitted
Write cycle status (READY / BUSY) status confirmation bit
―
R/B
R/B=0=READY
R/B=1=BUSY
●Write disable block setting
Write disable block
BR25H010-WC BR25H020-WC BR25H040-WC BR25H080-WC
BP1 BP0
BR25H160-WC BR25H320-WC
0
0
1
1
0
1
0
1
None
None
None
None
None
None
60h-7Fh
40h-7Fh
00h-7Fh
C0h-FFh
80h-FFh
00h-FFh
180h-1FFh
100h-1FFh
000h-1FFh
300h-3FFh
200h-3FFh
000h-3FFh
600h-7FFh
400h-7FFh
000h-7FFh
C00h-FFFh
800h-FFFh
000h-FFFh
○WPB pin
By setting WPB=LOW, write command is prohibited. As for BR25H080/160/320-WC, only when WPEN bit is set “1”, the
WPB pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25H010/
020/040-WC, both WRITE and WRSR commands are prohibited.
However, when write cycle is in execution, no interruption can be made.
Product number
BR25H010-WC
BR25H020-WC
BR25H040-WC
BR25H080-WC
BR25H160-WC
BR25H320-WC
WRSR
WRITE
Prohibition
possible
Prohibition
possible
Prohibition possible
but WPEN bit “1”
Prohibition
impossible
○HOLDB pin
By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to
EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted.
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
7/19
Technical Note
BR25H□□□-WC series
●Command mode
Ope code
BR25H080-WC
BR25H040-WC BR25H160-WC
BR25H320-WC
Command
Contents
BR25H010-WC
BR25H020-WC
WREN Write enable
WRDI Write disable
READ Read
Write enable command
Write disable command
Read command
0000
0000
0000
0000
0000
0000
*110
*100
*011
*010
*101
*001
0000
0000
0000
0000
0000
0000
*110
*100
0000
0000
0000
0000
0000
0000
0110
0100
0011
0010
0101
0001
A8011
A8010
*101
WRITE Write
Write command
RDSR Read status register Status register read command
WRSR Write status register Status register write command
*001
*=Don’t Care Bit.
●Timing chart
1. Write enable (WREN) / disable (WRDI) cycle
WREN (WRITE ENABLE): Write enable
CSB
SCK
SI
0
1
2
3
4
5
6
7
0
0
0
0
*1
1
1
0
High-Z
SO
*1 BR25H010/020/040-WC= Don’t care
BR25H080/160/320-WC= “0” input
Fig.33 Write enable command
WRDI (WRITE DISABLE): Write disable
CSB
SCK
SI
0
1
2
3
4
5
6
7
0
0
0
0
*1
1
0
0
High-Z
SO
*1 BR25H010/020/040-WC= Don’t care
BR25H080/160/320-WC= “0” input
Fig.34 Write disable
○This IC has write enable status and write disable status. It is set to write enable status by write enable command, and
it is set to write disable status by write disable command. As for these commands, set CSB LOW, and then input the
respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks,
command becomes valid.
When to carry out write and write status register command, it is necessary to set write enable status by the write enable
command. If write or write status register command is input in the write disable status, commands are cancelled. And even
in the write enable status, once write and write status register command is executed, it gets in the write disable status.
After power on, this IC is in write disable status.
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2009.08 - Rev.C
8/19
© 2009 ROHM Co., Ltd. All rights reserved.
Technical Note
BR25H□□□-WC series
2. Read command (READ)
CSB
~~
~~
~~
~~
Product
number
BR25H010-WC
BR25H020-WC
BR25H040-WC
Address
length
A6-A0
A7-A0
A8-A0
0
1
2
3
4
5
6
7
8
9
10
11
15
16
22
SCK
SI
~~
0
0
0
0
*1
0
1
1
A7 A6 A5
A4
A1 A0
~~
~~
~~
~~
High-Z
D7 D6
D2 D1 D0
SO
*1 BR25H010/020-WC=Don’t care
BR25H040-WC=A8
Fig.35 Read command (BR25H010/020/040-WC)
CSB
SCK
~
~
~~
~~
~~
Productnumber
Address
length
A9-A0
A10-A0
A11-A0
~~
0
1
2
3
4
5
6
7
8
12
23
24
30
~~
BR25H080-WC
BR25H160-WC
BR25H320-WC
~~
~~
*
*
*
0
0
0
0
0
0
1
1
A11
A1 A0
~~
SI
~~
~~
~~
~~
~~
High-Z
D7 D6
D2 D1 D0
SO
*=Don’t Care
*1 BR25H010/020/040-WC=15 clocks
BR25H080/160/320-WC=23 clocks
Fig.36 Read command (BR25H080/160/320-WC)
By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope
code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23*1 clock, and
from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input
of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data
of the most significant address, by continuing increment read, data of the most insignificant address is read.
3. Write command (WRITE)
CSB
~~
~~
~~
~~
Product
number
BR25H010-WC
BR25H020-WC
BR25H040-WC
Address
length
A6-A0
A7-A0
A8-A0
0
1
2
3
4
5
6
7
8
15
16
22
23
SCK
~~
~~
~~
0
0
0
0
*1
0
1
0
A7
A6
A5
A4
A1
A0
D7 D6
D2
~~
D1
D0
SI
~~
~~
High-Z
SO
*1 BR25H010/020-WC=Don’t care
BR25H040-WC=A8
Fig.37 Write command (BR25H010/020/040-WC)
Product
number
BR25H080-WC
BR25H160-WC
BR25H320-WC
Address
length
A9-A0
A10-A0
A11-A0
CSB
SCK
~~
~~
~~
~~
~~
~~
0
1
2
3
4
5
6
7
8
12
23
24
30
31
~~
~~
~~
*
*
*
0
0
0
0
0
0
1
0
A11
A1
A0
D7 D6
D2
~~
D1
D0
SI
~~
High-Z
~~
~~
SO
*=Don't Care
Fig.38 Write command (BR25H080/160/320-WC)
By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data
after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of
tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CSB after taking the last data (D0),
and before the next SCK clock starts. At other timing, write command is not executed, and this write command is
cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without
starting CSB, data up to 16/32*1bytes can be written for one tE/W. In page write, the insignificant 4/5*2 bit of the designated
address is incremented internally at every time when data of 1 byte is input and data is written to respective addresses.
When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten.
*1 BR25H010/020/040-WC=16 bytes at maximum
BR25H080/160/320-WC=32 bytes at maximum
*2 BR25H010/020/040-WC=Insignificant 4 bits
BR25H080/160/320-WC=Insignificant 5 bits
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
9/19
Technical Note
BR25H□□□-WC series
4. Status register write / read command
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
*
0
0
1
*
BP1 BP0
*
*
*
*
*
SI
High-Z
SO
*=Don't care
Fig.39 Status register write command (BR25H010/020/040-WC)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit7
WPEN
bit6
bit5
bit4
bit3
bit2
bit1
bit0
*
*
*
*
*
0
0
0
0
0
0
0
1
BP1 BP0
SI
High-Z
SO
*=Don't care
Fig.40 Status register write command (BR25H080/160/320-WC)
Write status register command can write status register data. The data can be written by this command are 2 bits* 1, that is,
BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As
for this command, set CSB LOW, and input ope code of write status register, and input data. Then, by making CSB HIGH,
EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, start CSB after taking the last
data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.
(Refer to the write disable block setting table.)
To the write disabled block, write cannot be made, and only read can be made.
*1 3bits including BR25H080/160/320-WC WPEN (bit7)
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
0
0
0
0
*
1
0
1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
WEN
bit0
R/B
High-Z
1
1
1
BP1 BP0
SO
1
*=Don’t care
Fig.41 Status register read command (BR25H010/020/040-WC)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
1
SI
0
bit7
WPEN
bit6
bit5
bit4
bit3
bit2
bit1
WEN
bit0
R/B
High-Z
0
0
0
BP1 BP0
SO
Fig.42 Status register read command (BR25H080/160/320-WC)
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
10/19
Technical Note
BR25H□□□-WC series
●At standby
○Current at standby
Set CSB “H”, and be sure to set SCK, SI, WPB, HOLDB input “L” or “H”. Do not input intermediate electric potantial.
○Timing
As shown in Fig.43, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read
at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status.
Even if CSB is fallen at SCK=SI=”H”,
SI status is not read at that edge.
CSB
Command start here. SI is read.
SCK
SI
0
1
2
Fig.43 Operating timing
●WPB cancel valid area
WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command and
write command, pay attention to the following WPB valid timing.
While write or write status register command is executed, by setting WPB = “L” in cancel valid area, command can be
cancelled. The area from command ope code before CSB rise at internal automatic write start becomes the cancel valid area.
However, once write is started, any input cannot be cancelled. WPB input becomes Don’t Care, and cancellation becomes invalid.
SCK
6
7
15
16
tE/W
Ope Code
Data
Data write time
Valid
(WEN is reset by WPB=L)
(BR25H010/020/040-WC)
(BR25H080/160/320-WC)
Invalid
Invalid
Invalid
Valid
Fig.44 WPB valid timing (WRSR)
*1
*2
24/32
SCK
6
7
8
15/23
tE/W
Data
Ope Code
Address
Valid
Data write time
(BR25H010/020/040-WC)
(BR25H080/160/320-WC)
Invalid
Invalid
(WEN is reset by WPB=L)
Invalid
Invalid
Invalid
*1 BR25H010/020/040-WC = 15
BR25H080/160/320-WC = 23
*2 BR25H010/020/040-WC = 24
BR25H080/160/320-WC = 32
Fig.45 WPB valid timing (WRITE)
●HOLDB pin
By HOLDB pin, command communication can be stopped temporarily (HOLD status). The HOLDB pin carries out command
communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the
HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release
the HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point
before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD
status, by starting A4 address input, read can be restarted. When in HOLD status, leave CSB LOW. When it is set CSB=HIGH
in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
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2009.08 - Rev.C
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© 2009 ROHM Co., Ltd. All rights reserved.
Technical Note
BR25H□□□-WC series
●Method to cancel each command
○READ
・Method to cancel : cancel by CSB = “H”
Ope code
8 bits
Address
Data
8 bits/16bits
8 bits
Cancel available in all areas of read mode
Fig.46 READ cancel valid timing
○RDSR
・Method to cancel : cancel by CSB = “H”
Data
Ope code
8 bits
8 bits
Cancel available in all
areas of rdsr mode
Fig.47 RDSR cancel valid timing
○WRITE、PAGE WRITE
a:Ope code, address input area.
Address
Data
tE/W
d
Ope code
8bits
Cancellation is available by CSB=”H”
b:Data input area (D7~D1 input area)
Cancellation is available by CSB=”H”
8bits/16bits
8bits
b
a
c:Data input area (D0 area)
c
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
d:tE/W area.
SCK
SI
Cancellation is available by CSB = “H”. However, when
write starts (CSB is started) in the area c, cancellation
cannot be made by any means. And by inputting on
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
D7 D6 D5 D4 D3 D2 D1 D0
c
b
Fig.48 WRITE cancel valid timing
Note 1) If VCC is made OFF during write execution, designated address data is not guaranteed, therefore
write it once again.
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WRSR
a:From ope code to 15 rise.
14 15
16
17
SCK
SI
Cancel by CSB =”H”.
D1
D0
b:From 15 clock rise to 16 clock rise (write enable area).
When CSB is started, write starts.
a
b
c
After CSB rise, cancellation cannot be made by any means.
c:After 16 clock rise.
tE/W
c
Ope code
8 bits
Data
8 bits
Cancel by CSB=”H”. However, when write starts (CSB is started)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
a
b
Fig.49 WRSR cancel valid timing
Note 1) If VCC is made OFF during write execution, designated address data is not guaranteed, therefore write it once again
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WREN/WRDI
7
8
9
SCK
a:From ope code to 7-th clock rise, cancel by CSB = “H”.
b:Cancellation is not available when CSB is started after 7-th clock.
Ope code
8 bits
a
b
Fig.50 WREN/WRDI cancel valid timing
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2009.08 - Rev.C
12/19
Technical Note
BR25H□□□-WC series
●High speed operation
In order to realize stable high speed operations, pay attention to the following input / output pin conditions.
○Input pin pull up, pull down resistance
When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller
VOL, IOL from VIL characteristics of this IC.
○Pull up resistance
VCC-VOLM
RPU
≥
・・・①
・・・②
IOLM
Microcontroller
VOLM
“L” output
IOLM
EEPROM
VILE
RPU
VOLM
≤
VILE
“L” input
Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA,
from the equation ①,
5-0.4
2×10-3
RPU≥
Fig.51 Pull up resistance
∴RPU
≥
2.3[kΩ]
With the value of Rpu to satisfy the above equation, VOLM
becomes 0.4V or lower, and with VILE (=1.5V), the equation ② is
also satisfied.
・VILE :EEPROM VIL specifications
・VOLM :Microcontroller VOL specifications
・IOLM :Microcontroller IOL specifications
And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CSB pull up.
○Pull down resistance
VOHM
RPD
≥
・・・③
・・・④
Microcontroller
VOHM
EEPROM
VIHE
IOHM
VOHM
≥
VIHE
RPD
“H” output
“H” input
IOHM
Fig.52 Pull down resistance
Example) When VCC=5V, VOHM=VCC-0.5V, IOHM=0.4mA,
VIHE=VCC×0.7V, from the equation③,
5-0.5
0.4×10-3
RPD≥
∴RPU
≥
11.3[kΩ]
Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude
of VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of
0.8VCC / 0.2VCC is input, operation speed becomes slow.*1
In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as
possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level.
(ж1 At this moment, operating timing guaranteed value is guaranteed.)
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
13/19
Technical Note
BR25H□□□-WC series
tPD_VIL characteristics
Spec
80
70
60
50
40
30
20
10
0
Vcc=2.5V
Ta=25
℃
VIH=Vcc
CL=100pF
0
0.2
0.4
0.6
0.8
1
VIL[V]
Fig.53 VIL dependency of
data output delay time tPD
○SO load capacity condition
Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLDB
to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, “Do
not connect many devices to SO bus”, “Make the wire between the controller and EEPROM short”, and so forth.
tPD-CL characteristics
80
ꢀ
℃
Spec
Vcc=2.5V Ta=25
70
60
50
40
30
20
VIH/VIL=0.8Vcc/0.2Vcc
EEPROM
SO
Spec
CL
0
20
40
60
80
100
120
CL[pF]
Fig.54 SO load dependency of data output delay time tPD
○Other cautions
Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold
violation to EEPROM, owing to difference of wire length of each input.
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2009.08 - Rev.C
14/19
Technical Note
BR25H□□□-WC series
●Equivalent circuit
○Output circuit
SO
OEint.
Fig.55 SO output equivalent circuit
○Input circuit
RESETint.
CSB
Fig.56 CSB input equivalent circuit
SCK
SI
Fig.57 SCK input equivalent circuit
Fig.58 SI input equivalent circuit
HOLDB
WPB
Fig.59 HOLDB input equivalent circuit
Fig.60 WPB input equivalent circuit
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2009.08 - Rev.C
15/19
Technical Note
BR25H□□□-WC series
●Notes on power ON/OFF
○At power ON/OFF, set CSB “H” (=VCC).
When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, mistake write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs
are canceled.)
Vcc
Vcc
GND
Vcc
CSB
GND
Good
Bad
example
example
Fig.61 CSB timing at power ON/OFF
(Good example) CSB terminal is pulled up to VCC.
At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal
circuit may not be reset, which please note.
(Bad example)
CSB terminal is “L” at power ON/OFF.
In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to noises
and the likes.
Even when CSB input is High-Z, the status becomes like this case, which please note.
○LVCC circuit
LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.9V) or below, it prevent data rewrite.
○P.O.R. circuit
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable
status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the
recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to
noises and the likes.
Recommended conditions of tR, tOFF, Vbot
tR
Vcc
tR
tOFF
Vbot
tOFF
Fig.62 Rise waveform
10ms or below
100ms or below
10ms or higher
10ms or higher
0.3V or below
0.2V or below
Vbot
0
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2009.08 - Rev.C
16/19
Technical Note
BR25H□□□-WC series
●Noise countermeasures
○VCC noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1μF) between IC VCC and GND. At that moment, attach it as close to IC as
possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND.
○SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock
bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about
0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time
(tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures.
Make the clock rise, fall time as small as possible.
○WPB noise
During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and
forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same
manner, a Schmitt trigger circuit is built in CSB input, SI input and HOLDB input too.
●Note of use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics
further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient
margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our
LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is higher than that of
GND terminal.
(5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal short circuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
17/19
Technical Note
BR25H□□□-WC series
●Ordering part number
B R
2 5
H
0
1
0
F
- W C
E
2
Rohm type
BUS type Operating
Capacity
Package type
F : SOP8
Double cell
Packaging and forming
25:SPI
temperature 010= 1K
specification
H:-40℃~+125℃
E2: Embossed tape and reel
020= 2K
040= 4K
080= 8K
160=16K
320=32K
FJ : SOP-J8
FVT :TSSOP-B8
SOP-J8
<Tape and Reel information>
4.9± 0.2
(MAX 5.25 include BURR)
Tape
Embossed carrier tape
2500pcs
+
6°
4°
−4°
Quantity
8
7
6
5
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
2
3
4
0.545
0.2± 0.1
S
1.27
0.42± 0.1
Direction of feed
1pin
0.1
S
Reel
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
∗
SOP8
<Tape and Reel information>
5.0± 0.2
(MAX 5.35 include BURR)
Tape
Embossed carrier tape
+
−
6
°
4°
4
°
Quantity
2500pcs
8
7
6
5
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
2
3
4
0.595
+0.1
0.17
-
0.05
S
1.27
Direction of feed
1pin
0.42± 0.1
Reel
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
∗
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2009.08 - Rev.C
18/19
Technical Note
BR25H□□□-WC series
TSSOP-B8
<Tape and Reel information>
3.0± 0.1
(MAX 3.35 include BURR)
Tape
Embossed carrier tape
3000pcs
4 ± ±4
8
7
6
5
Quantity
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
2
3
4
1PIN MARK
+0.05
0.145
–0.03
0.525
S
0.08 S
+0.05
0.245
M
–0.04
0.08
Direction of feed
1pin
0.65
Reel
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
∗
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.08 - Rev.C
19/19
Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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© 2009 ROHM Co., Ltd. All rights reserved.
R0039
A
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