BR24L01ANUX-W [ROHM]
推荐罗姆新产品采用BR24G01NUX-3。;型号: | BR24L01ANUX-W |
厂家: | ROHM |
描述: | 推荐罗姆新产品采用BR24G01NUX-3。 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总26页 (文件大小:390K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
128×8 bit electrically erasable PROM
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W
BR24L01AFV-W / BR24L01AFVM-W
The BR24L01A-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.
I2C BUS is a registered trademark of Philips.
zApplications
General purpose
zFeatures
1) 128 registers × 8 bits serial architecture.
2) Single power supply (1.8V to 5.5V).
3) Two wire serial interface.
4) Self-timed write cycle with automatic erase.
5) 8 byte page write mode.
6) Low power consumption.
Write (5V) : 1.2mA (Typ.)
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Typ.)
7) DATA security
Write protect feature (WP pin) .
Inhibit to WRITE at low VCC.
8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8
9) High reliability EEPROM with Double-Cell Structure
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retention : 40 years
13) Filtered inputs in SCL•SDA for noise suppression.
14) Initial data FFh in all address.
zAbsolute maximum ratings (Ta=25°C)
Parameter
Supply voltage
Symbol
Limits
Unit
V
VCC
−0.3 to +6.5
800 (DIP8)
450 (SOP8)
1
2
Power dissipation
Pd
mW
450 (SOP-J8)
3
4
5
300 (SSOP-B8)
310 (MSOP8)
−65 to +125
Storage temperature
Operating temperature
Terminal voltage
Tstg
Topr
−
°C
°C
V
−40 to +85
−0.3 to VCC+0.3
1
Degradation is done at 8.0mW/°C for operation above 25°C.
2, 3 Degradation is done at 4.5mW/°C for operation above 25°C.
4
5
Degradation is done at 3.0mW/°C for operation above 25°C.
Degradation is done at 3.1mW/°C for operation above 25°C.
1/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zRecommended operating conditions
Parameter
Supply voltage
Input voltage
Symbol
Limits
1.8 to 5.5
0 to VCC
Unit
V
V
CC
IN
V
V
zDC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)
Parameter
Symbol
Min.
Typ.
−
Max.
Unit
V
Conditions
2.5V≤VCC≤5.5V
"HIGH" input volatge 1
"LOW" input volatge 1
"HIGH" input volatge 2
"LOW" input volatge 2
"LOW" output volatge 1
"LOW" output volatge 2
Input leakage current
Output leakage current
V
IH1
IL1
IH2
IL2
0.7VCC
−
0.3VCC
−
V
−
−
V
2.5V≤VCC≤5.5V
1.8V≤VCC≤2.5V
1.8V≤VCC≤2.5V
V
0.8VCC
−
V
V
−
−
−
0.2VCC
0.4
0.2
1
V
V
OL1
OL2
−
V
I
I
OL=3.0mA, 2.5V≤VCC≤5.5V, (SDA)
OL=0.7mA, 1.8V≤VCC≤5.5V, (SDA)
V
−
−
V
I
LI
−1
−1
−
µA
µA
VIN=0V to VCC
I
LO
−
1
VOUT=0V to VCC
V
CC=5.5V, fSCL=400kHz, tWR=5ms,
I
I
CC1
CC2
−
−
2.0
mA
Byte Write, Page Write
Operating current
VCC=5.5V, fSCL=400kHz
−
−
−
−
0.5
2.0
mA
Random Read, Current Read,
Sequential Read
VCC=5.5V, SDA·SCL=VCC
,
µA
Standby current
I
SB
A0, A1, A2=GND, WP=GND
This product is not designed for protection against radioactive rays.
2/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zDimension
9.3±0.3
8
5
4
5.0±0.2
8
5
1
7.62
1
4
0.15±0.1
0.1
1.27
0.4±0.1
2.54
0.5±0.1
0° ~ 15°
Fig.1(a) PHYSICAL DIMENSION (Units : mm)
DIP8 (BR24L01A-W)
Fig.1(b) PHYSICAL DIMENSION (Units : mm)
SOP8 (BR24L01AF-W)
3.0±0.2
4.9±0.2
8
5
8 7 6 5
1
4
0.15±0.1
1 2 3 4
0.2±0.1
0.1
0.22±0.1
(0.52) 0.65
0.1
1.27
0.42±0.1
Fig.1(c) PHYSICAL DIMENSION (Units : mm)
SOP-J8 (BR24L01AFJ-W)
Fig.1(d) PHYSICAL DIMENSION (Units : mm)
SSOP-B8 (BR24L01AFV-W)
2.9±0.1
8
5
1
4
+0.05
0.145
−0.03
0.475
+0.05
−0.04
M
0.22
0.08
0.08 S
0.65
Fig.1(e) PHYSICAL DIMENSION (Units : mm)
MSOP8 (BR24L01AFVM-W)
3/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zBlock diagram
A0
A1
1
2
3
4
8
7
6
5
VCC
1kbit EEPROM array
8bit
7bit
Address
decoder
Slave word
address register
Data
register
WP
7bits
START
STOP
A2
SCL
SDA
Control logic
ACK
High voltage generator
Vcc level detect
GND
Fig.2 BLOCK DIAGRAM
zPin configuration
V
CC
WP
7
SCL
6
SDA
5
8
BR24L01A-W
BR24L01AF-W
BR24L01AFJ-W
BR24L01AFV-W
BR24L01AFVM-W
1
2
3
4
A0
A1
A2
GND
Fig.3 PIN LAYOUT
zPin name
Pin name
I / O
Function
V
CC
−
−
Power supply
Ground (0V)
GND
IN
IN
Slave address set
Serial clock input
A0, A1, A2
SCL
Slave and word address,
serial data input, serial data output
1
SDA
WP
IN / OUT
IN
Write protect input
1 An open drain output requires a pull-up resistor.
4/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)
Fast-mode
Standard-mode
2.5V ≤ Vcc ≤ 5.5V
1.8V ≤ Vcc ≤ 5.5V
Parameter
Symbol
Unit
Min. Typ. Max. Min. Typ. Max.
fSCL
tHIGH
tLOW
tR
−
0.6
1.2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
400
−
−
4.0
4.7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
−
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
ns
µs
µs
Clock frequency
Data clock "HIGH" period
Data clock "LOW" period
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Input data hold time
−
−
1
1
0.3
0.3
−
1.0
0.3
−
tF
−
−
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
0.6
0.6
0
4.0
4.7
0
−
−
−
−
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus free time
100
0.1
0.1
0.6
1.2
−
−
250
0.2
0.2
4.7
4.7
−
−
0.9
−
3.5
−
tDH
tSU:STO
tBUF
−
−
−
−
tWR
5
5
Write cycle time
Noise spike width (SDA and SCL)
WP hold time
−
0.1
−
−
0.1
−
tl
tHD:WP
tSU:WP
tHIGH:WP
0
0
0.1
1.0
−
0.1
1.0
−
WP setup time
WP high period
−
−
1 Not 100% tested.
5/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zSynchronous data timing
t
R
t
F
tHIGH
SCL
t
HD : STA
t
SU : DAT
t
LOW
PD
tHD : DAT
SDA
(IN)
t
BUF
t
tDH
SDA
(OUT)
SCL
t
SU : STA
t
HD : STA
tSU : STO
SDA
START BIT
STOP BIT
Fig.4 SYNCHRONOUS DATA TIMING
•SDA data is latched into the chip at the rising edge of SCL clock.
•Output data toggles at the falling edge of SCL clock.
zWrite cycle timing
SCL
SDA
D0
ACK
WRITE DATA (n)
tWR
STOP CONDITION
START CONDITION
Fig.5 WRITE CYCLE TIMING
6/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zWP timing
SCL
DATA (1)
DATA (n)
D1
D0
SDA
ACK
ACK
t
WR
STOP BIT
WP
t
SU : WP
t
HD : WP
Fig.6(a) WP TIMING OF THE WRITE OPERATION
SCL
SDA
WP
DATA (1)
DATA (n)
D1
D0
ACK
ACK
t
HIGH : WP
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
WR
D0 of first byte until the end of t . ( See Fig.6 (a) )
During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )
WR
•In the case of setting WP “HIGH” during t , WRITE operation is stopped in the middle and the data of accessing
address is not guaranteed. Please write correct data again in the case.
7/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zDevice operation
1) Start condition (Recognition of start bit)
• All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
• The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)
2) Stop condition (Recognition of stop bit)
• All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (See Fig.4 SYNCHRONOUS DATA TIMING)
3) Notice about write command
• In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.
4) Device addressing
• Following a START condition, the master output the slave address to be accessed.
• The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”.
• The next three bit (device address) identify the specified device on the bus.
The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight
device may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation to
the performed.
• The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ
1010
A2
A1
A0
R / W
5) Write protect (WP)
CC
When WP pin set to V (H level), write protect is set for 128 words (all address).
When WP pin set to GND (L level), enable to write 128 words (all address).
CC
Either control this pin or connect to GND (or V ). It is inhibited from being left unconnected.
8/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
6) Acknowledge
• Acknowledge is a software convention used to indicate successful data transfers.
The transmitter device will release the bus after transmitting eight bits.
(When inputting the slave address in the write or read operation, transmitter is µ-COM. When outputting the data in
the read operation, it is this device.)
• During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledge that the eight bits of data has
been received.
(When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in
the read operation, it is µ-COM.)
• The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).
• In the WRITE mode, the device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word
(word address and write data).
• In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an
Acknowledge.
• If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit
the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP
condition before returning to the standby mode. (See Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER)
START CONDITION
(START BIT)
SCL
(From µ−COM)
1
8
9
SDA
(µ−COM
OUTPUT DATA)
SDA
(IC OUTPUT DATA)
Acknowledge Signal
(ACK Signal)
Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER
9/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zByte write
S
T
A
R
T
W
R
I
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
T
E
DATA
SDA
LINE
WA
6
WA
0
1
0
1
0
D7
D0
A2 A1A0
R A
A
C
K
A
C
K
/
C
W K
WP
Fig.8 BYTE WRITE CYCLE TIMING
• By using this command, the data is programmed into the indicated word address.
• When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
zPage write
S
T
A
R
T
W
R
I
T
E
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS (n)
DATA (n)
DATA (n+7)
SDA
LINE
WA
6
WA
0
1
0
1
0
D7
D0
D0
A2 A1A0
R
/
A
C
A
C
K
A
C
K
A
C
K
W K
WP
Fig.9 PAGE WRITE CYCLE TIMING
• This device is capable of eight byte page write operation.
• When two or more byte data are inputted, the three low order address bits are internally incremented by one after the
receipt of each word. The four higher order bits of the address (WA6 to WA3) remain constant.
• If the master transmits more than eight words, prior to generating the STOP condition, the address counter will
“roll over”, and the previous transmitted data will be overwritten.
10/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zCurrent read
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
DATA
SDA
LINE
1
0
1
0
A2 A1 A0
D7
D0
R
/
W
A
C
K
A
C
K
Fig.10 CURRENT READ CYCLE TIMING
• In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the
internal address counter is increased by one from the last accessed address (n).
Thus Current Read outputs the data of the next word address (n+1).
If the last command is Byte or Page Write, the internal address counter stays at the last address (n).
Thus Current Read outputs the data of the word address (n).
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue
to transmit the data. [ It can transmit all data (1kbit 128word) ]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
zRandom read
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
SLAVE
ADDRESS
WORD
ADDRESS(n)
DATA(n)
SDA
LINE
WA
6
WA
0
1
0
1
0
A2A1A0
1
0
1
0
A2A1A0
D7
D0
R
/
A
C
A
C
K
R
/
A
C
A
C
K
W K
W K
Fig.11 RANDOM READ CYCLE TIMING
• Random read operation allows the master to access any memory location indicated word address.
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to
transmit the data. [ It can transmit all data (1kbit 128word) ]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
11/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zSequential read
S
T
A
R
T
R
S
E
T
SLAVE
ADDRESS
A
D
O
P
DATA(n)
DATA(n+x)
SDA
LINE
1
0
1
0 A2 A1 A0
D7
D0
D7
D0
R A
A
C
K
A
C
K
A
C
K
/
C
W K
Fig.12 SEQUENTIAL READ CYCLE TIMING
(Current Read)
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to
transmit the data. [ It can transmit all data (1kbit 128word) ]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
• The Sequential Read operation can be performed with both Current Read and Random Read.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
12/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
zApplication
1) WP effective timing
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
[WP effective timing] as follows.
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (tWR) is the cancellation
WR
effective period. In case of setting WP to “H” during t , WRITE operation is stopped in the middle and the data of
accessing address is not guaranteed, so that write correct data again please.
WR
It is not necessary waiting t (5msmax.) after stopping command by WP, because the device is stand by state.
· The rising edge of the clock
which take in D0
SCL
SDA
SCL
SDA
· The rising edge
of SDA
D1
D0
ACK
D0
ACK
AN ENLARGEMENT
AN ENLARGEMENT
S
T
A
R
T
A
C
K
L
A
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
tWR
SLAVE
ADDRESS
WORD
ADDRESS
C
K
L
SDA
WP
D7 D6 D5 D4 D3 D2 D1 D0
DATA
Stop of the write
operation
WP cancellation invalid period
WP cancellation effective period
No data will be written
Data is not
guaranteed
Fig.13 WP EFFECTIVE TIMING
13/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
2) Software reset
Please execute software reset in case that the device is an unexpected state after power up and / or the command
input need to be reset.
There are some kinds of software reset. Here we show three types of example as follows.
During dummy clock, please release SDA bus ( tied to VCC by pull up resistor ).
During that time, the device may pull the SDA line LOW for Acknowledge or outputting or read data.
If the master controls the SDA line HIGH, it will conflict with the device output LOW then it makes a current overload.
It may cause instantaneous power down and may damage the device.
DUMMY CLOCK × 14
START × 2
COMMAND
COMMAND
SCL
SDA
1
2
13
14
Fig.14-(a) DUMMY CLOCK × 14 + START + START
DUMMY CLOCK × 9
START
START
COMMAND
COMMAND
SCL
SDA
1
2
8
9
Fig.14-(b) START+ DUMMY CLOCK × 9 + START
START × 9
COMMAND
COMMAND
SCL
SDA
1
2
3
7
8
9
Fig.14-(c) START × 9
COMMAND starts with start condition.
14/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
3) Acknowledge polling
Since the device ignore all input commands during the internal write cycle, no ACK will be returned.
When the master send the next command after the wire command, if the device returns the ACK, it means that the
program is completed. If no ACK id returned, it means that the device is still busy.
By using Acknowledge polling, the waiting time is minimized less than tWR=5ms.
In case of operating Write or Current Read right after Write, first, send the slave address (R / W is “HIGH” or “LOW”
respectively). After the device returns the ACK, continue word address input or data output respectively.
During the internal write cycle,
no ACK will be returned.
(ACK=HIGH)
THE FIRST WRITE COMMAND
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
H
A
C
K
H
SLAVE
ADDRESS
SLAVE
ADDRESS
WRITE COMMAND
• • •
t
WR
THE SECOND WRITE COMMAND
S
T
A
R
T
S
T
A
R
T
A
A
C
K
L
A
C
K
L
S
T
O
P
A
C
K
L
SLAVE
ADDRESS
C
K
H
WORD
ADDRESS
SLAVE
ADDRESS
• • •
DATA
t
WR
After the internal write cycle
is completed ACK will be returned
(ACK=LOW). Then input next
Word Address and data.
Fig.15 SUCCESSIVE WRITE OPERATION BY ACKNOWLEDGE POLLING
15/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
4) Command cancellation by start and stop condition
During a command input, it is canceled by the successive inputs of start condition and stop condition. (Fig.4)
But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop
condition is impossible, so that the reset can’t work. Execute the software reset in the cases. (See Page14)
Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read
or Current Read, internal address counter is not confirmed.
Therefore operation of Current Read after this in not valid. Operate a Random Read in this case.
SCL
1
0
1
0
SDA
START
STOP
CONDITION
CONDITION
Fig.16 COMMAND CANCELLATION BY START AND STOP CONDITION
DURING THE INPUT OF SLAVE ADDRESS
16/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
5) Notes for power supply
CC
V
rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device
may not work properly due to an incomplete reset of internal circuit.
CC
To prevent this, the device has the feature of P.O.R. and LV
.
CC
In the case of power up, keep the following conditions to ensure functions of P.O.R and LV
.
(1) It is necessary to be “SDA=H” and “SCL=’L’ or ‘H’ ”.
R
OFF
(2) Follow the recommended conditions of t , t , Vbot for the function of P.O.R. durning power up.
t
R
V
CC
Recommended conditions of tR, tOFF, Vbot
t
R
tOFF
Vbot
Below 10ms Above 10ms
Below 100ms Above 10ms
Below 0.3V
t
OFF
Below 0.2V
Vbot
0
V
CC rising wave from
(3) Prevent SDA and SCL from being “Hi-Z”.
In case that condition 1. and / or 2. cannot be met, take following actions.
A) Unable to keep condition 1. (SDA is “LOW” during power up.)
→Control SDA, SCL to be “HIGH” as figure below.
V
CC
t
LOW
SCL
SDA
After VCC becomes stable
After VCC becomes stable
t
DH
t
SU:DAT
t
SU:DAT
a) SCL="H" and SDA="L"
b) SCL="L" and SDA="L"
B) Unable to keep condition 2.
→After power becomes stable, execute software reset. (See page14 )
C) Unable to keep condition 1 and 2.
→Follow the instruction A first, then the instruction B.
17/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
CC
• LV circuit
CC
CC
LV circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LV voltage
(Typ.=1.2V), write operation is inhibited.
6) I / O circuit
• Pull up resister of SDA pin
The pull up resister is needed because SDA is NMOS open drain. Decide the value of this resister (R ) properly,
PU
IL
L
OH OL
by considering V , I characteristics of a controller which control the device and V , I characteristics of the device.
PU
PU
If large R is chosen, clock frequency need to be slow. In case of small R , the operating current increases.
PU
• Maximum of R
PU
Maximum of R is determined by following factor.
① SDA rise time determined by RPU and the capacitance of bus line (CBUS) must be less than TR.
And the other timing must keep the conditions of AC spec.
① When SDA bus is HIGH, the voltage A of SDA bus determined by a total input leak (IL) of the all devices
PU
connected to the bus and R must be enough higher than input HIGH level of a controller and the device,
CC
including noise margin 0.2 V
.
V
CC − ILRPU − 0.2VCC ≥ VIH
MICRO
COMPUTER
BR24LXX
SDA PIN
0.8VCC − VIH
RPU
RPU ≤
A
IL
IL
IL
Examples : When VCC=3V I
L=10µA VIH=0.7VCC
THE CAPACITANCE OF
BUS LINE (CBUS)
2
According to
0.8×3−0.7×3
10×10−6
RPU ≤
≤ 300 [kΩ]
18/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
PU
• The minimum value R
PU
The minimum value of R is determined by following factors.
① Meet the condition that VOLMAX=0.4V, IOLMAX=3mA when the device output low on SDA line.
V
CC − VOL
≤ IOL
RPU
V
CC − VOL
RPU
≥
I
OL
① VOLMAX (=0.4V) must be lower than the input LOW level of the controller and the EEPROM including
CC
recommended noise margin (0.1 V ).
V
OLMAX ≤ VIL − 0.1VCC
Examples : VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC
3−0.4
1
According to
RPU ≥
3×10−3
≥ 867 [Ω]
and
V
V
OL
IL
=0.4[V]
=0.3×3
=0.9[V]
so that condition 2 is met
• Pull up resister of SCL pin
In the case that SCL is controlled by CMOS output, the pull up resister of SCL is not needed.
CC
But in the case that there is a timing at which SCL is Hi-Z, connect SCL to V with pull up resister.
Several several dozen kΩ is recommended as a pull up resister, which is considered with the driving ability of the
output port of the controller.
7) Connections of A0, A1, A2, WP pin
• Connections of device address pin (A0, A1, A2)
The state of device address PIN are compared with the device address send by the master, then one of the devices
which are connected to the identical bus is selected. Pull up or down these pins, or connect them to VCC or GND.
Pins which is not used as device address (N.C. PIN) may be either HIGH, LOW, and Hi-Z.
The type of the device which have N.C. PIN
BR24L16 / F / FJ / FV / FVM-W A0, A1, A2
BR24L08 / F / FJ / FV / FVM-W A0, A1
BR24L04 / F / FJ / FV / FVM-W A0
• Connections of WP pin
The WP input allows or inhibits write operations. When WP is HIGH, only READ is available and WRITE to any
address is inhibited. Both Read and Write are available when WP is LOW.
In the case that the device is used as a ROM, it is recommended that WP is pulled up or connected to VCC.
In the case that both READ and WRITE are operated, WP pin must be pulled down or connected to GND or
controlled.
19/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
CC
8) Notes for noise on V
• About bypass capacitor
Noise and surges on power line may cause the abnormal function. It is recommended that the bypass capacitors
CC
(0.1µF) are attached on the V and GND line beside the device.
The attachment of bypass capacitors on the board near by connector is also recommended.
IC
capacitor 0.01 to 0.1µF
PRINT BASE
GND
VCC
capacitor 10 to 100µF
9) The notice about the connection of controller
S
• About R
The open drain interface is recommended for SDA port in I2CBUS. But, in the case that Tri-state CMOS interface is
S
PU
applied to SDA, insert a series resister R between SDA pin of the device and a pull up resister R . It limits the
current from PMOS of controller to NMOS of EEPROM.
S
S
R also protects SDA pin from surges. Therefore, R is able to be used though SDA port is open drain.
RPU
RS
CONTROLLER
EEPROM
ACK
SCL
SDA
"H" OUTPUT OF
CONTROLLER
"L" OUTPUT OF
EEPROM
The "H" output of controller
and the "L" output of EEPROM may cause
current overload to SDA line.
20/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
S
• The maximum value of R
S
The maximum value of R is determined by following factors.
① SDA rise time determined by RPU and the capacitance of bus line (CBUS ) of SDA must be less than tR.
And the other timing must also keep the conditions of the AC timing.
① When the device outputs LOW on SDA line, the voltage of the bus A determined by RPU and RS must be
CC
lower than the inputs LOW level of the controller, including recommended noise margin (0.1V ).
(VCC−VOL) × R
S
+ VOL+0.1VCC ≤ VIL
RPU+R
S
V
IL−VOL−0.1VCC
1.1VCC−VIL
RS
≤
× RPU
Examples : when VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ
2
According to
0.3×3−0.4−0.1×3
1.1×3−0.3×3
RS
≤
× 20×103
≤ 1.67 [kΩ]
V
CC
A
RPU
RS
V
OL
I
OL
CAPACITANCE OF
BUS LINE (CBUS)
V
IL
CONTROLLER
EEPROM
S
• The minimum value of R
S
The minimum value of R is determined by the current overload due to the conflict on the bus.
The current overload may cause noise on the power line and instantaneous power down.
The following conditions must be met, where Ι is the maximum permissible current.
The maximum permissible current depends on VCC line impedance and so on. It need to be less than 10mA for
EEPROM.
V
R
CC
≤ Ι
S
V
CC
RS ≥
Ι
Examples : When VCC=3V, Ι=10mA
RPU
RS
"L" OUTPUT
3
RS ≥
10×10−3
MAXIMUM
CURRENT
≥ 300 [Ω]
Ι
"H" OUTPUT
CONTROLLER
EEPROM
21/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
10) The special character DATA
The following characteristic data are typ value.
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
Ta=85°C
Ta=−40°C
Ta=25°C
SPEC
Ta=25°C
Ta=85°C
Ta=85°C
Ta=−40°C
Ta=25°C
SPEC
SPEC
5
Ta=−40°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
6
L
OUTPUT CURRENT : IOL (mA)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.19 Low output voltage VOL−IOL
(VCC=1.8V)
Fig.17 High input voltage VIH
(A0,A1,A2,SCL,SDA,WP)
Fig.18 Low input voltage VIL
(A0,A1,A2,SCL,SDA,WP)
1
0.8
0.6
0.4
0.2
0
1.2
1
1.2
1
SPEC
SPEC
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
SPEC
Ta=25°C
Ta=85°C
Ta=85°C
Ta=25°C
Ta=−40°C
Ta=85°C
Ta=25°C
Ta=−40°C
Ta=−40°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
L
OUTPUT CURRENT : IOL (mA)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.20 Low output voltage VOL−IOL
(VCC=2.5V)
Fig.21 Input leakage current ILI
(A0,A1,A2,SCL,WP)
Fig.22 Output leakage current
I
LO(SDA)
2.5
2
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2
SPEC
SPEC
SPEC
f
SCL=400kHz
f
SCL=100kHz
DATA=AAh
DATA=AAh
f
SCL=400kHz
DATA=AAh
1.5
1
1.5
1
Ta=25°C
Ta=85°C
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=25°C
Ta=85°C
Ta=−40°C
0.5
0.5
Ta=−40°C
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.23 Write operating current
Fig.24 Read operating current
Fig.25 Write operating current
I
CC1 (fSCL=400kHz)
I
CC2 (fSCL=400kHz)
ICC1 (fSCL=100kHz)
22/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
0.6
0.5
2.5
2
10000
1000
100
10
SPEC
Ta=85°C
Ta=25°C
Ta=−40°C
SPEC
f
SCL=100kHz
0.4
0.3
0.2
0.1
0
DATA=AAh
SPEC1
1.5
1
SPEC2
Ta=25°C
Ta=85°C
0.5
0
Ta=25°C
Ta=−40°C
Ta=−40°C
Ta=85°C
1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.26 Read operating current
Fig.27 Standby current ISB
Fig.28 Clock frequency fSCL
I
CC2 (fSCL=100kHz)
5
5
4
3
2
1
0
5
4
3
2
1
0
SPEC2
SPEC2
SPEC2
4
3
2
1
0
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
SPEC1
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=85°C
Ta=25°C
Ta=−40°C
Ta=−40°C
Ta=25°C
Ta=85°C
SPEC1
4
SPEC1
4
0
1
2
3
5
6
0
1
2
3
4
5
6
0
1
2
3
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.29 Data clock "H" period tHIGH
Fig.30 Data clock "L" period tLOW
Fig.31 Start condition hold time
t
HD:STA
6
5
4
3
2
1
0
50
0
50
0
SPEC1,2
SPEC1,2
SPEC2
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
−50
−50
Ta=85°C
−100
−150
−200
−100
−150
−200
Ta=85°C
Ta=25°C
Ta=−40°C
SPEC1
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=25°C
Ta=−40°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.32 Start condition setup time
Fig.33 Input data hold time
Fig.34 Input data hold time
t
SU:STA
t
HD:DAT(HIGH)
tHD:DAT(LOW)
23/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
300
300
200
100
0
4
3
2
1
0
SPEC2
SPEC2
SPEC2
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
200
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1
SPEC1
100
Ta=85°C
Ta=85°C
Ta=25°C
Ta=−40°C
0
Ta=85°C
Ta=25°C
Ta=−40°C
SPEC1
Ta=25°C
Ta=−40°C
−100
−100
−200
SPEC2
SPEC1
−200
0
1
2
3
4
5
6
6
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.35 Input data setup time
Fig.36 Input data setup time
Fig.37 Output data delay time
t
SU:DAT(HIGH)
t
SU:DAT(LOW)
tPD0
4
4
3
2
1
0
4
3
2
1
0
SPEC2
SPEC2
SPEC2
3
2
1
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=85°C
Ta=25°C
Ta=−40°C
Ta=−40°C
Ta=25°C
Ta=85°C
SPEC1
SPEC1
SPEC1
SPEC2
SPEC1
SPEC2
SPEC1
SPEC2
SPEC1
0
1
2
3
4
5
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.38 Output data delay time
Fig.39 Output data hold time
Fig.40 Output data hold time
t
PD1
t
DH0
tDH1
5
6
5
4
3
2
1
0
5
4
3
2
1
0
SPEC1,2
SPEC2
SPEC2
4
3
2
1
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Ta=−40°C
Ta=25°C
Ta=85°C
SPEC1
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=85°C
Ta=25°C
Ta=−40°C
SPEC1
4
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
5
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.42 BUS free time tBUF
Fig.43 Write cycle time tWR
Fig.41 Stop condition setup time
t
SU:STO
24/25
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
BR24L01AFV-W / BR24L01AFVM-W
Memory ICs
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
SPEC2 : STANDARD-MODE
0.5
Ta=−40°C
Ta=85°C
0.4
Ta=25°C
Ta=−40°C
Ta=85°C
Ta=25°C
0.3
0.2
0.1
0
Ta=−40°C
Ta=25°C
Ta=85°C
SPEC1,2
SPEC1,2
SPEC1,2
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.44 Noise spike width
Fig.45 Noise spike width
Fig.46 Noise spike width
t
I
(SCL H)
t
I
(SCL L)
t
I
(SDA H)
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2
0
1.2
1
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC1,2
SPEC1,2
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.8
0.6
0.4
0.2
0
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Ta=−40°C
Ta=85°C
−0.2
−0.4
−0.6
Ta=25°C
Ta=85°C
Ta=−40°C
Ta=−40°C
Ta=25°C
Ta=85°C
Ta=25°C
SPEC1,2
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.48 WP setup time tSU:WP
Fig.49 WP high period tHIGH:WP
Fig.47 Noise spike width
tI (SDA L)
25/25
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document use silicon as a basic material.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level of
reliability and the malfunction of with would directly endanger human life (such as medical instruments,
transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other
safety devices), please be sure to consult with our sales representative in advance.
About Export Control Order in Japan
Products described herein are the objects of controlled goods in Annex 1 (Item 16) of Export Trade Control
Order in Japan.
In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)
on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.
Appendix1-Rev1.0
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