BM1050AF_技术文档

Datasheet

Quasi-Resonant Control DC/DC

converter and Power Factor Correction

converter IC for AC/DC Converter

BM1050AF-G

●General Description

●Features

 Quasi-resonant circuit + PFC circuit

BM1050AF is compounded LSI of Power Factor Correction

converter (PFC) for harmonic solution and DC/DC converter

(DC/DC). Because DC/DC operates on Quasi-resonant

method, DC/DC contributes to Low EMI.

 Built-in HV Starter circuit

 Low consumption current (typ.10uA) when starter

circuit is OFF.

BM1050AF built in a HV starter circuit that tolerates 650V.

Because of putting the current sense resistors externally

both the PFC part and the DC/DC part, IC enables power

supply design free.

In the PFC part, IC adopts peak current control operation.

Suitable application is proposed by a various protection

circuit, such as the multiplier with a revision circuit on the AC

voltage falls, the load regulation revision circuit, and the

maximum power feed-forward circuit, etc.

 Quasi resonant circuit

Max operating frequency(120kHz)

Frequency reduction function

Over-current limiting variable function

Pulse-by-pulse over-current protection circuit

Built-in Soft start

Voltage protection function (brown out) during low

input

ZT pin Over Voltage Protection

Output overload protection (auto recovery /latch

switching enabled)

Moreover, the frequency hopping function is built in and it

contributes to low EMI.

The Quasi-resonant system of a DC/DC part contributes to

low EMI because PFC operates by soft switching.

A burst mode is built in, so the power is reduced at light load.

Various protection functions, such as a soft start function, a

burst function, an over-current limiting for every cycle,

overvoltage protection, and over current protection, are built

in. The pin for communicated control with a controller and the

external stop pin are prepared; it proposes the system that

can be adapted for various applications.

250nsec Leading-Edge Blanking

 Power Factor Correction circuit

Peak current control (65kHz)

Frequency hopping function

Per-cycle over current protection circuit

Maximum power revision

the multiplier with a revision circuit when the AC

voltage falls

the load change measure circuit



Selectable protection method by LATCH/AUTOR

terminal.

●Basic specifications

 Operating Power Supply Voltage Range:

VCC：8.5 to 24.0V

LATCH/AUTOR=H : Latch

LATCH/AUTOR=L : Auto recovery

 External stop function (COMP pin)

 AC input voltage stop detected function (ACDET)

 Built-in PFC stop terminal (PFCON/OFF)

 Operating Current:

QR ON (PFC OFF)：1.20mA(pulse on)

QR ON (PFC OFF)：1.00mA(pulse off)

QR ON (PFC ON)：1.80mA(pulse on)

●Package(s)

SOP24 15.0mm×5.40mm ×1.80mm pitch1.27mm

 Oscillation Frequency QR part :120kHz(FB=2.0V typ)

 Operating Temperature: -40℃to +85℃



(Typ.)

(TYP.)

（TYP.）

●Typical Application Circuit(s)

●Applications

TV, AC adapters, printers, LED lighting

Figure 1. Application circuit

○Product structure：Silicon monolithic integrated circuit ○This product is not designed for protection against radioactive rays

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●Absolute Maximum Ratings (Ta = 25℃)

Parameter

Maximum applied voltage 1

Maximum applied voltage 2

Symbol

Vmax1

Vmax2

Rating

650

30

Unit

V

Conditions

VH_IN

VCC, QR_SEL

P_BO, P_VSEO, P_VS, P_BOPK

P_CS,PFCON/OFF,COMP,

ACDET, ACTIMER,QR_CS, QR_ZT,

QR_FB,LATCH/AUTOR, VREF

GCLAMP, P_OUT, QR_OUT

QR_OUT, P_OUT

Maximum applied voltage 3

Vmax3

5.5

V

Maximum applied voltage 4

output peak current 1

Vmax4

I_OH

15

-0.5

V

A

output peak current 2

I_OL

1.0

A

QR_OUT, P_OUT

QR_ZT pin current 1

QR_ZT pin current 2

Allowable dissipation

Operating temperature range

Maximum junction temperature

Storage temperature range

I_SZT1

I_SZT2

Pd

Topr

Tjmax

Tstr

-2.0

3.0

687.6 (Note1)

-40 ～ +85

150

mA

mW

^oC

-55 ～ +150

(Note1) When mounted (on 70 mm × 70 mm, 1.6 mm thick, glass epoxy on single-layer substrate).

Reduce to 5.5 mW/C when Ta = 25C or above.

●Operating Conditions (Ta = 25℃)

Parameter

Symbol

VCC

Rating

8.5～24.0

80～600

0.0～1.8

Unit

V

Conditions

VCC

Power supply voltage range 1

Power supply voltage range 2

Power supply voltage range 3

VH_IN

P_BO

V

VH_IN

V

P_BO

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●Electrical Characteristics (Unless otherwise noted, Ta=25, VH_IN=320Vdc, VCC=12V)

Specifications

Parameter

［Circuit current］

Symbol

Unit

Conditions

Minimum

Standard Maximum

VCC=12.0V

(QR=ON, PFC=OFF)

QR_FB=1.0V

(during pulse operation)

Circuit current (ON) 1

Circuit current (ON) 2

I_ON1

0.700

1.200

1.700

mA

VCC=12.0V

(QR =ON, PFC=OFF)

QR_FB=VREF

I_ON2

0.700

0.800

1.000

1.800

1.300

2.800

mA

(during

pulse

operation

when OFF)

VCC=12.0V

(QR =ON, PFC=ON)

QR_FB=1.0V

Circuit current (ON) 3

I_ON3

(during pulse operation)

［Start circuit Block］

Start current 1

Start current 2

I_START1

I_START2

0.100

1.000

0.500

3.000

1.000

5.000

mA

VCC= 0V

VCC=10V

Input current from VH_IN

terminal after releasing

UVLO

OFF Current

I_START3

V_SC

-

10

16

uA

V

VH voltage switched

start current

0.400

0.800

1.400

［VREF Block］

VREF output voltage

VREF output capacitor

GCLAMP voltage 1

GCLAMP voltage 2

V_REF1

C_REF

GCL1

GCL2

3.500

0.68

11.0

4.000

1.00

12.5

4.500

2.20

14.0

V

uF

V

VCC=15V

VCC=22V

V

When VREF rise

The ratio of VREF pin

voltage.

77.5

（3.100V）

87.5

(3.500V)

97.5

(3.900V)

VREF UVLO 1

V_RUVLO1

%

When VREF drop

The ratio of VREF pin

voltage.

52.5

(2.100V)

62.5

(2.500V)

72.5

(2.900V)

VREF UVLO 2

V_RUVLO2

V_RUVLO3

%

25

（1.000V）

13.50

7.00

6.50

27.0

23.0

4.0

0.400

0.200

VREF UVLO hysteresis

-

V_RUVLO3=V_RUVLO1-V_RUVLO2

VCC UVLO voltage 1

VCC UVLO voltage 2

VCC UVLO hysteresis

VCC OVP voltage 1

VCC OVP voltage 2

VCC OVP hysteresis

Brown out detection voltage 1

Brown out detection voltage 2

Brown out hysteresis

Brown out detection

delay time 1

V_UVLO1

V_UVLO2

V_UVLO3

V_OVP1

V_OVP2

V_OVP3

V_BO1

12.50

5.50

-

24.0

20.0

-

0.350

-

14.50

8.50

-

30.0

26.0

-

0.450

-

V

VCC rise

VCC drop

V_UVLO3=V_UVLO1-V_UVLO2

VCC rise

VCC drop

V_OVP3=V_OVP1- V_OVP2

P_BO rise

P_BO drop

V_BO2

V_BO3

V_BO3= V_BO1－V_BO2

Times until ACDET logic

change ( ACTIMER=L)

Times until ACDET logic

change ( ACTIMER=H)

Times until PFC and QR

stop

T_BO1

T_BO2

T_BO3

21.8

87.0

170

32.0

128.0

250

42.2

169.0

330

ms

Brown out detection

delay time 2

Brown out detection

delay time 3

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●Electrical Characteristics (Unless otherwise noted ,Ta=25,VH_IN=320Vdc,VCC=12V)

Specifications

Parameter

Symbol

Unit

Conditions

Minimum

50

Standard Maximum

［ACDET pin characteristics］

ACDET pin ON resister

R_ACDET

100

200

Ω

［ACTIMER pin characteristics］

ACTIMER pin input L level

ACTIMER pin input H level

ACTIMER pin

V_ACTIMEL

V_ACTIMEH

-

0.3

-

V

1.2

R_ACTIMEH

165

330

500

kΩ

pull-down resistor

［PFCON/OFF pin characteristics］

PFCON/OFF pin input L level

PFCON/OFF pin input H level

PFCON/OFF pin

pull-down resistor

PFCON/OFF pin timer time

V_PON/OFFL

-

0.3

-

V

PFC = ON

PFC = OFF

V_PON/OFFH

R_PON/OFFH

T_PFCON/OFF

1.2

50

100

150

kΩ

0.50

1.50

3.00

ms

［LATCH/AUTOR pin characteristics］

LATCH/AUTOR pin

input L level

LATCH/AUTOR pin

input H level

LATCH/AUTOR pin

pull-down resistor

V_MODEL

V_MODEH

R_MODEH

-

0.3

-

V

1.2

50

100

150

kΩ

[COMP pin characteristics]

COMP pin detection voltage

COMP pin pull-up resistor

External Thermistor resistor

V_COMP

R_COMP

R_T

0.370

19.4

3.32

0.500

25.9

3.70

0.630

32.3

4.08

V

kΩ

Latch release voltage

（VCC pin voltage）

V_LATCHOFF

T_COMP

-

V_UVLO2-0.5

150

-

V

Latch mask time

70

240

us

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●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)

Specifications

Parameter

[Quasi-resonant Control Block]

[Quasi-resonant DC/DC converter Block (turn off)]

Symbol

Unit

Conditions

Minimum

Standard Maximum

QR_FB pin pull-up resistance

R_FB

15

20

25

kΩ

CS over-current

detect voltage 1A

V_lim1A

0.950

1.000

1.050

V

I_zt<1.0mA

CS over-current

detect voltage 1B

V_lim1B

V_lim1C

V_lim1D

0.630

0.700

0.250

0.750

0.770

V

I_zt>1.0mA

I_zt<1.0mA

CS over-current

detect voltage 1C

-

CS over-current

detect voltage 1D

CS over-current

detect voltage 2A

CS switched ZT current

CS Leading

V_lim2A

I_ZT

-

0.800

-

0.150

1.000

0.250

-

1.200

-

V

QR_FB=0.3V (I_zt<1.0mA)

mA

us

T_LEB

Edge Blanking time

Turn off time

Minimum ON width

T_OFF

T_min

-

0.250

0.500

-

us

*1

T_LEB＋T_OFF

[Quasi-resonant DC/DC converter Block (turn on)]

Maximum operating

frequency 1

F_SW1

F_SW2

106

24

120

30

134

36

KHz

V

QR_FB=2.00V

QR_FB=0.50V

Maximum operating

frequency 2

Frequency reduction

start FB voltage

Frequency reduction

end FB voltage

V_FBSW1

V_FBSW2

1.15

0.35

1.250

0.50

1.350

0.65

V

⊿V (QR_FB)/⊿V

（QR_CS）

Voltage gain

AV_CS

1.70

2.00

2.30

V/V

ZT comparator voltage 1

ZT comparator voltage 2

ZT trigger timeout period

V_ZT1

V_ZT2

T_ZTOUT

60

300

-

100

400

15

140

500

-

mV

us

QR_ZT drop

QR_ZT rise

Count from final ZT trigger

[Quasi-resonant DC/DC converter protection functions]

Soft start time1

Soft start time2

FB OLP Voltage 1a

FB OLP Voltage 1b

T_SS1

T_SS2

V_FOLP1A

V_FOLP1B

0.60

2.60

2.5

-

1.00

4.00

2.8

1.40

5.40

3.1

-

ms

V

Operate QR_FB rise

Operate QR_FB drop

Switched latch / Auto

recovery rise

Switched latch / Auto

recovery drop

2.6

V

FB OLP Voltage 2a

FB OLP Voltage 2b

V_FOLP2A

V_FOLP2B

3.3

-

3.6

3.4

3.9

-

V

QR_FB

resistance value (during

latch mode)

external

FB OLP mode switched

external connected resistor

R_FOLP2

90

100

110

kΩ

FB OLP timer

ZT OVP Voltage

T_FOLP

V_ZTL

44

3.2

64

3.5

84

3.8

ms

V

[QR_OUT pin]

QR_OUT pin

PMOS ON resistor

QR_OUT pin

NMOS ON resistor

R_POUT

R_NOUT

5

2

15

5

30

10

Ω

[QR_SEL pin]

QR_SEL pin Ron

R_MASK

-

150

-

Ω

*1 Pulse is applied to QR_CS pin

*2 Pulse is applied to QR_ZT pin

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●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)

Specifications

Parameter

Symbol

Unit

Conditions

Minimum

Standard Maximum

[Power Factor Correction（PFC）controller block]

[Power Factor Correction (PFC) Gm amplifier block]

P_VS pin pull-up current

Gm amplifier normal voltage

Gm amplifier

trans-conductance

Maximum Gm amplifier

source current

I_{P_VS}

V_VSAMP

-

0.50

2.500

-

uA

V

2.460

2.540

V_VSGM

I_VSAMP1

I_VSAMP2

30.8

15

44.0

25

57.2

35

uS

uA

P_VS=1.0V

Maximum Gm amplifier

sink current

24

40

56

P_VS=3.5V

[Power Factor Correction (PFC) input voltage monitor block]

P_BO input voltage range

P_BO pin leak current

V_{P_BOIN}

I_BOLEAK

0.000

-1.00

-

1.800

1.00

V

uA

0.00

[Power Factor Correction (PFC) input voltage peak detect block]

P_BOPK max charge current

P_BOPK max

discharge current

I_BOPKCHG

I_BOPKDIS

36

72

144

0.4

uA

0.1

0.2

[Power Factor Correction (PFC) multiplier block]

Multiplier constant

P_VSEO stop voltage 1

P_VSEO stop voltage 2

K_MULTI

V_VSEO1

V_VSEO2

0.37

181

88

0.54

226

128

0.71

271

168

mV

BOPK=0.56V

BOPK=1.30V

[Power Factor Correction (PFC) Oscillation frequency block]

PFC Oscillation frequency

PFC Frequency hopping width

PFC hopping frequency

Minimum Pulse width

F_PSW1

F_PSWEL

F_PCH

T_min

D_max

60

-

75

-

65

4.0

125

500

94.0

70

-

175

-

KHz

Hz

ns

%

Maximum DUTY

90.0

98.0

[Power Factor Correction (PFC) Driver block]

P_OUT pin PMOS ON resistor

P_OUT pin NMOS ON resistor

RP_POUT

RP_NOUT

5

2

15

5

30

10

Ω

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●Electrical Characteristics (Unless otherwise noted Ta=25, VH_IN=320Vdc, VCC=12V)

Specifications

Parameter

Symbol

Unit

Conditions

Minimum

[Power Factor Correction (PFC) controller block ]

Standard

Maximum

[Power Factor Correction (PFC) protection function block ]

Leading Edge Blanking time

P_CS over current limit

voltage 1

P_CS over current limit

voltage 2

T_PLEB

V_PCS1

-

250

-

ns

V

0.93

1.16

1.40

P_BOPK=0.56V

P_BOPK=1.30V

V_PCS2

0.48

0.60

0.72

V

Figure of () is comparison

with P_VS standard voltage

2.5V

0.300

（-88%）

0.200

(-92%)

0.400

(-84%)

P_VS short protection voltage

V_{P_SHORT}

1.800

(-28%)

1.100

2.000

(-20%)

1.250

2.200

(-12%)

1.400

Figure of () is the ratio of

P_VS standard voltage 2.5V

Figure of () is the ratio of

P_VS standard voltage 2.5V

QR power-limit P_VS voltage1

QR power limit P_VS voltage2

V_PFCON

V

V_PFCOFF

(-56%)

(-50%)

(-44%)

P_VS QR power

limit hysteresis

0.750

(30%)

Figure of () is the ratio of

P_VS standard voltage 2.5V

V_PFCHYS

-

V

2. 250

（-10%）

2.625

（+5%）

2.725

2.050

(-18%)

2.450

(-2%)

Figure of () is the ratio of

P_VS standard voltage 2.5V

Figure of () is the ratio of

P_VS standard voltage 2.5V

Figure of () is the ratio of

P_VS standard voltage 2.5V

The time to detect P_VS

over voltage protection

P_VS gain rise voltage

P_VS gain fall voltage

V_PGUP

V_POVP1

V_POVP2

T_POVP2

V

-

P_VS over voltage

protection voltage

P_VS over voltage

protection timer

V

（+9%）

16

32

48

ms

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●PIN Configure

Table 1. I/O Pin Functions

Function

ESD protection system

NO

I/O

VCC

○

-

○

-

○

-

GND

○

-

○

-

1

2

P_BO

I

I/O

I

Input AC Voltage monitor pin

PFC gm amplifier output pin

PFC Output voltage monitor pin

Connected capacitor to the pin

PFC Coil current monitor pin

PFC ON/OFF control input pin

External latch stop pin

P_VSEO

P_VS

3

4

P_BOPK

P_CS

O

I

5

6

PFCON/OFF

COMP

ACDET

ACTIMER

GND

I

7

I

8

O

I

Input AC voltage state communication pin

Brown out detection time setting input pin

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O

O

I/O

O

I/O

I

P_OUT

GCLAMP

VCC

PFC Output drive pin

Gate H level clamp pin

Power supply pin

QR_OUT

QR_SEL

GND

Quasi-resonant Output drive pin

Quasi-resonant Mask pin

GND

QR_CS

QR_FB

QR_ZT

LATCH/AUTOR

VREF

Quasi-resonant Over current detected pin

Quasi-resonant Feedback detected pin

Quasi-resonant Zero cross detected pin

Protection mode switched input pin

Internal power supply pin

-

○

-

I

○

-

O

-

VH_IN

I

AC Input voltage applied pin

-

○

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●I/O Equivalent Circuit Diagram

Figure 2. I/O Equivalent Circuit Diagram

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●Block Diagram

+

FUSE

Diode

Bridge

AC

85-265Vac

Filter

P_VS

-

BD9212F

BD92XX

AND

+

-

AND

Internal

Supply

100k

-

+

-

QR_ZT

AND

-

+

-

OR

-

+

0.5V

GateClamp

+

-

ERROR

AMP

1/V_BOPK

+

-

MIN ON

WIDTH

Internal CLK

65kHz±4.0kHz

+

-

S

R

Q

RAMP

MAX DUTY

94%

15Ω

5Ω

+

-

PRE

Driver

AND

-

+

OR

*K2

*K3

+

-

×

+

-

1MΩ

P_VS

+

-

+

-

+

*K1

Leading Edge

Blanking

(250ns)

+

-

3.50V

STOP

QR_ZT

+

-

1

shot

AND

7V

OR

ZT Blanking

OUT(H->L) 0.60us

TimeOut

15 usec

100mV

/400mV

NOUT

1.25V

(

)

AND

S

R

MAX Blanking

Frequency

(120kHz)

+

-

OR

POUT

15Ω

Q

PRE

Driver

BURST_OH

AND

20kΩ

+

-

0.50V

NOUT

5Ω

Timer

(64ms)

+

-

1MΩ

FBOLP_OH

Soft

Start

+

-

200kΩ

FB/2

-

SS1ms

SS4ms

1.00V

+

Leading Edge

Blanking

(250ns)

CURRENT SENSE (V-V Change)

Normal ×1.0

:

Figure 3. Block Diagram

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AND

+

-

AND

Internal

Supply

100k

-

+

-

AND

-

+

-

OR

-

+

0.5V

GateClamp

+

-

1/V_BOPK

+

-

MIN ON

WIDTH

Internal CLK

65kHz±4.0kHz

S

R

+

-

Q

RAMP

MAX DUTY

94%

15Ω

5Ω

+

-

PRE

Driver

AND

-

+

OR

*K2

*K3

+

-

×

+

-

1MΩ

+

-

+

-

+

*K1

Leading Edge

Blanking

(250ns)

+

-

3.50V

STOP

+

-

1 shot

AND

7V

OR

ZT Blanking

OUT(H->L) 0.60us

TimeOut

( 15 usec )

100mV

/400mV

NOUT

1.25V

AND

S

R

MAX Blanking

Frequency

(120kHz)

+

-

OR

POUT

15Ω

Q

PRE

Driver

BURST_OH

AND

20kΩ

+

-

0.50V

NOUT

5Ω

Timer

(64ms)

+

-

1MΩ

FBOLP_OH

Soft

Start

+

-

200kΩ

FB/2

-

SS4ms

SS1ms

1.00V

+

Leading Edge

Blanking

(250ns)

CURRENT SENSE (V-V Change)

Normal : ×1.0

Figure 3-2. Block Diagram

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●Explanation of each block

(1) Starter block (24pin)

BM1050AF built in the starter circuit that withstands 650V. For that, application used the IC is enabled faster start time and

low standby power. After start-up, consumption power is idling current I_START3（typ=10uA）only.

Reference of start-up time is shown in Figure 6.

It can start-up less than 0.1sec when Cvcc=10uF.

Figure 4. Start Circuit Block Diagram

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0

5

10

15

20

25

30

35

40

45

50

Cvcc [uF]

Figure 5. Start-up current vs VCC voltage

*Start current flows from VH_IN pin to VCC pin.

Figure 6. Start time vs Cvcc (Reference values）

ex) When Vac=100V; consumption power of start-up circuit only.

PVH＝100V*√2*10uA=1.41mW

ex) When Vac=240V; consumption power of start-up circuit only.

PVH＝240V*√2*10uA=3.38mW

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(2) Start sequence

The start sequence of IC operates DC/DC part, next PFC part (See the figure 7).

A : Input voltage VH is applied.

B : Charge current flows from VH_IN pin to the VCC pin capacitor. Then VCC pin voltage rises.

C : Monitor the AC voltage by P_BO pin. And confirm normal state by releasing brown out.

D :When V_UVLO1（typ=13.5V） < VCC pin, release the inside UVLO and ON the inside regulator VREF.

E : When V_RUVLO1（typ=87.5%） < VREF pin, release the inside VREFUVLO.

F : If the ‘E’ state continues constant period, DC/DC part starts because it recognizes normal state.

When the switching starts, VOUT voltage rises.

When the DC/DC start-up, please set external parts to be regulated output voltage within the T_FOLPperiod (64ms .typ ).

[QR start-up operation]

G: This IC adjusts over current limiter of DC/DC by operation of soft start 1 against over voltage and current rising.

That term continues T_ss1(typ=1ms).

H: This IC adjusts over current limiter of DC/DC by operation of soft start 2 against over voltage and current rising.

Soft start 2 operation continues power limiter operation until P_VS pin voltage > V_PFCON(2.00V typ) and T_SS2（typ=4ms） .

This IC operates the state that maximum power of QR is 50% at this state.

I: If secondary voltage is setting value, QR_FB pin voltage is constant value corresponded load by current from photo coupler.

At normal state, QR_FB voltage is QR_FB<V_FBOLP1B(2.60V typ).

[PFC start up operation]

J: At the point in I time, This IC recognizes that the part of DC/DC operation is normal, Part of PFC starts operation.

K: If P_VS pin voltage is upper V_{P_SHORT}(typ = 0.3V), this IC judges short detection normal.

L: P_VSEO voltage rises from 0V to prevent from over rising voltage and current at PFC part.

At this time P_OUT pin DUTY increase from 0% with P_VSEO voltage increasing.

Figure 7. Start sequences Timing chart

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About figure7, condition is PFCON/OFF=L.

Start up operation is shown at figure8, 9 by the state shift figure.

Figure 8 is LATCH/AUTOR=L (auto return operation), and figure 9 is LATCH/AUTOR=H (LATCH operation)

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Figure 8. Diagram of state machine (LATCH/AUTOR=L)

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Figure 9. Diagram of state machine (LATCH/AUTOR=H)

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(3) VCC protection function and VREF pin function

(3-1) VCC pin protection function(13pin)

BM1050AF built in VCC low voltage protection function of VCCUVLO (Under Voltage Lock Out) and over voltage protection

function of VCC OVP (Over Voltage Protection).

This function monitors VCC pin and prevent VCC pin from destroying switching MOSFET at abnormal voltage.

VCCUVLO is auto recovery comparator that has voltage hysteresis. VCCOVP operates as latch mode comparator in the

LATCH/AUTOR=H and as auto return comparator in the LATCH/AUTOR=L.

VCC<V_LATCHOFF(typ = Vuvlo1 - 0.5) is condition of latch release (reset) after detection of latch operation by VCCOVP.

Refer to the operation figure10.

VCCOVP built in mask time T_COMP(typ=150us), in case of continuing VCCOVP 150us, operates over voltage detection.

By this function, this IC masks pin generated surge etc.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Figure10. VCC UVLO / OVP (LATCH/AUTOR=H at Latch stop)

A:VH input, VCC voltage rise

B:VCC>Vuvlo1,DC/DC operation start

C:VCC<Vuvlo2,DC/DC operation stop

D:VCC>Vuvlo1,DC/DC operation start

E:VCC voltage decreases until starting DC/DC switching

F:VCC rise

F:When VCC>Vovp1,DC/DC operation is stopped. Switching is stopped by internal latch signal.

G:Then DC/DC operation is stopped, power supply is lost from auxiliary, VCC voltage downs.

H:VCC<Vuvlo2, VCC voltage rises for dropping IC's consumption current.

I:VCC>Vuvlo1, this IC dose not operate DC/DC for latch operation. VCC voltage drops because of dropping of IC's consumption

current.

J:same of H

K:same of I

L:same of J

M:VH is open(the state is outlet out).VCC drops.

N:VCC <V_COMP, latch releases.

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(3-2) VREF pin function(21pin)

VREF pin is internal regulator output pin.

The use of VREF pin is IC's internal supply and connection of LATCH/AUTOR pin changing.

This pin needs an external capacitance, please use the capacitance following table.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Table 2. VREF pin output capacitor capacitance

Specification

Parameter

Symbol

Unit

uF

Conditions

Minimum

Standard Maximum

VREF Output Capacitor

C_REF

0.68

1.00 2.20

(3-3) VREF pin protection function(21pin)

VREF pin built in low voltage protection function VREF UVLO (Under Voltage Protection).

This IC prevents from error operating at the time, VREF starts up and VREF is low, by this function.

Figure11. VREF UVLO Function

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（3-4）Blown out function(1 pin)

BM1050AF built in blown out function. This function is that this IC stops DCDC operating at the time when input AC voltage is

low. Show the example figure12. This IC divides input voltage by the resistance, and input P_BO pin.

This IC detects from circuit normal state, and starts DC/DC operation the time when P_BO pin exceeds Vbo1(0.4V typ).

ACDET=L after TBO1(typ.32ms) or Tbo2(typ.128ms) from P_BO pin drops from VBO2(0.2V typ).

Moreover, if TBO3 (typ.250ms) passes from P_BO<VBO2, DC/DC part and PFC part is stopped.

About every resistance of fugure12, because P_BO pin is used PFC operation, please set Rbo1=4Mohm,Rbo2=16kohm for

operating the range of P_BO pin voltage 0~1.8V. In this case, by the following formula, P_BO=0V~0.56V at the case AC100V,

P_BO=0V~1.237V at the case AC220V.

R_BO2

P_BO =（ 2 ×V_ACV_F1）×

R_BO1+R_BO2

Then

２×V_ACꢀ>> V_F1

R_BO2

P_BO = ２× V_AC

×

R_BO1+R_BO2

Figure12. Block Diagram of Blown out Function

Figure13. Detection Way of Blown out Function

A : P_BO > V_BO1(typ.0.4V) 、ACDET=L->H

B: After 150us from A DC/DC part starts up.

C:QR_FB<V_FCLP1B（typ.2.6V）. PFC part starts up.

D: If PFC output is larger than constant voltage, ACTIMER=L->H.

E: P_BO<V_BO2(typ.0.2V) Timer start operation by detection blown out protection.

F:After T_BO1(typ.32ms) or T_BO(typ.128ms) from E, ACDET=H->L. It is possible to set T_BO1and T_BOat ACTIMER pin

２

G:After T_BO2(typ.250ms) from E, DC/DC part and PFC part are OFF

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(4)Controller part

(4-1)ACDET pin (8pin)

ACDET pin is NMOS open drain output. It monitors AC voltage, and is used for controlling secondary micon.

Show the using example figure14, 15. Please set VIN is H voltage of micon.

ACDET=L ： Abnormal state（P_BO < 0.2V）

ACDET=H ： Normal state

Figure14. Using Example of ACDET Pin

Figure15. Explanation of ACDET Pin

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Next, show an easy sequence.

Figure16. At applied AC Input Voltage（P_BO voltage<0.4V）

Because P_BO < 0.4V, DC/DC part is OFF.

VCC voltage>13.5V

Figure17. At applied AC Input Voltage（P_BO voltage >0.4V）

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A：Detect P_BO＞0.4V, Quasi resonance starts operation After 150μs

B：PFC start up

C：PFC output stabilized

*About PFC operation, by the micon, is able to be controlled using PFCON/OFF pin.

Figure18. At AC Power Supply OFF

A：Detect P_BO＜0.2V, internal ACDET timer operates. At this time, output of PWC downs.

B：After 32ms （ACTIMER=L） from the point A, ACDET pin voltage is H->L, send to the μ-controller abnormal signals.

C：After 250ms from the point of A,PFC and Quasi Resonant are stopped

Figure19. At AC Power Supply the case of operation moment stop

The case of AC voltage is OFF suddenly, constant area is masked.

The time of constant area of masking is depends on ACTIMER pin.

The case of ACTIMER pin=L, Mask time=32ms、 the case of ACTIMER pin=H, mask time=128ms.

The moment of AC voltage momentary power interruption, because PFC output voltage is down by corresponding to load,

please watch out.

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(4-3) PFCON/OFF pin

PFCON/OFF pin is NMOS gate input pin. Refer to following the functions.

An internal timer is integrated for noise protection on PFCON/OFF pin.

After T_PFCON/OFF(typ.1ms) from PFCON/OFF H→L, PFCON/OFF L operation starts. At PFCON/OFF L→H, internal timer is not

integrated.

function1）PFC circuit operation is OFF control.

In order to reduce standby power, IC controls PFC part operation at PFCON/OFF pin.

function2）QR_SEL pin is Hi-z→L

Refer to example of using at figure 20.

PFCON/OFF=L ： DC/DC part＝ON、 PFC part＝ON、QR_SEL＝Hi-Z

PFCON/OFF=H ： DC/DC part＝ON、 PFC part＝OFF、QR_SEL=L

VREF

LOGIC

PFC

ON/OFF

uCOM

PC

Controlled by Nch OPEN-drain

Plimary Side

Secondary Side

Figure20. Using example of PFCON/OFF pin

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(4-4) LATCH/AUTOR pin

LATCH/AUTOR pin is NMOS gate input pin. Refer to example of using at figure21.

Operation setting of protection function is shown at table3.

LATCH/AUTOR=L ： Auto recovery

LATCH/AUTOR=H ： Latch

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Figure21. Using example of LATCH/AUTOR pin

LATCH/AUTOR=GND

LATCH/AUTOR

ITEM

VREFUVLO

VCCUVLO

VCCOVP

Contents

detection

method

operation

release

mothod

operaetion

at detection

detection

method

operation

at detection

release

mothod

operaetion

at detection

VREF PIN

ꢀLow voltage protection

function

PFC part, DC/DC

part operation

stops

PFC partDC/DC

part

ꢀenable to operate

VREF<2.5V

（VREF falling）

VREF>3.5V

ꢀ（VREFrising）

same as LATCH/AUTOR=GND

VCC PIN

ꢀLow voltage protection

function

PFC part, DC/DC

part operation

stops

PFC partDC/DC

part

ꢀenable to operate

VCC<7.0V

（VCC falling）

VCC>13.5V

ꢀ（VCC rising）

VCC PIN

VCC>27V state

PFC part, DC/DC

ꢀOver voltage protection continues between part operation

PFC partDC/DC

part

ꢀenable to operate

PFC part, DC/DC

part latch operation

stops

PFC part,

DC/DCpart enable

to operate

VCC<23.0V

ꢀ（VCCfalling）

VCC>27V

（VCC rising）

VCC<6.5V

ꢀ（VCC falling）

function

150us（VCC rising） stops

P_BO＜0.2V state

continues between

250ms

Input AC voltage

ꢀLow voltage protection

function

PFC part, DC/DC

part operation

stops

PFC partDC/DC

part

ꢀenable to operate

P_BO>0.4V

ꢀ（P_BOrising）

same as LATCH/AUTOR=GND

blown out

QR_FB>2.8V state

continues between

250ms（QR_FB

QR_FB pin

DC/DC part

ꢀoperation stops

QR_FB<2.6V

ꢀ（QR_FB falling）

QR_FB_OLP1 ꢀOver current protection

function

normal operation

QR_FB pin

QR_FB_OLP2 ꢀOver current protection

function

QR_FB>3.6V

（QR_FB rising）

DC/DC part

ꢀoperation stops

QR_FB<3.4V

ꢀ（QR_FB falling）

QR_ZT>3.5V state

continues between

150us（QR_ZT

QR_ZT>3.5V state

continues between

150us（QR_ZT

QR_ZT pin

ꢀOver voltage protection

function

PFC part, DC/DC

part latch operation

stops

DC/DC part

ꢀoperation stops

QR_ZT<3.5V

ꢀ（QR_ZT falling）

VCC<6.5V

ꢀ（VCC falling）

QR_ZT OVP

normal operation

P_VS pin

ꢀShort protection

function

P_VS short

protection

P_VS<0.30V

（P_VS falling）

PFC part

ꢀoperation stops

P_VS>0.30V

ꢀ（P_VS rising）

same as LATCH/AUTOR=GND

P_VS pin

ꢀLow voltage gain

increasing function

P_VS GAIN

increasing

P_VS<2.25V

（P_VS falling）

GM AMP GAIN

increasing

P_VS>2.25V

ꢀ（P_VS rising）

P_VS pin

ꢀOver voltage protection

function1

P_VS>2.625V

（P_VS rising）

GM AMP GAIN

falling

P_VS<2.625V

ꢀ（P_VS falling）

P_VSꢀOVP1

P_VSꢀOVP2

COMP function

P_VS pin

ꢀOver voltage protection

function2

PFC part, DC/DC

part latch operation

stops

P_VS>2.725V

（P_VS rising）

P_VS<2.600V

ꢀ（P_VS falling）

P_VS>2.725V

（P_VS rising）

VCC<6.5V

ꢀ（VCC下降時）

PFC part stops

normal operation

COMP<0.5V state

continues between

150us（COMP

COMP<0.5V state

continues between

150us（COMP

PFC part, DC/DC

part operation

stops

PFC part, DC/DC

part latch operation

stops

COMP pin

ꢀProtection function

COMP>0.50V

ꢀ（COMP rising）

VCC<6.5V

ꢀ（VCC falling）

Table 3. List of Protection Function Operation Setting by LATCH/AUTOR pin

*Comparator level of protection function is shown by TYP value.

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(4-5) ACTIMER pin

ACTIMER pin is NMOS gate input pin. Show example of using figure 22, 23

Set the detect timer of AC voltage drop. （please refer to ACDET pin page）

Figure22. Using example of ACTIMER pin

ACTIMER=GND

: 32ms Timer

ACTIMER=VREF :128ms Timer

Figure23. AC power at the case momentary power interruption OFF

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(4-6) COMP pin（external stop control function）

COMP pin is stop control pin. When COMP pin voltage drops from V_COMP(0.5V. typ), COMP pin stops PFC and DC/DC part

operation.

This IC built in T_COMP(150us .typ) until stopping switching, prevent from stopping by noise.

COMP pin is in pull-up resistor R_COMP(25.9kΩ. typ), When COMP pin is the state of pull-down with lower resistance than

R_T(3.70kΩ.typ), COMP pin detects abnormal. Show application examples at the figure24, 25, and 26.

Temperature protection by NTC thermister

By putting a thermister at the COMP pin, it is possible to stop latch on temperature rising.

The case of this application, please design thermister resister is R_T(3.70kΩ.typ) on temperature detection.

（Figure24 and 25 is application circuit that latch on Ta=110℃）

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

20.0

18.0

16.0

14.0

12.0

10.0

8.0

6.0

4.0

2.0

0.0

R_Tt(typ3.7kΩ)

Detect

0

20

40

60

80 100 120 140 160 180 200

Temparature T[℃]

Figure 24. Temperature Protection Application

Figure 25. Temperature–Thermistor Resistor characteristic

Secondary over- voltage protection

This IC can detect secondary over-voltage by putting photo coupler to COMP pin.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Figure26.Output Over Voltage Protection Application

Table 4. Changes of COMP function Operation by LATCH/AUTOR pin

LATCH/AUTOR=GND

LATCH/AUTOR=VREF

ITEM

contents

detection

method

operation

release

operaetion

detection

method

operation

release

operaetion

at detection

mothod

at detection

mothod

at detection

COMP<0.5V state

continues between

150us（COMP falling）

COMP<0.5V state

PFC part, DC/DC

COMP pin

PFC part, DC/DC

COMP>0.50V

P_VCC<6.5V

COMP function

normal operation

continues between part latch operation

150us（COMP falling） stops

normal operation

ꢀprotection function

part operation stops ꢀ（COMP rising）

ꢀ（P_VCC falling）

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(5)Quasi-Resonant DC/DC converter function

Part of quasi-resonant DC/DC uses PFM(Pulse Frequency Modulation)mode control.

The QR_FB pin, QR_ZT pin and QR_CS pin are monitored to provide a system optimized for DC/DC."

The switching MOSFET ON width (turn OFF) is controlled via the QR_FB pin and QR_CS pin, and the OFF width(turn ON).

Show following detail explanation. (refer to figure27).

Figure27. Diagram of Quasi-resonant DC/DC Operation

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(5-1) Determination of ON width (turn OFF)

ON width is controlled via the QR_FB pin and QR_CS pin.

The QR_FB pin voltage is compared with the IC internal voltage V_lim1(1.0V typ) and, as is shown in Figure28.

And the comparator level changes linearly.

The QR_CS pin is also used for the pulse-by-pulse over current limiter circuit.

By changing voltage at the QR_FB pin, DC/DC results in changes of the maximum blanking frequency and

over-current limiter level.

・mode1: Burst operation

・mode2: Frequency reduction operation(reduces maximum frequency)

・mode3: Maximum frequency operation(operates at maximum frequency)

・mode4: Overload operation(pulse operation is stopped when overload is detected)

(a) I_zt<1.0mA

(b) I_zt>1.0mA

Figure 28. Relation of QR_FB pin, over current limiter and maximum frequency

The over current limiter level is adjusted, when the input voltage is changed, operate the soft start function.

In this case, the Vlim1 and Vlim2 values are as listed below."

Table 5. current protection voltage of Quasi-resonant DC/DC

AC=100V

AC=230V

Soft start

Vlim1

Vlim2

Vlim1

Vlim2

Start～1ms

0.250V ( 25.0%)

0.750V ( 75.0%)

1.000V (100.0%)

0.039V ( 3.9%)

0.113V ( 11.3%)

0.150V ( 15.0%)

0.176V ( 17.6%)

0.525V ( 52.5%)

0.700V ( 70.0%)

0.026V ( 2.6%)

0.079V ( 7.9%)

0.105V ( 10.5%)

1ms～PFC Start &4ms

PFC Start & 4ms～

*( ) is AC=100V, these show relative value of compare with V_lim1（1.0Vtyp） of normal operation.

This table is separated AC100V and AC230V for the function of QR_CS current changing function that is shown （4-3）.

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(5-2)LEB(Leading Edge Blanking)function

When the switching MOSFET is turned ON, surge current occurs at each capacitor charge /discharge or drive current.

For that, QR_CS voltage rise temporarily, over current limiter may be detected errors.

To prevent detection errors blanking time is built in to mask T_LEB(typ=250ns).

This blanking function enables a reduction of CS pin filtering.

(5-3) CS over current protection function

When the AC input voltage (VHIN) is high, the ON time is reduced and the operating frequency increases. As a result, the

maximum rated power is increased for a constant over current limiter level. As a countermeasure, DC/DC is switched over

current detected level.

AC input voltage detection method is that monitoring QR_ZT current.

When MOSFET is turn ON, the auxiliary voltage (Va) is the minus voltage that depends on input voltage（VH）.

QR_ZT pin is clamped about 0V internal IC.

Following is the formula for that case.

Refer to the block figure29. See the graph figure30 and 31.

Izt ＝（Va－Vzt）/Rzｔ1 ≒ Va/Rzｔ1 ＝ VH * Na/Np /Rzｔ1

Rzt1 ＝ Va/Izt

For that, VH voltage is set by the resistance value of R_zt1. Then, QR_ZT bottom detection voltage is decided, Please set timing

by Czt.

NOUT

+

-

+

-

1 shot

+

-

OR

AND

TimeOut

( 15 usec )

7V

POUT

NOUT

ZT Blanking

OUT(H->L)

0.60us

100mV

/400mV

S

R

AND

Q

NOUT

PRE

Driver

FBOLP_OH AND

MAX

Blanking

Frequency

(120kHz)

+

-

1.25V

20k

+

-

0.30V

FBOLP_OH

Timer

(250ms)

+

-

+

-

Soft Start

200kΩ

FB/2

-

1.00V

SS4ms

SS1ms

+

Leading Edge

Blanking

CURRENT SENSE (V-V Change)

Normal : ×1.0

Figure 29. Diagram of CS switching current

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Figure 30. QR_CS Switching QR_FB Voltage VS QR_CS Voltage Figure 31. QR_CS Switching Izt Current VS QR_CS

Voltage

ex) setting method（operate changing AC100V and AC220V）

AC100V 141V±42V（±30％ margin）

AC220V 308V±62V（±20％ margin）

The case of above, Between 182V～246V, operates changing of CS current => Operate VH＝214VH

Np=100, Na=15

Va=Vin*Na/Np = 214V*15/100 *(-1) = -32.1V

Rzc = Va/ I_ZT= -32.1V/-1mA = 32.1kΩ

By the above explanation, Rzt=32KΩ

Figure 32. Example of Over current limiter of CS switching

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(5-4) Determination of OFF width(turn ON)

OFF width is controlled at the QR_ZT pin.

When switching is OFF, the power stored in the coil is supplied to the secondary-side output capacitor.

When this power supply ends there is no more current flowing to secondary side, so the switching MOS drain pin voltage drops.

Consequently, the voltage on the auxiliary coil side also drops.

A voltage that was resistance-divided from the QR_ZT pin by Rzt1 and Rat2 is applied. When this voltage level drops to

Vzt1(100mV typ) or below, switching is turned ON the QR_ZT comparator. Since bottom status is detected at the QR_ZT pin,

time constants are generated using Czt, Rzt1, and Rzt2.

Additionally, a QR_ZT trigger mask function (described in section 5-5) and a QR_ZT time out function

(described in section 5-6) are built in.

(5-5)QR_ZT trigger mask function

The QR_ZT trigger mask function is shown below figure33.

When switching is set ON -> OFF, super position of noise may occur at the QR_ZT pin.

At such times, the QR_ZT comparator is masked for the T_ztmasktime to prevent QR_ZT comparator operation errors.

Figure 33. ZT trigger mask Function

A: QR_OUT OFF=>ON

B: QR_OUT ON=>OFF

C: Because of generation of QR_ZT pin noise, T_ZTMASKdoesn’t operate the QR_ZT comparator.

D: Same as A

E: Same as B

F: Same as C

G: Same as A

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(5-6)ZT time out function(Figeure34)

After the ZT comparator is detected, this function forcibly turns switching ON if the following is not detected, even when T_ztout

(15us typ) has elapsed.

If, the secondary output voltage is low, the auxiliary coil voltage VA is reduced, and the QR_ZT pin voltage drops below V_zt1

(100mVtyp).

In such cases, this function turns switching ON forcibly.

As for T_ztout, since 15 us (typ) = 66.7kHz, when the maximum frequency is in frequency reduction mode, the QR_ZT timeout time

depends on the frequency reduction mode

Figure 34. ZT Time out Function

A: QR_ZT＜V_ZT1、DC/DC is ON. Count maximum frequency at this point.

B: DC/DC ON=>OFF

C: Because noise is generated at QR_ZT pin, T_ZTMASKdoesn’t operate QR_ZT comparator.

D: DC/DC OFF=>ON

E: Same as B

F: Same as C

G: Count maximum frequency

H: Because 1cycle>T_ZTOUT, forcibly be DC/DC OFF=>ON

(5-7)Soft start operations

Normally, when the power supply is turned ON, a large current flows to the AC/DC power supply. The BM1050AF builds-in a

soft start function to prevent large changes in the output voltage and output current during startup.

this function is reset when the VCC pin voltage is at

power-on.

V_UVLO2(7.0V typ) or below, soft start is performed again at the next AC

During a soft start, the following post-startup operations are performed. (See turn OFF described in section 5-1)

Start to 1ms -> Set to 25% when CS limiter value is normal

1ms PFC normal status -> Set to 75% when CS limiter value is normal

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(5-8)Overload protection function/Overload protection mode switching

The overload protection function monitors the overload status of the secondary output current at the FB pin, and fixes the OUT

pin at low level when overload status is detected.

During overload status, current no longer flows to the photocoupler, so the QR_FB pin voltage rises.

When this status continues for the T_FOLPtime (64ms typ), it is considered an over load, and the OUT pin is fixed at low level.

Once the QR_FB pin voltage exceeds V_FOLP1a(2.8V typ), if it drops to lower than V_FOLP1b(2.6V typ) during the T_FOLPtime (64ms typ),

the overload protection timer is reset. At startup, the QR_FB voltage is pulled up to the internal voltage by pull-up resistor, and

operation starts once the voltage reaches V_FOLP1a(2.8V typ) or above. Therefore, the design must set the QR_EB voltage at or

below the V_FOLP1b(2.6V typ) voltage within the T_FOLP(64ms typ) time. In other words, the secondary output voltage start time must

be set to within T_FOLP(64ms typ) after IC startup.

When an overload is detected, either auto recovery mode or latch mode can be selected for the BM1050AF.When pull-down

resistance R_FOLP(100kΩ typ)is attached to QR_FB pin, latch mode is set. Do not attach any R_FOLPvalue other than 100kΩtyp,

since that would prevent latching due to the IC7s internal resistance ratio.

To release latching after selecting latch mode, first unplug the power supply, and then set VCC<V_LATCH(typ=6.5V) to release

latching.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

(5-9)QR_ZT pin OVP(Over Voltage Protection)

An OVP（Over Voltage Protection) function is built in for the QR_ZT pin.

When the QR_ZT pin voltage reaches V_ZLT(TYP=3.5V),over voltage status is detected. QR_ZT pin OVP protection performed

latch mode.

A mask time defined as T_LATCH(TYP=150us) is built in for the QR_ZT pin OVP function. When QR_ZT OVP status continues for

150us, overvoltage is detected. This function masks any surges (etc.) that occur at the pin. See the illustration in Figure 35.

(Like VCC OVP, T_LATCH(TYP=150us) is built in)

Figure 35. ZTOVP and Latch mask Function

A: DC/DC pulse operates. QR_ZT pin operates too.

B: QR_ZT pin voltage＞V_ZTL(TYP=3.5V)

C: QR_ZT pin voltage＞V_ZTL(TYP=3.5V) state within T_COMP（typ=150us）, returns to normal DC/DC operation.

D: QR_ZT pin voltage＞V_ZTL(TYP=3.5V)

E: QR_ZT pin voltage＞V_ZTL(TYP=3.5V) state continues T_COMP（typ=150us）, operates latch and DC/DC OFF.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

(5-10) Quasi-resonant DC/DC block protection operation mode

Show every protection function operation mode table 6.

FB pin over load protection function is able to change AUTR/LATCH by FB pin pull down resistance.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Table 6. Protection Circuit Operation Mode of Quasi-resonant DC/DC

LATCH/AUTOR=GND

release

mothod

LATCH/AUTOR=VREF

operation

at detection

ITEM

contents

detection

method

operation

at detection

operaetion

at detection

detection

method

release

mothod

operaetion

at detection

QR_FB pin

ꢀover current protection

function

QR_FB>2.8V state

continues 250ms

（QR_FB rising）

DC/DC part

ꢀoperation stop

QR_FB<2.6V

ꢀ（QR_FB falling）

QR_FB_OLP1

normal operation

same as LATCH/AUTOR=GND

QR_FB pin

ꢀover current protection

function

QR_FB>3.6V

（QR_FB rising）

DC/DC part

ꢀoperation stop

QR_FB<3.4V

ꢀ（QR_FB falling）

QR_FB_OLP2

QR_ZT OVP

QR_ZT ipn

ꢀover voltage protection

function

QR_ZT>3.5V state

continue 150us

（QR_QR_ZTrising）

QR_ZT>3.5V state

continues 150us

（QR_ZT rising）

DC/DC part

ꢀLATCH operation

stop

DC/DC part

ꢀoperation stop

QR_ZT<3.5V

ꢀ（QR_ZT falling）

VCC<6.5V

ꢀ（VCC falling）

normal operation

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(6)Power Factor Correction Circuit (PFC: Power Factor Correction)Part

Power Factor Correction Circuit is peak current control method of fixed frequency.

It is possible to supply proper system as PFC by monitoring P_VS pin, P_CS pin, and P_BO.

It is possible to control the MOSFET ON width by monitoring output voltage at P_VS pin, AC input voltage at P_BO pin, and

MOSFET current at P_CS pin.

The switching frequency is F_PSW1(typ=65kH),built in frequency hopping function (±4kHz),and contribute to low EMI. Following is

detail explanation of PFC (reference figure36).

+

Diode

Bridge

AC

85-265Vac

P_VS

CM

-

0.01uF

P_BOPK

Peak

Hold

I

IO

P_BO

VSOVP2_OK

VSOVP1_OK

+

-

GCLAMP

IO

1/V

*K3

2.725V(+9%)

S

R

MIN ON

WIDTH

Internal CLK

65kHz±4kHz

+

-

2.625V(+5%)

VM = K1*V(P_BO)* K2*V(P_VS)*K3/V(P_BOPK)*K4

≒K * V(P_BO) * V(P_VS) / V(P_BOPK)

Q

P_OUT

MAX DUTY

94%

15Ω

VSGUP_OK

VPFC_ON

+

-

PRE

Driver

O

AND

OR

-

+

*K2

*K4

×

2.25V(-10%)

NGB

+

-

1MΩ

P_GND

5Ω

2.00V(-20%) / 1.25V(-50%)

+

P_VS

IO

-

VSSHORT_OK

+

-

0.30V(-88%)

P_VS

I

-

+

*K1

P_CS

V_PCS

Leading Edge

Blanking

(250ns)

I

2.500V

P_VSEO

RS

O

Figure 36. Diagram of PFC block

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(6-1) gm AMP

P_VS pin monitors a divide voltage between resistors of PFC output voltage. P_VS pin is piled up ripple voltage of AC

frequency (50kHz/60kHz).

The gmAMP filters this ripple voltage and controls the voltage level of P_VSEO, by responding to error of P_VS pin voltage

P_VS pin voltage and internal reference voltage V_VSAMP(typ 2.5V).

Please set cut-off frequency of filter at P_VSEO pin showed in figure 37, to about 5~10Hz.

Gm constant is designed 44[uA/V].

Figure 37. Diagram of gmAMP

(6-2)Monitor of input voltage

PFC is monitored AC input voltage at the P_BO pin.

Because the range of input voltage at P_BO pin is 0~1.8V, please select Rbo1 and Rbo2 to set P_BO voltage in the range.

Refer to block figure at figure38.

Figure 38. Diagram of Input Voltage Monitor

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(6-3)Maximum power limiting function

PFC maximum power is also larger as input voltage is larger.

To compensate this maximum power, PFC built-in Maximum power limiting.

Maximum power is in proportion to the square of output of multiplier V_MULT, so it is possible to correct that maximum power

depends on input voltage by dividing P_BO voltage by P_BOPK voltage which is peak voltage of P_BO pin.

P_BOPK

0.01uF

PEAK

HOLD

IO

I

P_BO

1/V

VM = K1* V(P_BO) * K2* V(P_VS)/{K3*V(P_BOPK)}*K4

≒K * V(P_BO) * V(P_VS )/V(P_BOPK)

*K2

×

*K3

P_ VS

P_VS

I

-

+

*K1

2.500V

P_ VSEO

O

Figure 39. Diagram of Maximum Power Restriction Function

(6-4)Multiplier

A multiplier is calculated gmAMP output voltage and P_BO pin voltage, and P_BOPK pin voltage.

Following is formula of Multiplier output.

K1



V(P_BO) K₂ V(P_VSEO)



V_MULT



K₃ V(P_BOPK)





ꢀꢀ K  V(P_BO) V(P_VSEO)/（V(P_BOPK)）

V

_MULT: Multiplier output voltage K: Multiplier constant

(6-5) Switching frequency

Switching frequency is averaged typ.65kHz. MAX DUTY is D_MAX(typ 94%), always the period has OFF width.

PFC built in frequency hopping function, frequency changes every 500us. The amplitude is F_PSWEL(typ=±4kHz)

The cycle is F_PCH(typ = 125Hz)( figure40).

By this function, frequency spectrums are diffused, and contribute to low EMI.

Switching Frequency

[kHz]

69 kHz

65 kHz

61 kHz

125 Hz

Time

Figure 40. Frequency Hopping Function

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(6-6)LEB(Leading Edge Blanking) function

When the switching MOSFET is turned ON, surge current occurs at each capacitor charge /discharge or drive current.

For that, P_CS voltage rise temporarily, over current limiter may be detected errors.

To prevent detection errors blanking time is built in during T_PLEB(typ=250ns) from P_OUT pin changing L →H..

This blanking function enables a reduction of P_CS pin noise filter.

(6-7) Over current protection function

P_CS pin built in over current protection function for MOSFET. This function operates in pulse by pulse, and detects over

current. Over current detection voltage is changed by P_BOPK pin voltage. Over current detection voltage is V_PCS1(typ = 1.16V)

at P_BOPK voltage =0.56V, V_PCS2(typ = 0.60V) at P_BOPK voltage = 1.30V.

Show figure41 changing of over current detection voltage by P_BOPK pin voltage.

Over-current detection value I_PCSis decided I_PCS=V_PCS/R_sby external resistance Rs at figure42.

Figure 41. Over-current detection Voltage - P_BOPK Voltage Peculiarity

Leading Edge

+

Blanking

(250ns)

-

Figure 42. Diagram of Over current Protection

(6-8)P_VS short protection function

PFC built in short protection function at P_VS. Switching is stopped at P_VS voltage<V_{P_SHORT}(0.30Vtyp).

Figure 43. P_VS Short Protection Operation

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(6-9) Gain increase function in P_VS low voltage

Dropping output voltage by suddenly load change, because PFC voltage response is slow, output voltage is low for a long time.

Therefore, PFC is speed up voltage control loop gain when P_VS pin voltage is low up to V_PGUP(typ = 2.25V)(Output voltage -

10%). In the operation, ON-duty at P_OUT pin increases, PFC prevents from output voltage dropping for a long time.

This operation is stopped when P_VS pin voltage is upper than V_GUP(typ=2.25V).

(6-10)P_VS first over voltage protection function

In case of output voltage is rise by starting up or output load suddenly change, because PFC voltage response is slow, output

voltage is high for a long time. Therefore, PFC is speed up voltage control loop gain when P_VS pin voltage is rise V_{P_OVP1}

(typ=2.625). In this operation, ON-duty at P_OUT pin decrease, PFC prevents from output voltage rising for a long time.

This operation is stopped when P_VS pin voltage is lower than Vp_ovp1(typ=2.625V).

(6-11)P_VS second over voltage protection function

PFC built in second over voltage protection, for the case that P_VS voltage exceeds over first over voltage protection voltage

V_{P_OVP1}. It is possible to switch Latch protection (LATCH/AUTOR=H) or auto recovery (LATCH/AUTOR=L) by LATCH/AUTOR pin.

In case of latch operation, P_VS pin voltage exceeds V_{P_OVP2}(typ=2.725V)(output voltage pulse9%) during T_{P_OVP2a}(Typ=32ms),

PFC switching is stopped.

In case of auto recovery, P_VS pin voltage is exceeded V_{P_OVP2}(typ=2.725V), switching is stopped instantly. When P_VS pin

voltage decrease lower than V_{P_OVP2}(typ=2.725V), switching operation is re-start. Refer to figure44.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Figure 44. VS Second Over Voltage Protection (at auto recovery mode)

Figure 45. Operation of P_VS Second Over Voltage Protection (at latch mode)

Switching is stopped by second over voltage protection in the case that the P_VS pin loop of output voltage is open loop.

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(6-12)PFC burst operation

PFC built-in burst operation for preventing PFC output voltage from rising at light load.

This function is that PFC monitors P_VSEO pin at light load, switched burst operation or not.

Burst operation voltage depends on P_BOPK voltage.

In case of P_BOPK voltage = 0.56V, burst function operates when P_VSEO voltage is lower than

VSEO=V_{P_BURST}(0.266V typ). In case of P_BOPK voltage = 1.30V, burst function operates when P_VSEO voltage is lower than

VSEO=V_{P_BURST1}(0.128V typ)

Refer to the change of burst voltage for P_BOPK voltage figure46.

Figure 46. Diagram of P_VSEO burst voltage by P_BOPK voltage

(6-13) Operation mode of PFC block protection

Show operation mode every protection function at Table7.

(Note) When the latch mode is used, it is necessary to apply 3.5V~4.5V to VREF terminal from the outside.

Table 7. Protection Circuit Operation mode of PFC

LATCH/AUTOR=GND

release

mothod

LATCH/AUTOR=VREF

operation

at detection

ITEM

contents

detection

method

operation

at detection

operaetion

at detection

detection

method

release

mothod

operaetion

at detection

P_VS SHORT

PROTECTION

P_VS PIN P_VS<0.30V

ꢀshort protection function （P_VS falling）

PFCpart

ꢀoperation stop

P_VS>0.30V

ꢀ（P_VS rising）

normal operation

Same as LATCH/AUTOR=GND

P_VS PIN

P_VS GAIN

INCREASING

P_VS<2.25V

GMAMP GAIN

INCREASE

P_VS>2.25V

ꢀ（P_VSrising）

ꢀlow voltage gain increasing

（P_VS falling）

function

P_VS PIN

P_VS>2.625V

ꢀover voltage protection

（P_VS rising）

function1

GM AMPGAIN

DECREASE

P_VS<2.625V

ꢀ（P_VS falling）

P_VSꢀOVP1

P_VSꢀOVP2

P_VS PIN

PFC part, DC/DC

part latch operation

stops

P_VS>2.725V

ꢀover voltage protection

（P_VS rising）

function2

PFC part

ꢀoperation stop

P_VS<2.725V

ꢀ（P_VS falling）

P_VS>2.725V

（P_VS rising）

VCC<6.5V

ꢀ（VCC falling）

normal operation

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● Basic Characteristics (This data is for reference only and is not guaranteed.)

1.7

1.5

1.3

1.1

0.9

0.7

1.3

1.2

1.1

1.0

0.9

0.8

0.7

2.8

2.4

2.0

1.6

1.2

0.8

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-1 Circuit current (ON) 1

Fig-47-2 Circuit current (ON) 2

Fig-47-3 Circuit current (ON) 3

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

15.0

0.9

0.7

0.5

0.3

0.1

13.0

11.0

9.0

7.0

5.0

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-4 Start current 1

Fig-47-5 Start current 2

Fig-47-6 OFF Current

1.4

1.2

1.0

0.8

0.6

0.4

4.5

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-7 VH voltage switched start current Fig-47-8 VREF output voltage

Fig-47-9 GCLAMP voltage 1

8.5

8.0

7.5

7.0

6.5

6.0

5.5

30.0

29.0

28.0

27.0

26.0

25.0

24.0

14.5

14.0

13.5

13.0

12.5

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-10 VCC UVLO voltage 1

Fig-47-11 VCC UVLO voltage 2

Fig-47-12 VCC OVP voltage 1

0.45

0.43

0.41

0.39

0.37

0.35

0.25

0.23

0.21

0.19

0.17

0.15

26.0

25.0

24.0

23.0

22.0

21.0

20.0

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-13 VCC OVP voltage 2

Fig-47-14 Brown out detection voltage 1 Fig-47-15 Brown out detection voltage 2

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● Basic Characteristics (This data is for reference only and is not guaranteed.)

0.25

42

167

157

147

137

127

117

107

97

0.23

37

0.21

32

0.19

27

0.17

0.15

22

87

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-16 Brown out hysteresis Fig-47-17 Brown out detection delay time 1 Fig-47-18 Brown out detection delay time 2

330

310

290

270

250

230

210

190

170

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

190

170

150

130

110

90

70

50

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-19 Brown out detection delay time 3

Fig-47-20 ACDET pin ON resister Fig-47-21 ACTIMER pin input level

1.2

150

130

110

90

465

415

365

315

265

215

165

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

70

50

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-22 ACTIMER pin pull-down res. Fig-47-23 PFCON/OFF pin input level Fig-47-24 PFCON/OFF pin pull-down res.

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

150

130

110

90

0.62

0.57

0.52

0.47

0.42

0.37

70

50

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-25 LATCH/AUTOR pin input level Fig-47-26 LATCH/AUTOR pin pull-down res. Fig-47-27 COMP pin detection voltage

8.0

4.0

31.4

7.5

3.9

29.4

7.0

6.5

6.0

5.5

5.0

3.8

3.7

3.6

3.5

3.4

3.3

27.4

25.4

23.4

21.4

19.4

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-28 COMP pin pull-up resistor

Fig-47-29 External Thermistor resistor Fig-47-30 Latch release voltage2

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● Basic Characteristics (This data is for reference only and is not guaranteed.)

25

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

230

210

23

190

21

19

17

15

170

150

130

110

90

70

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-31 Latch mask time

Fig-47-32 QR_FB pin pull-up resistance

Fig-47-33 CS over-current detect voltage 1A

0.85

0.30

0.29

0.28

0.27

0.26

0.25

0.24

0.23

0.22

0.21

0.20

0.77

0.75

0.73

0.71

0.69

0.67

0.65

0.63

0.80

0.75

0.70

0.65

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-34 CS over-current detect vol.1B Fig-47-35 CS over-current detect vol.1C Fig-47-36 CS over-current detect vol.1D

0.25

0.50

0.40

0.30

0.20

0.10

1.20

1.10

1.00

0.90

0.80

0.20

0.15

0.10

0.05

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-37 CS over-current detect vol. 2A

Fig-47-38 CS switched ZT current Fig-47-39 CS Leading Edge Blanking time

36

0.75

0.65

0.55

0.45

0.35

0.25

131

34

126

32

121

30

116

28

111

106

26

24

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-40 Minimum ON width

Fig-47-41 Maximum operating frequency 1 Fig-47-42 Maximum operating frequency 2

0.65

0.60

0.55

0.50

0.45

0.40

0.35

2.30

2.20

2.10

2.00

1.90

1.80

1.70

1.35

1.30

1.25

1.20

1.15

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-43 Freq. reduction start FB voltage Fig-47-44 Freq. reduction end FB voltage

Fig-47-45 Voltage gain

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● Basic Characteristics (This data is for reference only and is not guaranteed.)

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

140

130

120

110

100

90

30

25

20

15

10

5

80

70

60

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-46 ZT comparator voltage 1

Fig-47-47 ZT trigger timeout period

Fig-47-48 Soft start time

3.1

3.0

2.9

2.8

2.7

2.6

2.5

3.9

3.8

3.7

3.6

3.5

3.4

3.3

84

74

64

54

44

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-49 FB OLP Voltage 1a

Fig-47-50 FB OLP Voltage 2a

Fig-47-51 FB OLP timer

3.8

10.0

30.0

25.0

20.0

15.0

10.0

5.0

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

3.7

3.6

3.5

3.4

3.3

3.2

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-52 ZT OVP Voltage

Fig-47-53 QR_OUT pin PMOS ON resistor

Fig-47-54 QR_OUT pin NMOS ON resistor

2.54

2.53

2.52

2.51

2.50

2.49

2.48

56

51

46

41

36

31

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-55 P_VS pin pull-up current

Fig-47-56 Gm amplifier normal voltage Fig-47-57 Gm amplifier trans-conductance

25

23

21

19

17

15

271

54

261

49

44

39

34

29

24

251

241

231

221

211

201

191

181

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-58 Max. Gm amplifier source current Fig-47-59 Max. Gm amplifier sink current Fig-47-60 P_VSEO stop voltage1

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● Basic Characteristics (This data is for reference only and is not guaranteed.)

168

158

148

138

128

118

108

98

750

650

550

450

350

250

70

68

66

64

62

60

88

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-61 P_VSEO stop voltage 2

Fig-47-62 PFC Oscillation frequency

Fig-47-63 PFC Min. Pulse width

98

97

96

95

94

93

92

91

90

1.3

1.2

1.1

1.0

0.9

0.68

0.63

0.58

0.53

0.48

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-64 PFC Maximum DUTY Fig-47-65 P_CS over current limit voltage1 Fig-47-66 P_CS over current limit voltage 2

0.40

0.35

0.30

0.25

0.20

2.45

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.83

2.78

2.73

2.68

2.63

2.58

2.53

2.48

2.43

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-67 P_VS short protection voltage

Fig-47-68 P_VS gain rise voltage

Fig-47-69 P_VS gain fall voltage

2.93

2.88

2.83

2.78

2.73

2.68

2.63

2.58

2.53

46

41

36

31

26

21

16

‐40

‐20

0

20

40

Ta [℃]

60

80

100

‐40

‐20

0

20

40

Ta [℃]

60

80

100

Fig-47-70 P_VS over voltage protection voltage Fig-47-71 P_VS over voltage protection timer

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● Thermal loss

The thermal design should set operation for the following conditions.

(Since the temperature shown below is the guaranteed temperature, be sure to take a margin into account.)

1. The ambient temperature Ta must be 85℃ or less.

2. The IC’s loss must be within the allowable dissipation Pd.

The thermal abatement characteristics are as follows. (Figure 47)

1000

900

800

700

600

500

400

300

200

100

0

25

50

75

100

125

150

Ta[℃]

Figure 48. SOP24 Temperature reduction peculiarity

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● Use-related cautions

(1) Absolute maximum ratings

Damage may occur if the absolute maximum ratings such as for applied voltage or operating temperature range are exceeded,

and since the type of damage (short, open circuit, etc.) cannot be determined, in cases where a particular mode that may

exceed the absolute maximum ratings is considered, use of a physical safety measure such as a fuse should be investigated.

(2) Power supply and ground lines

In the board pattern design, power supply and ground lines should be routed so as to achieve low impedance. If there are

multiple power supply and ground lines, be careful with regard to interference caused by common impedance in the routing

pattern. With regard to ground lines in particular, be careful regarding the separation of large current routes and small signal

routes, including the external circuits. Also, with regard to all of the LSI’s power supply pins, in addition to inserting capacitors

between the power supply and ground pins, when using capacitors there can be problems such as capacitance losses at low

temperature, so check thoroughly as to whether there are any problems with the characteristics of the capacitor to be used

before determining constants.

(3) Ground potential

The ground pin’s potential should be set to the minimum potential in relation to the operation mode.

(4) Pin shorting and attachment errors

When attaching ICs to the set board, be careful to avoid errors in the IC’s orientation or position. If such attachment errors

occur, the IC may become damaged. Also, damage may occur if foreign matter gets between pins, between a pin and a power

supply line, or between ground lines.

(5) Operation in strong magnetic fields

Note with caution that these products may become damaged when used in a strong magnetic field.

(6) Input pins

In IC structures, parasitic elements are inevitably formed according to the relation to potential. When parasitic elements are

active, they can interfere with circuit operations, can cause operation faults, and can even result in damage. Accordingly, be

careful to avoid use methods that enable parasitic elements to become active, such as when a voltage that is lower than the

ground voltage is applied to an input pin. Also, do not apply voltage to an input pin when there is no power supply voltage being

applied to the IC. In fact, even if a power supply voltage is being applied, the voltage applied to each input pin should be either

below the power supply voltage or within the guaranteed values in the electrical characteristics.

(7) External capacitors

When a ceramic capacitor is used as an external capacitor, consider possible reduction to below the nominal capacitance due

to current bias and capacitance fluctuation due to temperature and the like before determining constants.

(8) Thermal design

The thermal design should fully consider allowable dissipation (Pd) under actual use conditions.

Also, use these products within ranges that do not put output Tr beyond the rated voltage and ASO.

(9) Rush current

In a CMOS IC, momentary rush current may flow if the internal logic is undefined when the power supply is turned ON, so

caution is needed with regard to the power supply coupling capacitance, the width of power supply and GND pattern wires, and

how they are laid out.

(10) Handling of test pins and unused pins

Test pins and unused pins should be handled so as not to cause problems in actual use conditions, according to the

descriptions in the function manual, application notes, etc. Contact us regarding pins that are not described.

(11) Document contents

Documents such as application notes are design documents used when designing applications, and as such their contents are

not guaranteed. Before finalizing an application, perform a thorough study and evaluation, including for external parts.

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●Ordering Information

B

M

1

0

5

0

A

F

-

G E 2

Product name

Package

Packaging and

F

: SOP24

forming specification

E2: Embossed tape and reel

●Physical Dimension Tape and Reel Information

Tape

Embossed carrier tape

2000pcs

Quantity

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

Direction of feed

1pin

Reel

Order quantity needs to be multiple of the minimum quantity.

∗

●Marking Diagram

1PIN

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Revision History

Date

Revision

Changes

15.Mar.2013

7.Feb.2014

11.Apr.2015

001

002

003

New Release

Correction of errors

P13, P16, P17, P23, P25, P31, P32, P37, P38

The note external application of VREF when the latch mode is used.

P12 Figure4->Figure6 (Reference of start-up time)

P25 Figure25->Figure24

11.Apr.2015

003

P25 Figure26->Figure25

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual

ambient temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.001

Daattaasshheeeett

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.001

Daattaasshheeeett

General Precaution

1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.

ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny

ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s

representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.

Notice – WE

Rev.001


型号：	BM1050AF
厂家：	ROHM
描述：	BM1050AF是组合了应对高次谐波的功率因数校正（Power Factor Correction）转换器（以下简称PFC部）与DC/DC转换器（以下简称DC/DC部）的复合LSI。DC/DC部采用准谐振方式动作，有助于实现低EMI。BM1050AF内置650V耐压启动电路。PFC部、DC/DC部均外接开关MOSFET及电流检测电阻，可实现自由度高的电源设计。PFC部采用峰值电流控制。利用带AC电压过低补偿电路的乘法器、应对负载变动的电路、最大功率补偿电路等各种保护电路，提供合适的应用方案。此外，内置跳频功能，有助于实现低EMI。DC/DC部的准谐振方式为软开关动作，有助于实现低EMI。内置脉冲串模式，可降低轻负载时的功耗。内置了软启动功能、脉冲串功能、逐周期过电流限制、过电压保护、过负荷保护等各种保护功能。与微控制器间设有通信控制用端子、外部停止端子，可提供适用于各种应用的系统方案。通信开关控制器微控制器软启动脉冲功率因数校正转换器
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中文：	中文翻译
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BM1050AF [ROHM]

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