BD9F500QUZ_技术文档

Nano Pulse Control^TM

Datasheet

4.5 V to 36 V Input, 5 A Integrated MOSFET

Single Synchronous Buck DC/DC Converter

BD9F500QUZ

General Description

Key Specifications

 Input Voltage Range:

 Output Voltage Range:

 Output Current:

BD9F500QUZ is a synchronous buck DC/DC converter

with built-in low on-resistance power MOSFETs. It is

capable of providing current up to 5 A. It features fast

transient response due to Constant On-Time control

system. The Light Load Mode control improves efficiency in

light-load conditions. It is ideal for reducing standby power

consumption of equipment. Power Good function makes it

possible for system to control sequence. It achieves the

high power density and offer a small footprint on the PCB

by employing small package.

4.5 V to 36 V

0.6 V to 14 V

5 A (Max)

 Switching Frequency: 600 kHz, 1 MHz, 2.2 MHz (Typ)

 High-Side FET ON Resistance:

 Low-Side FET ON Resistance:

 Shutdown Current:

40 mΩ (Typ)

22 mΩ (Typ)

2 μA (Typ)

 Operating Quiescent Current:

20 μA (Typ)

Package

VMMP16LZ3030

W (Typ) x D (Typ) x H (Max)

3.0 mm x 3.0 mm x 0.40 mm

Features

 Single Synchronous Buck DC/DC Converter

 Constant On-Time Control

 Light Load Mode Control

 Adjustable Soft Start

 Power Good Output

 Nano Pulse Control™

 Output Capacitor Discharge Function

 Over Voltage Protection (OVP)

 Over Current Protection (OCP)

 Short Circuit Protection (SCP)

 Thermal Shutdown Protection (TSD)

 Under Voltage Lockout Protection (UVLO)

 VMMP16LZ3030 Package

Backside Heat Dissipation, 0.5 mm Pitch

VMMP16LZ3030

Applications

 Step-down Power Supply for SoC, FPGA,

Microprocessor

 Printer (MFP / LBP / IJP / POS)

 OA Equipment

 Laptop PC

 USB Type-C Applications

Typical Application Circuit

BD9F500QUZ

V_EN

EN

PGD

V_IN

VIN

BOOT

SW

0.1 μF

C_IN

V_OUT

PGND

L

V_SEL1

V_SEL2

SEL1

SEL2

VREG

R₁

R₂

C_FB

C_OUT

FB

C_REG

AGND

SS

Nano Pulse Control™ is a trademark or a registered trademark of ROHM Co., Ltd.

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Pin Configuration

(TOP VIEW)

16

15

14

13

12

11

10

9

FB

1

2

PGND

VREG

SEL2

SEL1

17

18

3

4

5

6

7

8

Pin Descriptions

Pin No. Pin Name

Function

1-4

PGND

SW

Ground pins for the output stage of the switching regulator.

Switch pin. This pin is connected to the source of the High-Side FET and the drain of the

Low-Side FET. Connect a bootstrap capacitor of 0.1 µF between this pin and the BOOT pin.

In addition, connect an inductor considering the direct current superimposition characteristic.

5, 17

Pin for bootstrap. Connect a bootstrap capacitor of 0.1 µF between this pin and the SW pin.

The voltage of this pin is the gate drive voltage of the High-Side FET.

6

7

BOOT

PGD

Power Good pin. This pin is an open drain output that requires a pull-up resistor. See

Function Explanations (4) Power Good for setting the resistance. If not used, this pin can be

left floating or connected to the ground.

Pin for setting the soft start time of output voltage. The soft start time is 2 ms (Typ) when the

SS pin is open. A ceramic capacitor connected to the SS pin makes the soft start time more

than 2 ms. See Selection of Components Externally Connected 4. Soft Start Capacitor for

how to calculate the capacitance.

8

SS

Pin for setting switching control mode. See Function Explanations (7) Control Mode

Selectable Function for how to control.

9

SEL1

SEL2

Pin for setting switching control mode. See Function Explanations (7) Control Mode

Selectable Function for how to control.

10

Internal power supply output pin. This node supplies power 5.2 V (Typ) to other blocks which

are mainly responsible for the control function of the switching regulator. Connecting 2.2 µF

(Typ) ceramic capacitor is recommended.

11

VREG

Output voltage feedback pin. See Selection of Components Externally Connected 3. Output

Voltage Setting, FB Capacitor for the output voltage setting.

12

13

14

FB

AGND

EN

Ground pin for the control circuit.

Enable pin. The device starts up with setting V_ENto 1.2 V (Typ) or more. The device enters

the shutdown mode with setting V_ENto 1.1 V (Typ) or less. This pin must be terminated.

Power supply pin. Connecting 0.1 µF (Typ) and 10 µF (Typ) ceramic capacitors is

recommended. The detail of a selection is described in Selection of Components Externally

Connected 1. Input Capacitor. Connecting to the PCB VIN pattern by using thermal vias

provides excellent heat dissipation characteristics. See PCB Layout Design for the detailed

PCB layout design.

15, 16,

18

VIN

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Block Diagram

VREG

11

REG

HOCP

15

16

18

＋

－

VIN

EN

VIN

UVLO

TSD

6

BOOT

14

8

EN

SS

VREF

SS

Error Amplifier

Main Comparator

＋

－

＋

－

Control

Logic

On-Time

5

SW

17

VREG

SCP

OVP

FB 12

LOCP

＋

－

PGOOD

1

2

3

4

PGND

ZX/ROCP

＋

－

FREQ

9

SEL1

SEL2

OCP

SELECTOR

10

MODE

7

13

PGD

AGND

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Description of Blocks

1. VREF

This block generates the internal reference voltage.

2. REG

This block generates the internal power supply.

3. Soft Start

The Soft Start circuit slows down the rise of output voltage during start-up and controls the current, which allows the

prevention of output voltage overshoot and inrush current. The internal soft start time is 2 ms (Typ) when the SS pin is

open. A capacitor connected to the SS pin makes the rising time more than 2 ms.

4. Error Amplifier

The Error Amplifier adjusts the Main Comparator input voltage to make the internal reference voltage equal to FB

voltage.

5. Main Comparator

The Main Comparator compares the Error Amplifier output voltage and FB voltage (V_FB). When V_FBbecomes lower than

the Error Amplifier output voltage, the output turns high and reports to the On-Time block that the output voltage has

dropped below the control voltage.

6. On-Time

This block generates On-Time. The designed On-Time is generated after the Main Comparator output turns high.

7. PGOOD

The PGOOD block is for power good function. When the output voltage reaches within ±7 % (Typ) of the setting voltage,

the built-in open drain Nch MOSFET connected to the PGD pin is turned off and the PGD pin becomes Hi-Z (High

impedance). When the output voltage reaches outside ±10 % (Typ) of the setting voltage, the open drain Nch MOSFET

is turned on and PGD pin is pulled down with 500 Ω (Typ).

8. UVLO

The UVLO block is for under voltage lockout protection. The device is shutdown when input voltage (V_IN) falls to 4.0 V

(Typ) or less. The threshold voltage has the 200 mV (Typ) hysteresis.

9. TSD

The TSD block is for thermal protection. The device is shutdown when the junction temperature Tj reaches to 175 °C

(Typ) or more. The device is automatically restored to normal operation with a hysteresis of 25 °C (Typ) when the Tj

goes down.

10. OVP

The OVP block is for output over voltage protection. When the FB voltage (V_FB) exceeds 120 % (Typ) or more of FB

threshold voltage V_FBTH, the SW pin is pulled down with 400 Ω (Typ). After V_FBfalls 115 % (Typ) or less of V_FBTH, the

device is returned to normal operation condition.

11. HOCP

This block is for over current protection of the High-Side FET. When the current that flows through the High-Side FET

reaches the value of over current limit, it turns off the High-Side FET and turns on the Low-Side FET.

12. LOCP

This block is for over current protection of the Low-Side FET. While the current that flows through the Low-Side FET

over the value of over current limit, the condition that being turned on the Low-Side FET is continued.

13. SCP

This block is for short circuit protection. After soft start is completed and in condition where V_FBis 90 % (Typ) of 0.6 V or

less, this block counts the number of times of which current flowing in the Low-Side FET reaches over current limit.

When 128 times is counted, the device is shutdown for 16 times of soft start time (Typ) and re-operates.

14. ZX/ROCP

The ZX/ROCP is a comparator that monitors the inductor current. When inductor current falls below 0 A (Typ) while the

Low-Side FET is on, it turns off the Low-Side FET (Light Load Mode). When the current that flows through the Low-Side

FET reaches the value of over current limit, it turns off the Low-Side FET (Fixed PWM Mode).

15. Control Logic

The Control Logic controls the switching operation and protection function operation.

16. SELECTOR

This block controls switching frequency, maximum output current, and operating mode.

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Absolute Maximum Ratings (Ta = 25 °C)

Parameter

Symbol

Rating

Unit

Input Voltage

V_IN

V_SW

-0.3 to +39

-0.3 to V_IN+ 0.3

-2 to V_IN+ 0.3

-1 to V_IN+ 0.3

-0.3 to +45

-0.3 to +7

V

SW Voltage

SW Voltage (3 ns pulse width)

SW Voltage (30 ns pulse width)

Voltage from GND to BOOT

Voltage from SW to BOOT

FB Voltage

V_SWAC1

V_SWAC2

V_BOOT

ΔV_BOOT-SW

V_FB

V

-0.3 to +7

V

VREG Voltage

V_VREG

V_SEL1

V_SEL2

V_PGD

-0.3 to +7

V

SEL1 Voltage

-0.3 to V_VREG+ 0.3

-0.3 to +45

-0.3 to +39

-0.3 to +7

V

SEL2 Voltage

V

PGD Voltage

V

EN Voltage

V_EN

V

SS Voltage

V_SS

V

Output Current

I_OUT

6

A

Maximum Junction Temperature

Tjmax

150

°C

Storage Temperature Range

Tstg

-55 to +150

°C

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 3)}

2s2p^{(Note 4)}

VMMP16LZ3030

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

125.1

12

50.7

8

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air).

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

Footprints and Traces

70 μm

Thermal Via^{(Note 5)}

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

Copper Pattern

Thickness

Copper Pattern

Thickness

Footprints and Traces

70 μm

74.2 mm x 74.2 mm

35 μm

74.2 mm x 74.2 mm

70 μm

(Note 5) This thermal via connects with the copper pattern of all layers.

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Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltage

Operating Temperature^{(Note 1)}

V_IN

4.5

-40

0

-

36.0

+85

5

V

°C

A

Topr

Output Current^{(Note 1)(Note 2)}

Output Voltage Setting^{(Note 3)}

I_OUT

0

3

A

V_OUT

0.6

14.0

V

(Note 1) Tj must be 150 °C or less under the actual operating environment. Life time is derated at junction temperature greater than 125 °C.

(Note 2) The maximum value of the output current is determined by the control mode selection.

(Note 3) The switching frequency is reduced as needed to always ensure a proper regulation at low duty and high duty cycles. Use under the condition of V_OUT

V_IN× 0.8 [V].

≤

Electrical Characteristics (Unless otherwise specified Ta = 25 °C, V_IN= 12 V, V_EN= 3 V)

Parameter

Input Supply

Symbol

Min

Typ

Max

Unit

Conditions

Shutdown Current

I_SDN

I_Q

V_UVLO1

V_UVLO2

-

2

10

40

µA

V_EN= 0 V

I_OUT= 0 A,

No switching

Operating Quiescent Current

20

UVLO Detection Threshold Voltage

UVLO Release Threshold Voltage

UVLO Hysteresis Voltage

Enable

3.7

3.9

100

4.0

4.2

4.3

4.5

400

V

V_INfalling

V_INrising

V_UVLOHYS

200

mV

EN Threshold Voltage High

EN Threshold Voltage Low

EN Hysteresis Voltage

EN Input Current

V_ENH

V_ENL

1.1

1.0

50

-

1.2

1.1

100

0

1.3

1.2

200

2

V

V_ENrising

V_ENfalling

V_ENHYS

I_EN

mV

µA

V_EN= 3 V

V_EN= 0 V

VREG

VREG Shutdown Voltage

VREG Output Voltage

V_{VREG_SD}

V_VREG

-

0

0.1

5.4

V

5.0

5.2

Reference Voltage, Error Amplifier, Soft Start

FB Threshold Voltage

FB Input Current

Soft Start Time

V_FBTH

I_FB

0.594

-

0.600

-

0.606

100

2.6

V

PWM mode

nA

ms

µA

V_FB= 0.6 V

t_SS

1.4

1.6

2.0

The SS pin is open.

Soft Start Charge Current

Control

I_SS

2.4

V_VREG

-0.3

-

V_VREG

V

SEL1, SEL2 High Level Voltage

V_SELH

SEL1, SEL2 Low Level Voltage

SEL1, SEL2 Input Current

V_SELL

I_SEL

t_ON1

0

-

0.3

3

V

µA

V_OUT= 3.3 V, PWM mode,

600 kHz setting

V_OUT= 3.3 V, PWM mode,

1 MHz setting

V_OUT= 3.3 V, PWM mode,

2.2 MHz setting

-

458

275

-

ns

On-Time1

On-Time2

On-Time3

t_ON2

t_ON3

-

125

48

-

ns

Minimum On-Time^{(Note 4)}

t_MINON

SW (MOSFET)

V_BOOT- V_SW= 5 V,

I_OUTMAX= 5 A setting

V_BOOT- V_SW= 5 V,

I_OUTMAX= 3 A setting

High-Side FET ON Resistance1

R_ONH1

R_ONH2

-

40

65

80

mΩ

High-Side FET ON Resistance2

Low-Side FET ON Resistance1

130

R_ONL1

R_ONL2

-

22

38

44

76

mΩ

I_OUTMAX= 5 A setting

I_OUTMAX= 3 A setting

Low-Side FET ON Resistance2

(Note 4) No tested on outgoing inspection.

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Electrical Characteristics – continued (Unless otherwise specified Ta = 25 °C, V_IN= 12 V, V_EN= 3 V)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Power Good

V_FBrising,

V_PGDTHGR= V_FB/ V_FBTHx 100

V_FBfalling,

V_PGDTHGF= V_FB/ V_FBTHx 100

V_FBrising,

V_PGDTHFR= V_FB/ V_FBTHx 100

V_FBfalling,

Power Good Rising

Threshold Voltage

Power Good Falling

Threshold Voltage

Power Fault Rising

Threshold Voltage

Power Fault Falling

Threshold Voltage

V_PGDTHGR

V_PGDTHGF

V_PGDTHFR

V_PGDTHFF

90

104

107

87

93

107

110

90

96

110

113

93

%

V_PGDTHFF= V_FB/ V_FBTHx 100

PGD Output Leakage Current

PGD MOSFET ON Resistance

Protection

I_LKPGD

R_PGD

-

0

1

µA

V_PGD= 5 V

500

1000

Ω

Low-Side FET Over Current

I_LOCP1

I_LOCP2

5.3

3.2

6.7

4.0

8.1

4.8

A

I_OUTMAX= 5 A setting

I_OUTMAX= 3 A setting

Detection Current 1^{(Note 1)}

Low-Side FET Over Current

Detection Current 2^{(Note 1)}

(Note 1) No tested on outgoing inspection.

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Typical Performance Curves

10

40

35

30

25

20

15

10

5

V_IN= 12 V

8

6

4

2

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 1. Shutdown Current vs Temperature

Figure 2. Operating Quiescent Current vs Temperature

4.5

1.3

V_IN= 12 V

4.4

4.3

4.2

4.1

4

1.25

V_ENH( V_ENrising)

UVLO Release ( V_INrising)

UVLO Detection ( V_INfalling)

1.2

1.15

V_ENL( V_ENfalling)

1.1

3.9

3.8

3.7

1.05

1

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 3. UVLO Threshold Voltage vs Temperature

Figure 4. EN Threshold Voltage vs Temperature

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Typical Performance Curves – continued

0.1

0.08

0.06

0.04

0.02

0

2

V_IN= 12 V

V_IN= 12 V, V_EN= 3 V

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 5. EN Input Current vs Temperature

Figure 6. VREG Shutdown Voltage vs Temperature

5.4

0.61

V_IN= 12 V

0.608

5.35

5.3

0.606

0.604

0.602

0.6

5.25

5.2

0.598

0.596

0.594

0.592

0.59

5.15

5.1

5.05

5

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 7. VREG Output Voltage vs Temperature

Figure 8. FB Threshold Voltage vs Temperature

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Typical Performance Curves – continued

100

2.6

2.5

2.4

2.3

2.2

2.1

2

V_IN= 12 V

80

60

40

20

0

1.9

1.8

1.7

1.6

1.5

1.4

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 9. FB Input Current vs Temperature

Figure 10. Soft Start Time vs Temperature

5.2

5.1

5

2.4

V_IN= 12 V, V_VREG= 5.2 V (Typ)

V_IN= 12 V

2.3

2.2

2.1

2

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4

1.9

1.8

1.7

1.6

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 11. Soft Start Charge Current vs Temperature

Figure 12. SEL1, SEL2 High Threshold Voltage vs

Temperature

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Typical Performance Curves – continued

1

3

2.5

2

V_IN= 12 V

0.9

V_SEL1, V_SEL2= 0 V

V_SEL1, V_SEL2= 5.25 V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.5

1

0.5

0

-0.5

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 13. SEL1, SEL2 Low Threshold Voltage vs

Temperature

Figure 14. SEL1, SEL2 Input Current vs Temperature

80

V_IN= 12 V

70

V_IN= 12 V

120

100

80

60

40

20

0

60

50

40

30

20

10

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 15. High-Side FET ON Resistance1 vs Temperature

Figure 16. High-Side FET ON Resistance2 vs Temperature

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Typical Performance Curves – continued

50

80

70

60

50

40

30

20

10

0

V_IN= 12 V

45

40

35

30

25

20

15

10

5

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 17. Low-Side FET ON Resistance1 vs Temperature

Figure 18. Low-Side FET ON Resistance2 vs Temperature

0.72

0.69

0.66

0.63

0.6

1.2

1.15

1.1

1.05

1

0.57

0.54

0.51

0.48

0.95

0.9

0.85

0.8

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 19. Switching Frequency vs Temperature

(V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2 A,

Figure 20. Switching Frequency vs Temperature

(V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2 A,

600 kHz_I_OUTMAX= 5 A_PWM setting)

1 MHz_I_OUTMAX= 5 A_PWM setting)

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Typical Performance Curves – continued

2.6

2.5

2.4

2.3

2.2

2.1

2

115

110

105

100

95

V_IN= 12 V

Power Fault (V_FBrising)

Power Good (V_FBfalling)

Power Good (V_FBrising)

Power Fault (V_FBfalling)

90

1.9

1.8

85

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 21. Switching Frequency vs Temperature

(V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2 A, 2.2 MHz setting)

Figure 22. Power Good / Fault Threshold Voltage vs

Temperature

1

1000

V_IN= 12 V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V_IN= 12 V

900

800

700

600

500

400

300

200

100

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 23. PGD Output Leakage Current vs Temperature

Figure 24. PGD MOSFET ON Resistance vs Temperature

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Typical Performance Curves – continued

Time: 1 ms/div

Time: 50 ms/div

V_IN: 5 V/div

V_EN: 3 V/div

V_IN: 5 V/div

V_EN: 3 V/div

V_OUT: 2 V/div

V_PGD: 5 V/div

V_OUT: 2 V/div

V_PGD: 5 V/div

Figure 25. Start-up at No Load: V_EN= 0 V to 5 V

(V_IN= 12 V, V_OUT= 3.3 V, C_SS= OPEN,

1 MHz_I_OUTMAX= 5 A_LLM setting)

Figure 26. Shutdown at No Load: V_EN= 5 V to 0 V

(V_IN= 12 V, V_OUT= 3.3 V, C_SS= OPEN,

1 MHz_I_OUTMAX= 5 A_LLM setting)

Time: 1 ms/div

V_IN: 5 V/div

V_EN: 3 V/div

V_IN: 5 V/div

V_EN: 3 V/div

V_OUT: 2 V/div

V_PGD: 5 V/div

V_OUT: 2 V/div

V_PGD: 5 V/div

Figure 27. Start-up at R_LOAD= 0.66 Ω: V_EN= 0 V to 5 V

(V_IN= 12 V, V_OUT= 3.3 V, C_SS= OPEN,

1 MHz_I_OUTMAX= 5 A_LLM setting)

Figure 28. Shutdown at R_LOAD= 0.66 Ω: V_EN= 5 V to 0 V

(V_IN= 12 V, V_OUT= 3.3 V, C_SS= OPEN,

1 MHz_I_OUTMAX= 5 A_LLM setting)

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Typical Performance Curves – continued

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

45

40

V

_OUT= 5 V

V

_OUT= 5 V

50

45

40

_OUT= 3.3 V

_OUT= 1.0 V

_OUT= 3.3 V

_OUT= 1.0 V

0

1

2

3

4

5

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 29. Efficiency vs Output Current

Figure 30. Efficiency vs Output Current

(V_IN= 12 V, 600 kHz_I_OUTMAX= 5 A_LLM setting)

(V_IN= 12 V, 600 kHz_I_OUTMAX= 5 A_PWM setting)

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

V

_OUT= 5 V

V

_OUT= 5 V

50

45

40

50

45

40

_OUT= 3.3 V

_OUT= 1.0 V

_OUT= 3.3 V

_OUT= 1.0 V

0

1

2

3

4

5

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 31. Efficiency vs Output Current

(V_IN= 24 V, 600 kHz_I_OUTMAX= 5 A_LLM setting)

Figure 32. Efficiency vs Output Current

(V_IN= 24 V, 600 kHz_I_OUTMAX= 5 A_PWM setting)

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Typical Performance Curves – continued

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

55

50

45

40

55

V

_OUT= 5 V

= 5 V

V_OUT

50

_OUT= 3.3 V

_OUT= 1.0 V

V_OUT= 3.3 V

45

40

V

_OUT= 1.0 V

0

1

2

3

4

5

0.001

0.01

0.1

1 10

Output Current : I_OUT[A]

Figure 33. Efficiency vs Output Current

(V_IN= 12 V, 1 MHz_I_OUTMAX= 5 A_LLM setting)

Figure 34. Efficiency vs Output Current

(V_IN= 12 V, 1 MHz_I_OUTMAX= 5 A_PWM setting)

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

45

40

= 5 V

V_OUT

V

_OUT= 5 V

45

40

V_OUT= 3.3 V

_OUT= 3.3 V

0

1

2

3

4

5

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 35. Efficiency vs Output Current

(V_IN= 24 V, 1 MHz_I_OUTMAX= 5 A_LLM setting)

Figure 36. Efficiency vs Output Current

(V_IN= 24 V, 1 MHz_I_OUTMAX= 5 A_PWM setting)

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Typical Performance Curves – continued

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

45

40

V

_OUT= 5 V

V

_OUT= 5 V

50

45

40

_OUT= 3.3 V

_OUT= 1.0 V

_OUT= 3.3 V

_OUT= 1.0 V

0

1

2

3

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 37. Efficiency vs Output Current

Figure 38. Efficiency vs Output Current

(V_IN= 12 V, 600 kHz_I_OUTMAX= 3 A_LLM setting)

(V_IN= 12 V, 600 kHz_I_OUTMAX= 3 A_PWM setting)

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

V

_OUT= 5 V

V

_OUT= 5 V

50

45

40

50

45

40

_OUT= 3.3 V

_OUT= 1.0 V

_OUT= 3.3 V

_OUT= 1.0 V

0

1

2

3

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 39. Efficiency vs Output Current

(V_IN= 24 V, 600 kHz_I_OUTMAX= 3 A_LLM setting)

Figure 40. Efficiency vs Output Current

(V_IN= 24 V, 600 kHz_I_OUTMAX= 3 A_PWM setting)

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Typical Performance Curves – continued

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

45

40

V

_OUT= 5 V

V

_OUT= 5 V

50

45

40

_OUT= 3.3 V

_OUT= 1.0 V

_OUT= 3.3 V

_OUT= 1.0 V

0

1

2

3

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 41. Efficiency vs Output Current

(V_IN= 12 V, 1 MHz_I_OUTMAX= 3 A_LLM setting)

Figure 42. Efficiency vs Output Current

(V_IN= 12 V, 1 MHz_I_OUTMAX= 3 A_PWM setting)

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

45

40

V

_OUT= 5 V

V

_OUT= 5 V

45

40

V

_OUT= 3.3 V

0

1

2

3

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 43. Efficiency vs Output Current

(V_IN= 24 V, 1 MHz_I_OUTMAX= 3 A_LLM setting)

Figure 44. Efficiency vs Output Current

(V_IN= 24 V, 1 MHz_I_OUTMAX= 3 A_PWM setting)

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Typical Performance Curves – continued

100

95

90

85

80

75

70

65

60

55

50

3.4

3.35

3.3

3.25

3.2

= 24 V

Fixed PWM Mode

Light Load Mode

V_IN

45

40

V_IN= 12 V

0

1

2

3

0

1

2

3

4

5

Output Current : I_OUT[A]

Figure 45. Efficiency vs Output Current

(V_OUT= 3.3 V, 2.2 MHz setting)

Figure 46. Load Regulation

(V_IN= 12 V, V_OUT= 3.3 V, 600 kHz_I_OUTMAX= 5 A setting)

3.4

3.35

3.3

3.4

3.35

3.3

3.25

3.2

3.25

3.2

Fixed PWM Mode

Light Load Mode

0

1

2

3

0

1

2

3

4

5

Output Current : I_OUT[A]

Figure 47. Load Regulation

(V_IN= 12 V, V_OUT= 3.3 V, 1 MHz_I_OUTMAX= 5 A setting)

Figure 48. Load Regulation

(V_IN= 12 V, V_OUT= 3.3 V, 2.2 MHz setting)

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Typical Performance Curves – continued

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Fixed PWM Mode

Light Load Mode

Fixed PWM Mode

Light Load Mode

0.1

0

1

2

3

4

5

0

1

2

3

4

5

Output Current : I_OUT[A]

Figure 49. Switching Frequency vs Output Current

(V_IN= 12 V, V_OUT= 3.3 V, 600 kHz_I_OUTMAX= 5 A setting)

Figure 50. Switching Frequency vs Output Current

(V_IN= 12 V, V_OUT= 3.3 V, 1 MHz_I_OUTMAX= 5 A setting)

3.4

3.35

3.3

2.6

2.5

2.4

2.3

2.2

2.1

2

3.25

3.2

1.9

1.8

0

1

2

3

4

8

12

16

20

24

28

32

36

Output Current : I_OUT[A]

Input Voltage : V_IN[V]

Figure 51. Switching Frequency vs Output Current

(V_IN= 12 V, V_OUT= 3.3 V, 2.2 MHz setting)

Figure 52. Line Regulation

(V_OUT= 3.3 V, I_OUT= 2 A,

600 kHz_I_OUTMAX= 5 A_PWM setting)

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Typical Performance Curves – continued

3.4

3.35

3.3

3.4

3.35

3.3

3.25

3.2

3.25

3.2

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

Input Voltage : V_IN[V]

Figure 53. Line Regulation

(V_OUT= 3.3 V, I_OUT= 2 A, 1 MHz_I_OUTMAX= 5 A_PWM setting)

Figure 54. Line regulation

(V_OUT= 3.3 V, I_OUT= 1 A, 2.2 MHz setting)

0.72

0.69

0.66

0.63

0.6

1.2

1.15

1.1

1.05

1

0.57

0.54

0.51

0.48

0.95

0.9

0.85

0.8

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

Input Voltage : V_IN[V]

Figure 55. Switching Frequency vs Input Voltage

(V_OUT= 3.3 V, I_OUT= 2 A,

Figure 56. Switching Frequency vs Input Voltage

(V_OUT= 3.3 V, I_OUT= 2 A, 1 MHz_I_OUTMAX= 5 A_PWM setting)

600 kHz_I_OUTMAX= 5 A_PWM setting)

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Typical Performance Curves – continued

2.6

2.5

2.4

2.3

2.2

2.1

2

6.5

6

V_IN

= 24 V

= 12 V

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

1.9

1.8

0.5

0

4

8

12

16

20

24

28

32

36

-60 -40 -20

0

20

40

60

80 100

Input Voltage : V_IN[V]

Temperature : Ta [°C]

Figure 57. Switching Frequency vs Input Voltage

(V_OUT= 3.3 V, I_OUT= 1 A, 2.2 MHz setting)

Figure 58. Output Current vs Temperature^{(Note 1)}

Operating Range: Tj < 150 °C (V_OUT= 3.3 V, 600 kHz setting)

6.5

4

V_IN

= 24 V

= 12 V

= 24 V

= 12 V

6

5.5

5

3.5

3

4.5

4

2.5

2

3.5

3

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

-60 -40 -20

0

20

40

60

80 100

-60 -40 -20

0

20

40

60

80 100

Temperature : Ta [°C]

Figure 59. Output Current vs Temperature^{(Note 1)}

Figure 60. Output Current vs Temperature^{(Note 1)}

Operating Range: Tj < 150 °C (V_OUT= 3.3 V, 1 MHz setting)

Operating Range: Tj < 150 °C (V_OUT= 3.3 V, 2.2 MHz setting)

(Note 1) Measured on FR-4 board 85 mm x 85 mm, Copper Thickness: Top and Bottom 70 μm, 2 Internal Layers 35 μm.

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Function Explanations

1. Basic Operation

(1) DC/DC Converter Operation

BD9F500QUZ is a synchronous rectifying step-down switching regulator that has original On-Time control method.

Device operates as the SEL1 pin and the SEL2 pin setting. When the operating mode is Light Load Mode, it utilizes

switching operation in Pulse Width Modulation (PWM) mode control at heavier load, and it operates in Light Load

mode (LLM) control at lighter load to improve efficiency. When the operating mode is Fixed PWM Mode, the device

operates in PWM mode control regardless of the load.

Light Load Mode Control

PWM Control

Fixed PWM Mode Control

Output Current [A]

Figure 61. Efficiency Image between Light Load Mode Control and PWM Mode Control

(2) Enable Control

The startup and shutdown can be controlled by the EN voltage (V_EN). When V_ENbecomes 1.2 V (Typ) or more, the

internal circuit is activated and the device starts up. When V_ENbecomes 1.1 V (Typ) or less, the device is shutdown. In

this shutdown mode, the High-Side FET and the Low-Side FET are turned off and the SW pin is connected to GND

through an internal resistor 400 Ω (Typ) to discharge the output. The start-up with V_ENmust be at the same time of the

input voltage V_IN(V_IN= V_EN) or after supplying V_IN.

V_IN

0 V

V_EN

V_ENH

V_ENL

0 V

V_OUT

0 V

Startup

Shutdown

Figure 62. Startup and Shutdown with Enable Control Timing Chart

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1. Basic Operation – continued

(3) Soft Start

When V_ENgoes high, soft start function operates and output voltage gradually rises. This soft start function can

prevent overshoot of the output voltage and excessive inrush current. The soft start time t_SSis 2 ms (Typ) when the SS

pin is left floating. A capacitor connected to the SS pin makes t_SSmore than 2 ms. See Selection of Components

Externally Connected 4. Soft Start Capacitor for how to set the soft start time.

V_IN

0 V

V_EN

0 V

V_OUT

0 V

V_FBTHx 90 %

0.6 V

(Typ)

V_FB

0 V

V_PGD

0 V

0.4 ms (Typ)

t_SS

Figure 63. Soft Start Timing Chart

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1. Basic Operation – continued

(4) Power Good

When the output voltage V_OUTreaches within ±7 % (Typ) of the voltage setting, the built-in open drain Nch MOSFET

connected to the PGD pin is turned off, and the PGD pin goes Hi-Z (High impedance). When V_OUTreaches outside

±10 % (Typ) of the voltage setting, the open drain Nch MOSFET is turned on and PGD pin is pulled down with 500 Ω

(Typ). It is recommended to connect a pull-up resistor of 20 kΩ to 100 kΩ.

Table 1. PGD Output

State

Before Supply Input Voltage

Shutdown

Condition

V_IN< 2.5 V (Typ)

PGD Output

Hi-Z

V_EN≤ 1.1 V (Typ)

Low (Pull-down)

Hi-Z

93 % (Typ) ≤ V_FB/ V_FBTH≤ 107 % (Typ)

V_FB/ V_FBTH≤ 90 % (Typ) or 110 % (Typ) ≤ V_FB/ V_FBTH

2.5 V (Typ) < V_IN≤ 4.0 V (Typ)

Tj ≥ 175 °C (Typ)

Enable

V_EN≥ 1.2 V (Typ)

Low (Pull-down)

UVLO

TSD

V_IN

0 V

V_EN

0 V

+10 % (Typ)

-10 % (Typ)

+7 % (Typ)

-7 % (Typ)

V_OUT

0 V

V_FBTHx 110 % (Typ)

V_FBTHx 90 % (Typ)

V_FBTHx 107 % (Typ)

V_FBTHx 93 % (Typ)

V_FB

0 V

t_SS

V_PGD

0 V

Figure 64. Power Good Timing Chart

(Connecting a pull-up resistor to the PGD pin)

(5) Nano Pulse Control^TM

Nano Pulse Control^TMis an original technology developed by ROHM Co., Ltd. It enables to control voltage stably,

which is difficult in the conventional technology, even in a narrow SW ON time such as less than 50 ns at typical

condition.

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1. Basic Operation – continued

(6) Output Capacitor Discharge Function

When even one of the following conditions is satisfied, output is discharged with 400 Ω (Typ) resistor through the SW

pin.

• Shutdown: V_EN≤ 1.1 V (Typ)

• UVLO: V_IN≤ 4.0 V (Typ)

• TSD: Tj ≥ 175 °C (Typ)

• OVP: V_FB/ V_FBTH≥ 120 % (Typ)

When all of the above conditions are released, output discharge is stopped.

(7) Control Mode Selectable Function

BD9F500QUZ has the SEL1 pin and the SEL2 pin that can offer 9 different states of operation as a combination of

Switching Frequency, Maximum Output Current and Operation mode. It can operate at two different current limits to

support an output continuous current of 5 A, 3 A respectively. It can operate at three different frequencies of 600 kHz, 1

MHz and 2.2 MHz and also can choose between Light Load Mode and Fixed PWM mode for 600 kHz and 1 MHz

operation. Do not change the mode control of Switching Frequency and Maximum Output Current during operation.

Table 2. Control Mode Selection

Maximum

SEL1 pin

condition

SEL2 pin

condition

Switching

Frequency

Output Current

Operation Mode

(I_OUTMAX

)

GND

OPEN

GND

Light Load Mode (LLM)

Fixed PWM Mode

5 A

1 MHz (Typ)

VREG

OPEN

GND

Light Load Mode (LLM)

Fixed PWM Mode

3 A

5 A

OPEN

GND

Light Load Mode (LLM)

Fixed PWM Mode

OPEN

VREG

600 kHz (Typ)

2.2 MHz (Typ)

Light Load Mode (LLM)

Fixed PWM Mode

3 A

OPEN

VREG

Fixed PWM Mode

Table 3. OCP Value

Maximum Output

Low-Side Sink OCP

(Fixed PWM mode)

I_ROCP1= 4.2 A (Typ)

I_ROCP2= 2.5 A (Typ)

Low-Side OCP

High-Side OCP

Current (I_OUTMAX

)

5 A

3 A

I_LOCP1= 6.7 A (Typ)

I_LOCP2= 4.0 A (Typ)

I_HOCP1= 8.25 A (Typ)

I_HOCP2= 5.0 A (Typ)

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Function Explanations – continued

2. Protection

The protection circuits are intended for prevention of damage caused by unexpected accidents. Do not use the

continuous protection.

(1) Over Current Protection (OCP) / Short Circuit Protection (SCP)

Over Current Protection (OCP) restricts the flowing current through the Low-Side FET and the High-Side FET for every

switching period. If the inductor current exceeds the Low-Side OCP I_LOCP1= 6.7 A (Typ), I_LOCP2= 4.0 A (Typ) while the

Low-Side FET is on, the Low-Side FET remains on even with FB voltage V_FBfalls to V_FBTH= 0.6 V (Typ) or less. If the

inductor current becomes less than I_LOCP1, I_LOCP2, the High-Side FET is able to be turned on. When the inductor current

becomes the High-Side OCP I_HOCP1= 8.25 A (Typ), I_HOCP2= 5.0 A (Typ) or more while the High-Side FET is on, the

High-Side FET is turned off. Output voltage may decrease by changing frequency and duty due to the OCP operation.

Short Circuit Protection (SCP) function is a Hiccup mode. When Low-Side OCP 128 times is counted while V_FBis V_FBTH

x 90 % or less (V_PGD= Low), the device stops the switching operation for 16 times of Soft Start Time (Typ). After that,

the device restarts. SCP does not operate during the soft start even if the device is in the SCP conditions. Do not

exceed the maximum junction temperature (Tjmax = 150 °C) during OCP and SCP operation.

Table 4. The Operating Condition of OCP and SCP

V_EN

V_FB

Start-up

OCP

SCP

≤ V_FBTHx 90 % (Typ)

> V_FBTHx 93 % (Typ)

≤ V_FBTHx 90 % (Typ)

-

During Soft Start

Enable

Disable

Enable

Disable

≥ 1.2 V (Typ)

≤ 1.1 V (Typ)

Complete Soft Start

Shutdown

V_OUT

V_FBTHx 93 % (Typ)

V_FBTHx 90 % (Typ)

V_FB

V_PGD

V_SW

High-Side FET

Internal Gate Signal

Low-Side FET

Internal Gate Signal

I_HOCP

I_LOCP

Inductor Current

High-Side OCP

Internal Signal

Low-Side OCP

Internal Signal

OCP 128 counts

Less than

OCP 128 counts

SCP

Internal Signal

16 tims of SS time (Typ)

Figure 65. OCP and SCP Timing Chart

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BD9F500QUZ

2. Protection – continued

(2) Low-Side Sink (Reverse) Over Current Protection (ROCP)

When operating mode is Fixed PWM and inductor current exceeds the sink current limit threshold value I_ROCP1= 4.2 A

(Typ), I_ROCP2= 2.5 A (Typ) while Low-Side FET is ON, the Low-Side FET turns OFF.

(3) Under Voltage Lockout Protection (UVLO)

When input voltage V_INfalls to 4.0 V (Typ) or less, the device is shutdown. When V_INbecomes 4.2 V (Typ) or more, the

device starts up. The hysteresis is 200 mV (Typ).

V_IN

(=V_EN

)

Hysteresis

V_UVLOHYS= 200 mV (Typ)

V_OUT

UVLO Release

V_UVLO2= 4.2 V (Typ)

UVLO Detection

V_UVLO1= 4.0 V (Typ)

0 V

V_OUT

0 V

t_SS

Figure 66. UVLO Timing Chart

(4) Thermal Shutdown Protection (TSD)

Thermal shutdown circuit prevents heat damage to the IC. The device should always operate within the IC’s maximum

junction temperature rating (Tjmax = 150 °C). However, if it continues exceeding the rating and the junction

temperature Tj rises to 175 °C (Typ), the TSD circuit is activated and it turns the output MOSFETs off. When the Tj falls

below the TSD threshold, the circuits are automatically restored to normal operation. The TSD threshold has a

hysteresis of 25 °C (Typ). Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings.

Therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than

protecting the IC from heat damage.

(5) Over Voltage Protection (OVP)

When the FB voltage V_FBexceeds V_FBTHx 120 % (Typ) or more, output is discharged with 400 Ω (Typ) resister through

the SW pin to prevent the increase in the output voltage. After the V_FBfalls V_FBTHx 115 % (Typ) or less, the output

MOSFETs are returned to normal operation condition. Switching operation restarts after V_FBfalls below V_FBTH(Typ).

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Application Examples

1. V_IN= 12 V to 24 V, V_OUT= 3.3 V, f_SW= 1 MHz

Table 5. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

12 V to 24 V (Typ)

3.3 V (Typ)

V_IN

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Operation Mode

5 A

1 MHz (Typ)

Light Load Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 67. Application Circuit

Table 6. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

1.5 μH

1217AS-H-1R5N

8080

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

10 μF (50 V, X5R, ±20 %)

0.1 μF (50 V, X5R, ±10 %)

22 μF (25 V, X5R, ±20 %)

2.2 μF (25 V, X5R, ±20 %)

82 pF (50 V, C0G, ±5 %)

-

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

GRM0335C1H820JA01

Murata

-

R_1A

1.5 kΩ (1 %, 1/16 W)

120 kΩ (1 %, 1/16 W)

27 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

-

MCR01MZPF1500

1005

-

ROHM

R_1B

MCR01MZPF1203

ROHM

R₂

MCR01MZPF2702

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

MCR01MZPF1003

ROHM

-

Short

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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1. V_IN= 12 V to 24 V, V_OUT= 3.3 V, f_SW= 1 MHz – continued

100

90

80

70

60

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 5 V/div

50

V_IN= 12 V

V_IN= 24 V

40

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 68. Efficiency vs Output Current

Figure 69. Output Ripple Voltage (V_IN= 12 V, I_OUT= 5 A)

80

60

180

135

90

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 70. Frequency Characteristics (V_IN= 12 V, I_OUT= 3 A)

Figure 71. Load Transient Response

(V_IN= 12 V, I_OUT= 0.1 A to 3.0 A)

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BD9F500QUZ

Application Examples – continued

2. V_IN= 12 V to 24 V, V_OUT= 3.3 V, f_SW= 600 kHz

Table 7. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

12 V to 24 V (Typ)

3.3 V (Typ)

V_IN

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Operation Mode

5 A

600 kHz (Typ)

Light Load Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 72. Application Circuit

Table 8. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

3.3 μH

1217AS-H-3R3N

8080

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

10 μF (50 V, X5R, ±20 %)

0.1 μF (50 V, X5R, ±10 %)

22 μF (25 V, X5R, ±20 %)

2.2 μF (25 V, X5R, ±20 %)

82 pF (50 V, C0G, ±5 %)

-

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

GRM0335C1H820JA01

Murata

-

R_1A

1.5 kΩ (1 %, 1/16 W)

120 kΩ (1 %, 1/16 W)

27 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

-

MCR01MZPF1500

1005

-

ROHM

R_1B

MCR01MZPF1203

ROHM

R₂

MCR01MZPF2702

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

MCR01MZPF1003

ROHM

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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2. V_IN= 12 V to 24 V, V_OUT= 3.3 V, f_SW= 600 kHz – continued

100

90

80

70

60

50

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 5 V/div

V_IN

= 12 V

= 24 V

40

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 73. Efficiency vs Output Current

Figure 74. Output Ripple Voltage (V_IN= 12 V, I_OUT= 5 A)

80

60

180

135

90

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 75. Frequency Characteristics (V_IN= 12 V, I_OUT= 3 A)

Figure 76. Load Transient Response

(V_IN= 12 V, I_OUT= 0.1 A to 3.0 A)

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Application Examples – continued

3. V_IN= 5 V, V_OUT= 3.3 V, f_SW= 1 MHz

Table 9. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

5 V (Typ)

V_IN

V_OUT

I_OUTMAX

f_SW

Output Voltage

3.3 V (Typ)

5 A

Maximum Output Current

Switching Frequency

Operation Mode

1 MHz (Typ)

Light Load Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 77. Application Circuit

Table 10. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

1.0 μH

FDSD0518-H-1R0M

5249

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

10 μF (50 V, X5R, ±20 %)

0.1 μF (50 V, X5R, ±10 %)

22 μF (25 V, X5R, ±20 %)

2.2 μF (25 V, X5R, ±20 %)

33 pF (50 V, C0G, ±5 %)

-

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

GRM0335C1H330JA01

Murata

-

R_1A

120 kΩ (1 %, 1/16 W)

330 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

-

MCR01MZPF1203

1005

-

ROHM

R_1B

MCR01MZPF3303

ROHM

R₂

MCR01MZPF1003

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

MCR01MZPF1003

ROHM

-

Short

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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BD9F500QUZ

3. V_IN= 5 V, V_OUT= 3.3 V, f_SW= 1 MHz – continued

100

90

80

70

60

50

40

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 2 V/div

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 78. Efficiency vs Output Current

Figure 79. Output Ripple Voltage (I_OUT= 5 A)

80

60

180

135

90

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 80. Frequency Characteristics (I_OUT= 3 A)

Figure 81. Load Transient Response (I_OUT= 0.1 A to 3.0 A)

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TSZ22111 • 15 • 001

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Application Examples – continued

4. V_IN= 5 V, V_OUT= 3.3 V, f_SW= 600 kHz

Table 11. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

5 V (Typ)

V_IN

V_OUT

I_OUTMAX

f_SW

Output Voltage

3.3 V (Typ)

5 A

Maximum Output Current

Switching Frequency

Operation Mode

600 kHz (Typ)

Light Load Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 82. Application Circuit

Table 12. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

2.2 μH

FDSD0630-H-2R2M

7066

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

10 μF (50 V, X5R, ±20 %)

0.1 μF (50 V, X5R, ±10 %)

22 μF (25 V, X5R, ±20 %)

2.2 μF (25 V, X5R, ±20 %)

39 pF (50 V, C0G, ±5 %)

-

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

GRM0335C1H390JA01

Murata

-

R_1A

120 kΩ (1 %, 1/16 W)

330 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

-

MCR01MZPF1203

1005

-

ROHM

R_1B

MCR01MZPF3303

ROHM

R₂

MCR01MZPF1003

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

MCR01MZPF1003

ROHM

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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TSZ22111 • 15 • 001

BD9F500QUZ

4. V_IN= 5 V, V_OUT= 3.3 V, f_SW= 600 kHz – continued

100

90

80

70

60

50

40

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 2 V/div

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 83. Efficiency vs Output Current

Figure 84. Output Ripple Voltage (I_OUT= 5 A)

80

60

180

135

90

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 85. Frequency Characteristics (I_OUT= 3 A)

Figure 86. Load Transient Response (I_OUT= 0.1 A to 3.0 A)

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Application Examples – continued

5. V_IN= 12 V, V_OUT= 1 V, f_SW= 1 MHz

Table 13. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

12 V (Typ)

1 V (Typ)

V_IN

V_OUT

I_OUTMAX

f_SW

Output Voltage

Maximum Output Current

Switching Frequency

Operation Mode

5 A

1 MHz (Typ)

Fixed PWM Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 87. Application Circuit

Table 14. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

0.68 μH

FDSD0518-H-R68M

5249

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

10 μF (50 V, X5R, ±20 %)

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

0.1 μF (50 V, X5R, ±10 %)

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

22 μF (25 V, X5R, ±20 %)

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

22 μF (25 V, X5R, ±20 %)

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

2.2 μF (25 V, X5R, ±20 %)

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

27 pF (50 V, C0G, ±5 %)

GRM0335C1H270JA01

Murata

-

R_1A

Short

-

R_1B

180 kΩ (1 %, 1/16 W)

MCR01MZPF1803

1005

-

ROHM

R₂

270 kΩ (1 %, 1/16 W)

MCR01MZPF2703

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

ROHM

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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5. V_IN= 12 V, V_OUT= 1 V, f_SW= 1 MHz – continued

100

90

80

70

60

50

40

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 5 V/div

0

1

2

3

4

5

Output Current : I_OUT[A]

Figure 88. Efficiency vs Output Current

Figure 89. Output Ripple Voltage (I_OUT= 5 A)

80

60

180

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

135

90

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 90. Frequency Characteristics (I_OUT= 3 A)

Figure 91. Load Transient Response (I_OUT= 0 A to 3 A)

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Application Examples – continued

6. V_IN= 12 V, V_OUT= 1 V, f_SW= 600 kHz

Table 15. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

12 V (Typ)

V_IN

V_OUT

I_OUTMAX

f_SW

Output Voltage

1 V (Typ)

Maximum Output Current

Switching Frequency

Operation Mode

5 A

600 kHz (Typ)

Fixed PWM Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 92. Application Circuit

Table 16. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

1.5 μH

FDSD0630-H-1R5N

7066

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

10 μF (50 V, X5R, ±20 %)

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

0.1 μF (50 V, X5R, ±10 %)

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

22 μF (25 V, X5R, ±20 %)

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

22 μF (25 V, X5R, ±20 %)

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

2.2 μF (25 V, X5R, ±20 %)

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

33 pF (50 V, C0G, ±5 %)

GRM0335C1H330JA01

Murata

-

R_1A

Short

-

1005

-

ROHM

R_1B

180 kΩ (1 %, 1/16 W)

MCR01MZPF1803

ROHM

R₂

270 kΩ (1 %, 1/16 W)

MCR01MZPF2703

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

ROHM

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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6. V_IN= 12 V, V_OUT= 1 V, f_SW= 600 kHz – continued

100

90

80

70

60

50

40

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 5 V/div

0

1

2

3

4

5

Output Current : I_OUT[A]

Figure 93. Efficiency vs Output Current

Figure 94. Output Ripple Voltage (I_OUT= 5 A)

80

60

180

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

135

90

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 95. Frequency Characteristics (I_OUT= 3 A)

Figure 96. Load Transient Response (I_OUT= 0 A to 3 A)

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Application Examples – continued

7. V_IN= 12 V, V_OUT= 3.3 V, f_SW= 2.2 MHz

Table 17. Specification of Application

Parameter

Input Voltage

Symbol

Specification Value

12 V (Typ)

V_IN

V_OUT

I_OUTMAX

f_SW

Output Voltage

3.3 V (Typ)

3 A

Maximum Output Current

Switching Frequency

Operation Mode

2.2 MHz (Typ)

Fixed PWM Mode

25 °C

-

Temperature

Ta

BD9F500QUZ

EN

VIN

BOOT

SW

VIN

C_BOOT

C_IN2

C_IN1

VOUT

PGND

VREG

L

R₀

R_S2U

R_S2D

R_S1U

R_S1D

SEL1

R_1A

R_1B

R₂

C_OUT1

C_OUT2

R_PGD

C_FB

C_REG

SEL2

PGD

SS

FB

AGND

PGD

C_SS

Figure 97. Application Circuit

Table 18. Recommended Component Values

Part No.

Value

Part Name

Size Code (mm)

Manufacturer

L

1.0 μH

FDSD0518-H-1R0M

5249

1005

3225

1005

2012

1005

0603

-

Murata

(Note 1)

C_IN1

0.1 μF (50 V, X5R, ±10 %)

10 μF (50 V, X5R, ±20 %)

0.1 μF (50 V, X5R, ±10 %)

22 μF (25 V, X5R, ±20 %)

2.2 μF (25 V, X5R, ±20 %)

33 pF (50 V, C0G, ±5 %)

-

UMK105BJ104KV-F

TAIYO YUDEN

(Note 2)

C_IN2

UMK325BJ106MM-P

TAIYO YUDEN

(Note 3)

C_BOOT

UMK105BJ104KV-F

TAIYO YUDEN

(Note 4)

C_OUT1

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 4)

C_OUT2

TMK212BBJ226MG-TT

TAIYO YUDEN

(Note 5)

C_REG

TMK105CBJ225MV-F

TAIYO YUDEN

C_FB

C_SS

GRM0335C1H330JA01

Murata

-

R_1A

1.5 kΩ (1 %, 1/16 W)

120 kΩ (1 %, 1/16 W)

27 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

Short

MCR01MZPF1500

1005

-

ROHM

R_1B

MCR01MZPF1203

ROHM

R₂

MCR01MZPF2702

ROHM

R_PGD

R_S1U

R_S1D

R_S2U

R_S2D

MCR01MZPF1003

ROHM

-

Short

-

(Note 6)

R₀

Short

-

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C_IN1as close as possible to the VIN pin and the PGND pin.

(Note 2) For the input capacitor C_IN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 3 μF.

(Note 3) For the bootstrap capacitor C_BOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no

less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C_OUT1and C_OUT2

,

the loop response characteristics may change. Confirm with the actual application.

(Note 5) For the VREG capacitor C_REG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less

than 0.82 μF.

(Note 6) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency response

(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.

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7. V_IN= 12 V, V_OUT= 3.3 V, f_SW= 2.2 MHz – continued

100

90

80

70

60

50

40

Time: 1 µs/div

V_OUT: 30 mV/div

V_SW: 5 V/div

0

1

2

3

Output Current : I_OUT[A]

Figure 98. Efficiency vs Output Current

Figure 99. Output Ripple Voltage (I_OUT= 3 A)

80

60

180

Gain

Time: 200 µs/div

V_OUT: 50 mV/div

135

90

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 1 A/div

1

10

100

1000

Frequency [kHz]

Figure 100. Frequency Characteristics (I_OUT= 2 A)

Figure 101. Load Transient Response (I_OUT= 0 A to 2 A)

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Selection of Components Externally Connected

Contact us if not use the recommended component values in Application Examples.

1. Input Capacitor

Use ceramic type capacitor for the input capacitor. The input capacitor is used to reduce the input ripple noise and it is

effective by being placed as close as possible to the VIN pin. Set the capacitor value so that it does not fall to 3 μF

considering the capacitor value variances, temperature characteristics, DC bias characteristics, aging characteristics, and

etc. The PCB layout and the position of the capacitor may lead to IC malfunction. Refer to the notes on the PCB layout on

PCB Layout Design when designing PCB layout. In addition, the capacitor with value 0.1 μF can be connected as close as

possible to the VIN pin and the PGND pin in order to reduce the high frequency noise.

2. Output LC Filter

In order to supply a continuous current to the load, the DC/DC converter requires an LC filter for smoothing the output

voltage. For recommended inductance, use the values listed in Table 19.

V_IN

I_L

Inductor saturation current > I_OUTMAX+ ∆I_L/2

L

V_OUT

Driver

∆I_L

Maximum Output Current I_OUTMAX

C_OUT

t

Figure 102. Waveform of Inductor Current

Figure 103. Output LC Filter Circuit

For example, given that V_IN= 12 V, V_OUT= 3.3 V, L = 1.5 μH, and the switching frequency f_SW= 1.0 MHz, Inductor current

ΔI_Lcan be represented by the following equation.

1

(

)

×

∆퐼_퐿= 푉_푂푈푇× 푉 − 푉_푂푈푇

= ꢄ.595 [A]

ꢀ푁

ꢁ

ꢂꢃ

×푓 ×퐿

푆푊

The rated current of the inductor (Inductor saturation current) must be larger than the sum of the maximum output current

I_OUTMAXand 1/2 of the inductor ripple current ΔI_L.

Use ceramic type capacitor for the output capacitor C_OUT. For recommended actual capacitance, use the values listed in

Table 19. C_OUTaffects the output ripple voltage. Select C_OUTso that it must satisfy the required ripple voltage

characteristics.

The output ripple voltage can be estimated by the following equation.

1

∆푉_푅푃퐿= ∆퐼_퐿× ꢅꢆ_퐸ꢇ푅

+

ꢋ [V]

푆푊

8×퐶

×푓

ꢈꢉꢊ

where:

ꢆ_퐸ꢇ푅is the Equivalent Series Resistance (ESR) of the output capacitor.

For example, given that C_OUT= 44 μF and R_ESR= 3 mΩ, ΔV_RPLcan be calculated as below.

1

∆푉_푅푃퐿= ꢄ.595 퐴 × ꢅ3 푚훺 + _{8×44 휇퐹×1 푀퐻푧}ꢋ = 9.3 [mV]

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2. Output LC Filter – continued

In addition, the total capacitance connected to V_OUTneeds to satisfy the value obtained by the following equation.

푡

∆ꢀ

ꢌ_{푂푈푇푀ꢍ푋}

< +

^{푆푆ꢎꢂꢃ}× (퐼_{푂푈푇푀ꢍ푋}^ꢏ− 퐼_{푂푈푇ꢇꢇ}) [F]

ꢁ 2

ꢈꢉꢊ

where:

ꢐ_{ꢇꢇ푀ꢀ푁}is the minimum soft start time.

푉_푂푈푇is the output voltage.

퐼_{푂푈푇푀ꢍ푋}is the maximum output current.

∆I_Lis the inductor current.

I_OUTSSis the maximum output current during soft start.

For example, given that V_IN= 12 V, V_OUT= 3.3 V, L = 1.5 µH, f_SW= 1 MHz (Typ), t_SSMIN= 1.4 ms (C_SS= OPEN), I_OUTMAX= 5

A, and I_OUTSS= 5 A, C_OUTMAXcan be calculated as below.

ꢌ_{푂푈푇푀ꢍ푋}

<

^{1.4 ꢑ푠}× (5 퐴 + ^{1.ꢓꢔꢓ ꢍ}− 5 퐴) = 33ꢕ [µF]

ꢒ.ꢒ ꢁ 2

If the total capacitance connected to V_OUTis larger than C_OUTMAX, over current protection may be activated by the inrush

current at startup and prevented to turn on the output. Confirm this on the actual application.

Table 19. Recommended inductance and output capacitance

(Note 1)

Frequency

[MHz]

C_{OUT_EFF}

[μF]

V_IN[V]

V_OUT[V]

I_OUTMAX[A]

Inductor L[μH]

0.6

12

24

5

3.3

1

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

5

3

3.3

4.7

3.3

4.7

2.2

1.5

4.7

5.6

4.7

5.6

6.8

8.2

1.5

2.2

1.5

2.2

1

1.5

0.68

1

0.68

1

3.3

4.7

5.6

1

25 to 50

0.6

1

25 to 50

35 to 50

30 to 50

45 to 60

25 to 50

20 to 50

30 to 50

20 to 50

5

12

5

12

24

12

24

5

12

3.3

1

5

12

3.3

5

12

5

1

2.2

5

12

24

12

24

2.2

1

(Note 1) C_{OUT_EFF}is the sum of actual output capacitance.

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Selection of Components Externally Connected – continued

3. Output Voltage Setting, FB Capacitor

The output voltage can be set by the feedback resistance ratio connected to the FB pin. For recommended R₁and R₂, use

the values listed in Table 20.

V_OUT

The output voltage V_OUTcan be calculated as below.

C_FB

R₁

푅 ꢗ푅

ꢖ

^ꢘ× 0.6 [V]

푅

ꢘ

Error Amplifier

푉_푂푈푇

=

FB

0.6 ≤ 푉_푂푈푇≤ ꢄꢙ [V]

R₂

0.6 V

(Typ)

푉_푂푈푇≤ (푉 × 0.ꢕ) [V]

ꢀ푁

Figure 104. Feedback Resistor Circuit

The Constant On-Time control required the sufficient ripple voltage on FB voltage for the operation stability. This device is

designed to correspond to low ESR output capacitors by injecting the ripple voltage to FB voltage inside the IC. The FB

capacitor C_FBshould be set with the following expression as typical value in order to inject an appropriate ripple. For

recommended C_FB, use the values listed in Table 20.

600 kHz setting

⁄

ꢁ

×(1ꢚꢁ

ꢁ

ꢜ

)

ꢈꢉꢊ

ꢂꢃ

ꢌ_퐹퐵

=

[F]

푓

×ꢓ.2ꢓ×1ꢛ

푆푊

where:

is the input voltage.

푉

ꢀ푁

푉_푂푈푇is the output voltage.

f_SWis the switching frequency 600 kHz (Typ).

1MHz, 2.2MHz setting

⁄

ꢁ

×(1ꢚꢁ

ꢁ

ꢂꢃ

)

ꢈꢉꢊ

ꢌ_퐹퐵

=

[F]

ꢜ

푓

×ꢒ.ꢓ×1ꢛ

푆푊

where:

is the input voltage.

푉

ꢀ푁

푉_푂푈푇is the output voltage.

f_SWis the switching frequency 1 MHz, 2.2 MHz (Typ).

Load transient response and the loop stability depends on L, C_OUT, R₁, R₂, and C_FB. Actually, these characteristics may

change depending on PCB layout, wiring, the type of components, and the conditions (temperature, etc.). Be sure to

check them on the actual application.

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3. Output Voltage Setting, FB Capacitor – continued

Table 20. Recommended feedback resistance, C_FBcapacitance

Frequency

[MHz]

V_IN[V]

V_OUT[V]

R₁[kΩ]

R₂[kΩ]

C_FB[pF]

0.6

12

24

5

12

5

12

24

12

24

5

3.3

1

5

1.5 + 120

120 + 330

180

27

100

270

30

33

27

100

270

30

33

82

39

33

27

100

180

82

33

27

22

100

180

33

0.6

1

2.2

180

220

5

12

3.3

1

5

68 + 560

1.5 + 120

120 + 330

180

12

5

180

220

12

24

12

24

12

3.3

68 + 560

1.5 + 120

27

33

4. Soft Start Capacitor (Soft Start Time Setting)

The soft start time t_SSdepends on the value of the capacitor connected to the SS pin. The t_SSis 2 ms (Typ) when the SS

pin is left floating. The capacitor connected to the SS pin makes t_SSmore than 2 ms. The t_SSand C_SScan be calculated

using below equation. The C_SSshould be set in the range between 0.01 μF and 0.1 μF.

퐶

푆푆

×ꢛ.ꢝ×1.ꢒ

ꢐ_ꢇꢇ=

[s]

ꢀ

푆푆

where:

퐼_ꢇꢇis the Soft Start Charge Current 2.0 µA (Typ).

With C_SS= 0.022 μF, t_SScan be calculated as below.

ꢛ.ꢛ22 휇퐹×ꢛ.ꢝ×1.ꢒ

ꢐ_ꢇꢇ=

= ꢕ.5ꢕ [ms]

2.ꢛ 휇ꢍ

5. VREG Capacitor

The VREG capacitor 2.2 μF is recommended. Connect the capacitor between the VREG pin and the AGND pin. For the

capacitance, take temperature characteristics, DC bias characteristics, and etc. into consideration to set to the actual

capacitance of no less than 0.82 μF.

6. Bootstrap Capacitor

The bootstrap capacitor 0.1 μF is recommended. Connect the capacitor between the SW pin and the BOOT pin. For the

capacitance, take temperature characteristics, DC bias characteristics, and etc. into consideration to set to the actual

capacitance of no less than 0.022 μF.

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PCB Layout Design

PCB layout design for DC/DC converter is very important. Appropriate layout can avoid various problems concerning power

supply circuit. Figure 105-a to Figure 105-c show the current path in a buck DC/DC converter circuit. The Loop 1 in Figure

105-a is a current path when H-side switch is ON and L-side switch is OFF, the Loop 2 in Figure 105-b is when H-side switch is

OFF and L-side switch is ON. The thick line in Figure 105-c shows the difference between Loop1 and Loop2. The current in

thick line change sharply each time the switching element H-side and L-side switch change from OFF to ON, and vice versa.

These sharp changes induce a waveform with harmonics in this loop. Therefore, the loop area of thick line that is consisted by

input capacitor and IC should be as small as possible to minimize noise. For more details, refer to application note of switching

regulator series “PCB Layout Techniques of Buck Converter”.

Loop1

V_IN

V_OUT

L

H-side Switch

C_IN

C_OUT

L-side Switch

GND

Figure 105-a. Current Path when H-side Switch = ON, L-side Switch = OFF

V_IN

V_OUT

L

H-side Switch

C_IN

C_OUT

Loop2

L-side Switch

GND

Figure 105-b. Current Path when H-side Switch = OFF, L-side Switch = ON

V_IN

V_OUT

L

C_IN

C_OUT

High-Side FET

Low-Side FET

GND

Figure 105-c. Difference of Current and Critical Area in Layout

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PCB Layout Design – continued

When designing the PCB layout, pay attention to the following points:

•

Connect the input capacitor C_IN1and C_IN2as close as possible to the VIN pin and the PGND pin on the same plane as

the IC.

Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the inductor pattern L

as thick and as short as possible.

•

The feedback line connected to the FB pin should be as far away from the SW nodes as possible.

Place the output capacitor C_OUTaway from input capacitor C_IN1and C_IN2to avoid harmonics noise from the input.

Separate the reference ground and the power ground and connect them through VIA. The reference ground should be

connected to the power ground that is close to the output capacitor C_OUT. It is because C_OUThas less high frequency

switching noise.

•

To provide excellent heat dissipation characteristics connect the VIN pins to the PCB VIN pattern by using thermal vias.

Place the bypass capacitor between the VREG and AGND pins at a position as close as possible to the pin.

When the SEL1 and SEL2 pins are left open, the parasitic capacitance with the VIN, SW, and BOOT pins should be 0.2

pF or less.

•

R₀is provided for the measurement of feedback frequency characteristics (optional). By inserting a resistor into R₀, it is

possible to measure the frequency characteristics of feedback (phase margin) using FRA etc. R₀is short-circuited for

normal use.

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PCB Layout Design – continued

R₂

R_1B

R_1A

R₀

C_REG

(2.2 μF)

R_S2UR_S2D

R_S1UR_S1D

C_FB

12

11

10

9

C_SS

13

14

15

16

8

7

6

5

VIN

SW

R_PGD

PGD

AGND

SS

18

17

EN

PGD

C_BOOT

(0.1 μF)

VIN

BOOT

VIN

VOUT

GND

VIN

SW

L

C_IN2

(10 μF)

C_IN1

(0.1 μF)

3

4

1

2

C_OUT2

C_OUT1

GND

Figure 106. Application Circuit

Thermal VIA

Signal VIA

BD9F500QUZ

VIN

C_{BO OT}

L

VOUT

Pin 1

GND

Top Layer

Inner1 Layer

VIN

GND

Inner2 Layer

Bottom Layer

Figure 107. Example of PCB Layout

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I/O Equivalence Circuits

5, 17. SW

6. BOOT

VIN

BOOT

VREG

VIN

BOOT

SW

30 Ω

350 Ω

SW

VREG

100 kΩ

7. PGD

8. SS

PGD

10 kΩ

100 Ω

3 kΩ

25 kΩ

SS

300 Ω

9. SEL1, 10. SEL2

VREG

11. VREG

VREG

VIN

BOOT

10 kΩ

20 kΩ

VREG

2.5 MΩ

SEL1

SEL2

10 kΩ

5 MΩ

1.5 MΩ

12. FB

14.EN

VREG

20 kΩ

EN

10 kΩ

50 kΩ

100 kΩ

FB

(Note) Resistor values are typical.

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Operational Notes

1.

2.

3.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground

due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below

ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions

such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

4.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 108. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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Ordering Information

B D 9

F

5

0

Q U Z -

E 2

Package

VMMP16LZ3030

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

VMMP16LZ3030 (TOP VIEW)

Part Number Marking

D 9 F

5 0 0

LOT Number

Pin 1 Mark

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Physical Dimension and Packing Information

Package Name

VMMP16LZ3030

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Revision History

Date

Revision

001

Changes

02.Apr.2020

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BD9F500QUZ
厂家：	ROHM
描述：	BD9F500QUZ是内置低导通电阻的功率MOSFET的同步整流降压DC/DC转换器。最大可输出5A的电流。采用恒定时间控制方式，具有高速负载响应性能。通过轻负载模式控制，可以改善轻负载下的效率，适用于要降低待机功耗的设备。具有电源良好输出功能，可进行系统的时序控制。采用小型封装，可在大功率密度下减少贴装面积。Power Supply Reference BoardFor Xilinx’s FPGA Spartan-7 转换器
文件：	总58页 (文件大小：3269K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9F500QUZ [ROHM]

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