BD39042MUF-C [ROHM]
BD39042MUF-C是一款具有4路Power Good信号、看门狗定时器和复位功能的监控IC。使用该IC可以轻松提高现有系统的ASIL等级。BD39042MUF-C还具有内建自测试(BIST)功能。;型号: | BD39042MUF-C |
厂家: | ROHM |
描述: | BD39042MUF-C是一款具有4路Power Good信号、看门狗定时器和复位功能的监控IC。使用该IC可以轻松提高现有系统的ASIL等级。BD39042MUF-C还具有内建自测试(BIST)功能。 监控 测试 |
文件: | 总29页 (文件大小:1197K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
Supervisor IC
System Power Good + Watchdog Timer +
Reset for Automotive
BD39042MUF-C
General Description
Key Specifications
BD39042MUF-C is a supervisor IC with quad power good,
Watchdog timer and reset. This IC enables existing
system to improve its ASIL level easily.
◼ VDD Input Voltage Range:
2.7 V to 5.5 V
(VDD voltage level needs to be fixed within this range
in 6 % accuracy to avoid RSTIN reset detection)
◼ Detection Voltage (VDD POR / Power Good)
BD39042MUF-C includes built-in self-test (BIST).
Under Voltage Detection:
Over Voltage Detection:
Reset Assertion Delay Time:
-6 % (1.4 % accuracy)
+6 % (1.4 % accuracy)
10 ms
Features
◼ AEC-Q100 Qualified(Note 1)
Power Good Assertion Delay Time:
10 ms
◼ Functional Safety Supportive Automotive Products
◼ Quad Power Good for External Inputs
◼ Over Voltage Detection (OVD)
◼ Under Voltage Detection (UVD)
◼ Adjustable Window Watchdog Timer(WDT)
◼ Reset for VDD Input (POR)
◼ Operating Temperature Range:
-40 °C to +125 °C
Package
VQFN16FV3030
W (Typ) x D (Typ) x H (Max)
3.0 mm x 3.0 mm x 1.0 mm
◼ Built-in Self-test (BIST)
(Note 1) Grade 1
Applications
Enlarged View
◼ Automotive for ADAS
◼ Camera Module
◼ Microwave Module
◼ Power Train ECU
◼ Other ECU
VQFN16FV3030
Wettable Flank Package
Typical Application Circuit
Battery
VO1
VDD
RSTIN
XRSTOUT
PG1
VDD
VDD
VDD
VDD
VO2
DIN1
VO3
DIN2
PG2
PG3
PMIC/
Discrete DCDC
VO4
DIN3
Processor
BD39042MUF-C
VDD
VO5
DIN4
PG4
WDIN
WDEN
RTW
WDOUT
GND
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD39042MUF-C
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Block Diagram ................................................................................................................................................................................4
Absolute Maximum Ratings ............................................................................................................................................................9
Thermal Resistance........................................................................................................................................................................9
Recommended Operating Conditions.............................................................................................................................................9
Electrical Characteristics...............................................................................................................................................................10
Typical Performance Curves.........................................................................................................................................................12
Timing Chart .................................................................................................................................................................................16
Application Example .....................................................................................................................................................................20
Operational Notes.........................................................................................................................................................................22
Ordering Information.....................................................................................................................................................................24
Marking Diagram ..........................................................................................................................................................................24
Physical Dimension and Packing Information...............................................................................................................................25
Revision History............................................................................................................................................................................26
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BD39042MUF-C
Pin Configuration
(TOP View)
12
11
10
9
WDEN 13
WDIN 14
8
7
6
5
PG2
DIN2
EXP-PAD
XRSTOUT 15
WDOUT 16
PG1
DIN1
1
2
3
4
Pin Descriptions
Pin No.
1
Pin Name
VDD
Function
IC’s Power Source
The VDD pin voltage divided by external resistor input pin. Normal voltage level
needs to be 0.8 V.
IC’s Power Ground
WDT frequency setting pin. FAST Timeout and SLOW Timeout is adjusted by the
resistor value for this pin.
2
3
4
RSTIN
GND
RTW
Voltage for monitoring channel divided by external resistor input pin. Normal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN1 pin, and Nch Open Drain output.
Hi-Z for normal and Low for abnormal (reset). Please be pulled-up by external
resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Normal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN2 pin, and Nch Open Drain output.
Hi-Z for normal and Low for abnormal (reset). Please be pulled-up by external
resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Normal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN3 pin, and Nch Open Drain output.
Hi-Z for normal and Low for abnormal (reset). Please be pulled-up by external
resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Normal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN4 pin, and Nch Open Drain output.
Hi-Z for normal and Low for abnormal (reset). Please be pulled-up by external
resistor.
DIN1
PG1
DIN2
PG2
DIN3
PG3
DIN4
PG4
5
6
7
8
9
10
11
12
It can be pulled-up to any voltage source.
WDEN
WDIN
Enable pin for WDT. High = Active, Low = Disable and WDT error is ignored.
Clock input pin for WDT
13
14
Reset output pin. Nch Open Drain output.
Hi-Z for normal and Low for abnormal (reset). Please be pulled-up by external
resistor.
It can be pulled-up to any voltage source. Either error of OVD, UVD for RSTIN,
reference voltage monitoring, internal OSC monitoring, WDT and BIST at power-
up sequence causes this pin to drive low.
XRSTOUT
15
Buffer output pin for the WDEN pin input. Abnormal Power Source / the GND pin
shortage for the WDEN pin can be recognized by monitoring this pin. This pin
becomes Low when the XRSTOUT pin is low.
WDOUT
16
-
EXP-PAD
The EXP-PAD is connected to the PCB Ground plane.
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Block Diagram
VDD
VREF
VREF_SUB
UVLO
VREF_DET
VREF_DET
VREF_DET
RSTIN_DET
BIST_ERROR
WDT_DET
BIST_EN
XRSTOUT
UVLO
CLK_DET
WDT_OSC_DET
XRSTOUT_DET
OVD
+
RSTIN
OVD_RST
UVD_RST
-
RSTIN_DET
BIST_EN
UVD
Filter
Counter
-
+
VREF_DET
OVD_RST
UVD_RST
BIST_ERROR
BIST_EN
BIST
OVD1,OVD2,
OVD3,OVD4
OVD2
OVD
BIST_EN
DIN1
UVD1,UVD2,
UVD3,UVD4
+
OVD1
UVD1
VREF
-
VREF_DET
Counter
PG1
BIST_EN
Filter
Filter
Filter
UVD
-
+
BIST_EN
DIN2
OVD
+
OVD2
UVD2
VREF
-
VREF_DET
Counter
PG2
PG3
PG4
BIST_EN
UVD
-
+
DIGITAL
BIST_EN
OVD
+
DIN3
DIN4
OVD3
UVD3
VREF
-
VREF_DET
Counter
BIST_EN
UVD
-
+
BIST_EN
OVD
+
OVD4
UVD4
VREF
-
VREF_DET
Counter
BIST_EN
UVD
Filter
-
+
BIST_EN
DIGITAL_OSC
CLK_DET
CLK_DET
RTW
WDT_OSC
WDT_OSC_DET
WDT_DET
WDT
WDIN
VDD
WDOUT
XRSTOUT_DET
Counter
WDEN
UVLO
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BD39042MUF-C
Block Diagrams - continued
Description of Blocks
Reference Voltage (VREF)
VREF is reference voltage of each input voltage.
Reference Voltage (VREF_SUB)
VREF_SUB is reference voltage of VREF_DET.
Reference Voltage (VREF_DET)
This monitors the 2 reference voltage, VREF and VREF_SUB.
This block contributes to high reliability by continuously and mutually monitoring correct operation.
Occurrence of error leads to Low output at the XRSTOUT pin and which is never de-asserted as long as abnormal status
lasts. It becomes High at 10 ms (Typ) after the voltage returned to the normal range.
Under Voltage Lockout Circuit (UVLO)
Protection circuit to prevent internal circuit from malfunction at lower voltage (Power-up sequence or input power supply drop).
This monitors the VDD pin voltage and UVLO works when it goes down to threshold level.
As UVLO is detected, the XRSTOUT, WDOUT, PG1, PG2, PG3 and PG4 pins output Low. Also Counter value in DIGITAL
BLOCK is initialized and DIGITAL_OSC/WDT_OSC stop working.
Oscillator (DIGITAL_OSC)
This OSC generates the clock to control DIGITAL BLOCK. The frequency of DIGITAL_OSC is fixed at 2.2 MHz.
Oscillator (WDT_OSC)
This OSC generates the clock to control WDT.
The frequency of WDT_OSC is possible to be adjusted by the resistor value, so that FAST Timeout / SLOW Timeout is
changed by that.
WDT_OSC has the function to stop its working when the external resistor at the RTW pin is shorted or OPEN
(WDT_OSC_DET). Once CLK_DET is detected, XRSTOUT becomes Low.
Oscillator (CLK_DET)
This block monitors both DIGITAL_OSC and WDT_OSC.
2 OSCs always monitor their frequency each other and it leads to the higher reliability.
When an error happened at the monitoring, XRSTOUT becomes Low.
Over Voltage Detection (OVD1, OVD2, OVD3, OVD4, OVD_RST)
When input voltage goes over the threshold level, OVD is detected and the PG1, PG2, PG3 and PG4 pins are driven by Low.
Detecting pins are DIN1, DIN2, DIN3 and DIN4 and RSTIN. OVD detection for the DIN1, DIN2, DIN3 and DIN4 pins causes
corresponding the PG1, PG2, PG3 and PG4 pins to become Low. OVD detection for RSTIN causes the XRSTOUT pin to
become Low. These output signals become High at 10 ms (Typ) after each input pin returns within the normal voltage range.
And each input has a filter in DIGITAL BLOCK, then overshoot within 50 µs (Min) is ignored.
Under Voltage Detection (UVD1, UVD2, UVD3, UVD4, UVD_RST)
When input voltage goes below the threshold level, UVD is detected and the PG1, PG2, PG3 and PG4 pins are driven by
Low. Detecting pins are DIN1, DIN2, DIN3, DIN4 and RSTIN. UVD detection for the DIN1, DIN2, DIN3 and DIN4 pins causes
corresponding the PG1, PG2, PG3 and PG4 pins to become Low. UVD detection for RSTIN causes the XRSTOUT pin to
become Low. These output signals become High at 10 ms (Typ) after each input pin returns within the normal voltage range.
And each input has a filter in DIGITAL BLOCK, then undershoot within 50 µs (Min) is ignored.
BIST
When VDD Power on Reset (monitoring the RSTIN pin) is released, BIST is performed and self-test for DIN1, DIN2, DIN3,
DIN4, RSTIN and VREF_DET comparators are executed to see if each comparator correctly toggles their High/Low output
based on input level change.
BIST time (tBIST) is 2 ms (Max). Once BIST ends without any errors, XRSTOUT becomes High. If an error is found during
BIST, XRSTOUT keeps Low and BIST is repeated until it passes.
Watchdog Timer (WDT)
Watchdog Timer (WDT) monitors microprocessor’s operation by detecting the time from both rise and fall edge of WDIN. If
BIST result is abnormal, WDT does not work and XRSTOUT is kept low. WDT is activated when WDOUT = High, and both
WDEN and XRSTOUT have to be High in order to get WDOUT to be High.
As long as the duty of WDIN clock is kept within “Trigger open window” in Figure 1, WDT does not detect any errors and
XRSTOUT stays at High. Sequence for FAST Timeout and SLOW Timeout are shown in Figure 2 and Figure 3.
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Description of Blocks - continued
WDT Start from rising of WDOUT
Detecti on guaranteed
Detecti on guaranteed
WDT
Fast Timeout
WDT
SLOW Ti meout
WDT
Trigger open window
WDIN
tWF (Mi n)
tWF (Max)
t[ms]
tO K(Typ)
tWS (Mi n)
tWS (Max)
Figure 1. WDT Window Description
WDT FAST Timeout Detection
1. WDIN input signal is ignored when WDOUT = Low. WDT is activated when WDOUT = High, and both WDEN and
XRSTOUT have to be High in order to get WDOUT to be High.
2. For the initial duration just after WDOUT goes to High, only SLOW Timeout detection works and FAST Timeout does not
work. Either Low or High input to the WDIN pin is acceptable as initial level. Once rising-up or falling-down edge of WDIN
comes within SLOW Timeout, both FAST Timeout and SLOW Timeout detections start to work.
3. These time detection monitors the time until next edge and when it detects WDIN edge within FAST Timeout (tWF),
XRSTOUT and WDOUT becomes Low. XRSTOUT goes back to High after 10 ms (Typ) delay, while WDOUT goes back
to High after tWDIM (500 ms: Typ) in addition to tXRSTOUT (10 ms: Typ) as long as WDEN = High.
tWDIM is implemented as a time for microprocessor to be reset normally and stabilized.
If this time is unnecessary and WDT should be activated as soon as possible, WDEN may be controlled like state 5 in
the Figure 2.
WDEN toggle during XRSTOUT = Low is ignored.
4. When WDOUT becomes High, WDT is activated again and operation resumes.
Only SLOW Timeout detection works until the next first edge, and both SLOW Timeout and FAST Timeout starts at the
first edge like state 1 in Figure 2.
5. If this time is unnecessary and WDT should be activated as soon as possible, WDEN may be controlled like in Figure 2.
tWDIM is canceled by toggling WDEN like High->Low->High and WDT is activated immediately even during tWDIM
After WDT is enabled it works as same as state 2 in Figure 2.
.
6. When WDEN is Low, WDOUT becomes Low and WDT is disabled. During this period WDIN input signal is ignored and
XRSTOUT output is not affected by that.
FAST Timeout
FAST Timeout
Ignored
Ignored
Ignored
Ignored
OK
OK
OK
OK
Ignored OK
OK
OK
OK
WDIN
Enable:ON
Enable:OFF
Enable:ON
O.K.
Enable:OFF
WDEN
Ignored
SLOW
Timeout
SLOW
Timeout
SLOW
Timeout
O.K.
O.K.
tWS
FAST
Timeout
SLOW
Timeout
FAST
Timeout
SLOW
Timeout
O.K.
O.K.
FAST
Timeout
SLOW
Timeout
O.K.
FAST
Timeout
SLOW
Timeout
FAST
Timeout
SLOW
Timeout
tWF
tWS
O.K.
O.K.
Only SLOW Timeout is monitored for
the first edge right after WDOUT = High
FAST
Timeout
SLOW
Timeout
O.K.
FAST
Timeout
SLOW
Timeout
O.K.
FAST
Timeout
SLOW
Timeout
O.K.
tXRSTOUT
10 ms
tXRSTOUT
10 ms
XRSTOUT
WDOUT
tXRSTOUT
10 ms
tWDIM
500 ms
tXRSTOUT
10 ms
tWDIM
5500 ms
6
state
1
2
3
4
Figure 2. WDT FAST Timeout Detection
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BD39042MUF-C
Block Diagrams - continued
WDT SLOW Timeout Detection
1. WDIN input signal is ignored when WDOUT = Low. WDT is activated when WDOUT = High, and both WDEN and
XRSTOUT have to be High in order to get WDOUT to be High.
2. For the initial duration just after WDOUT goes to High, only SLOW Timeout detection works and FAST Timeout does not
work. Either Low or High input to the WDIN pin is acceptable as initial level. Once rising-up or falling-down edge of WDIN
comes within SLOW Timeout, both FAST Timeout and SLOW Timeout detections start to work.
3. These time detection monitors the time until next edge and when it cannot detect WDIN edge within SLOW Timeout (tWS),
XRSTOUT and WDOUT becomes Low. XRSTOUT goes back to High after 10 ms (Typ) delay, while WDOUT goes back
to High after tWDIM (500 ms: Typ) in addition to tXRSTOUT (10 ms: Typ) as long as WDEN = High.
tWDIM is implemented as a time for microprocessor to be reset normally and stabilized.
If this time is unnecessary and WDT should be activated as soon as possible, WDEN may be controlled like state 5 in
the Figure 3.
WDEN toggle during XRSTOUT = Low is ignored.
4. When WDOUT becomes High, WDT is activated again and operation resumes.
Only SLOW Timeout detection works until the next first edge, and both SLOW Timeout and FAST Timeout starts at the
first edge like state 1 in Figure 3.
5. If this time is unnecessary and WDT should be activated as soon as possible, WDEN may be controlled like the Figure
3. tWDIM is canceled by toggling WDEN like High->Low->High and WDT is activated immediately even during tWDIM
After WDT is enabled it works as same as state 2 in Figure 3.
.
6. When WDEN is Low, WDOUT becomes Low and WDT is disabled. During this period WDIN input signal is ignored and
XRSTOUT output is not affected by that.
SLOW Timeout
SLOW Timeout
Ignored
Ignored
Ignored
Ignored
OK
OK
OK
Ignored OK
OK
OK
WDIN
Enable:ON
Enable:OFF
Enable:ON
Enable:OFF
Ignored
WDEN
SLOW
Timeout
SLOW
Timeout
SLOW
Timeout
O.K.
tWS
O.K.
O.K.
FAST
Timeout
SLOW
Timeout
FAST
Timeout
SLOW
Timeout
O.K.
O.K.
FAST
Timeout
SLOW
Timeout
O.K.
tWF
tWS
FAST
Timeout
SLOW
Timeout
O.K.
Only SLOW Timeout is monitored for
the first edge right after WDOUT = High
FAST
Timeout
SLOW
Timeout
O.K.
FAST
Timeout
SLOW
Timeout
O.K.
tXRSTOUT
10 ms
tXRSTOUT
10 ms
XRSTOUT
WDOUT
tXRSTOUT
10 ms
tXRSTOUT
10 ms
tWDIM
500 ms
tWDIM
500 ms
5
state
1
2
3
4
6
Figure 3. WDT SLOW Timeout Detection
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BD39042MUF-C
WDT SLOW Timeout Detection - continued
SLOW Timeout
Ignored
SLOW Timeout
SLOW Timeout
SLOW Timeout
WDIN
Enable:ON
WDEN
SLOW
Timeout
SLOW
Timeout
SLOW
Timeout
SLOW
Timeout
O.K.
O.K.
O.K.
O.K.
tWS
tWS
tWS
tWS
WDT
WDT Enabled
Disabled
tXRSTOUT
10 ms
tXRSTOUT
10 ms
tXRSTOUT
10 ms
tXRSTOUT
10 ms
XRSTOUT
tXRSTOUT
10 ms
tWDIM
500 ms
tXRSTOUT
10 ms
tXRSTOUT
10 ms
tWDIM
500 ms
tXRSTOUT
10 ms
tWDIM
500 ms
tWDIM
500 ms
WDOUT
Figure 4. XRSTOUT Behavior with Continuous WDT Timeout Detected
The window time for detection can be changed by the resistor value between the RTW and GND pins. Following figure shows
the detection time determined by RRTW resistor value. Please refer to a table of electric characteristic regarding accuracy.
Customer can choose the value ranging from 10 kΩ to 47 kΩ according to their clock frequency. The ratio for detection time
is fixed and can be shown like this, FAST Timeout: SLOW Timeout = 1 : 2.
WDT Detection Time vs RRTW
130
120
SLOW Timeout Detect Area guaranteed
110
100
90
80
70
60
50
40
30
20
10
0
SLOW Timeout Detect
FAST/SLOW Normal time
FAST Timeout Detect
FAST Timeout Detect Area guaranteed
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
RRTW[kΩ]
Figure 5. Detection Time vs RRTW
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BD39042MUF-C
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VDD Voltage
VDD
-0.3 to +7
-0.3 to +7
V
V
RSTIN Voltage
VRSTIN
VDIN1, VDIN2,
VDIN3, VDIN4
DIN1, DIN2, DIN3, DIN4 Voltage
XRSTOUT Voltage
-0.3 to +7
-0.3 to +7
-0.3 to +7
V
V
V
VXRSTOUT
VPG1, VPG2,
VPG3, VPG4
PG1, PG2, PG3, PG4 Voltage
WDIN Voltage
VWDIN
-0.3 to +7
V
WDEN Voltage
VWDEN
VWDOUT
VRTW
-0.3 to +7
-0.3 to VDD+0.3(Note 1)
-0.3 to VDD+0.3(Note 1)
150
V
V
WDOUT Voltage
RTW Voltage
V
Maximum Junction Temperature
Tjmax
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Maximum voltage is 7 V.
Thermal Resistance (Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
VQFN16FV3030
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
189.0
23
57.5
10
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70 μm
Footprints and Traces
Layer Number of
Measurement Board
Thermal Via(Note 5)
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
Footprints and Traces
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
+125
Unit
Operating Ambient Temperature
VDD Voltage
Topr
VDD
-40
2.7
10
-
-
-
-
-
°C
V
5.5
125
100
WDIN Input Pulse Width
tWDIN
tWDP
ms
μs
WDIN Minimum ON Pulse / OFF Pulse
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BD39042MUF-C
Electrical Characteristics (Unless otherwise specified VDD = 2.7 V to 5.5 V, -40 °C ≤ Ta ≤ +125 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
All
VDD = 4.1 V, RRTW = 27 kΩ,
XRSTOUT, PG1, PG2, PG3, PG4
= H
IVDD
465
810
1345
2.65
µA
V
Circuit Current
VDD Power On Reset Threshold
Voltage (Falling)
VDD Power On Reset Threshold
Voltage (Rising)
VVDDUV1
2.25
2.50
VDD monitor
VDD monitor
VVDDUV2
VVDDHYS
2.30
-
2.55
50
2.70
-
V
mV
VDD Power On Reset Hysteresis
Power Good
DIN1 Power Good Low Detect
Voltage
DIN1 Power Good High Detect
Voltage
VUVD1
VOVD1
0.7415 0.7520 0.7625
0.8362 0.8480 0.8598
V
V
DIN1 Pin Voltage=Sweep down
DIN1 Pin Voltage=Sweep up
DIN1 Input Filter Time
PG1 Low Voltage
tDIN1
VPG1L
ILPG1
tPG1
50
-
75
-
100
0.3
2
µs
V
IPG1 = 1 mA
VPG1 = 5.5 V
-
-
µA
ms
PG1 Leak Current
7
10
13
PG1 Assertion Delay Time
DIN2 Power Good Low Detect
Voltage
DIN2 Power Good High Detect
Voltage
VUVD2
VOVD2
0.7415 0.7520 0.7625
0.8362 0.8480 0.8598
V
V
DIN2 Pin Voltage = Sweep down
DIN2 Pin Voltage = Sweep up
DIN2 Input Filter Time
PG2 Low Voltage
tDIN2
VPG2L
ILPG2
tPG2
50
-
75
-
100
0.3
2
µs
V
IPG2 = 1 mA
VPG2 = 5.5 V
PG2 Leak Current
-
-
µA
ms
PG2 Assertion Delay Time
7
10
13
DIN3 Power Good Low Detect
Voltage
DIN3 Power Good High Detect
Voltage
VUVD3
VOVD3
0.7415 0.7520 0.7625
0.8362 0.8480 0.8598
V
V
DIN3 Pin Voltage = Sweep down
DIN3 Pin Voltage = Sweep up
DIN3 Input Filter Time
PG3 Low Voltage
tDIN3
VPG3L
ILPG3
tPG3
50
-
75
-
100
0.3
2
µs
V
IPG3 = 1 mA
VPG3 = 5.5 V
PG3 Leak Current
-
-
µA
ms
PG3 Assertion Delay Time
7
10
13
DIN4 Power Good Low Detect
Voltage
DIN4 Power Good High Detect
Voltage
DIN4 Pin Voltage = Sweep down
DIN4 Pin Voltage = Sweep up
VUVD4
VOVD4
0.7415 0.7520 0.7625
0.8362 0.8480 0.8598
V
V
DIN4 Input Filter Time
PG4 Low Voltage
tDIN4
VPG4L
ILPG4
tPG4
50
-
75
-
100
0.3
2
µs
V
IPG4 = 1 mA
VPG4 = 5.5 V
PG4 Leak Current
-
-
µA
ms
PG4 Assertion Delay Time
7
10
13
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BD39042MUF-C
Electrical Characteristics (Unless otherwise specified VDD=2.7 V to 5.5 V, -40 °C ≤ Ta ≤ +125 °C) - continued
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
VDD Power On Reset
RSTIN Power Good Low Detect
Voltage
RSTIN Power Good High Detect
Voltage
RSTIN Pin Voltage = Sweep
down
RSTIN Pin Voltage = Sweep
up
VUVDRST
VOVDRST
0.7415 0.7520
0.8362 0.8480
0.7625
0.8598
V
V
RSTIN Input Filter Time
XRSTOUT Low Voltage
XRSTOUT Leak Current
XRSTOUT Assertion Delay Time
Watch Dog Timer
tRSTIN
VXRSTL
IXRST
50
-
75
-
100
0.3
10
µs
V
IXRSTOUT = 1 mA
VXRSTOUT = 5.5 V
-
-
µA
ms
tXRSTOUT
7
10
13
FAST Timeout Detect1
tWF1
tWS1
tOK1
9.0
17.9
13.6
24.4
48.8
36.7
42.5
85.0
63.9
20
11.2
22.4
15.7
30.5
61.0
42.7
53.2
106.3
74.4
-
13.5
26.9
17.8
36.6
73.2
48.7
63.8
127.6
84.9
-
ms
ms
ms
ms
ms
ms
ms
ms
ms
µs
RRTW = 10 kΩ
RRTW = 10 kΩ
RRTW = 10 kΩ
RRTW = 27 kΩ
RRTW = 27 kΩ
RRTW = 27 kΩ
RRTW = 47 kΩ
RRTW = 47 kΩ
RRTW = 47 kΩ
SLOW Timeout Detect1
FAST/SLOW Normal Time1
FAST Timeout Detect2
tWF2
tWS2
tOK2
SLOW Timeout Detect2
FAST/SLOW Normal Time2
FAST Timeout Detect3
tWF3
tWS3
tOK3
SLOW Timeout Detect3
FAST/SLOW Normal Time3
WDIN Detect Minimum Pulse Width
WDIN Initial Mask Time
WDIN Pull-down Resistor Value
tWDIN
tWDIM
RWDIN
325
50
500
100
675
150
ms
kΩ
VDD < 5 V
0.2
x VDD
WDIN Low Level Input Voltage
VWDINL
-
-
V
0.8
x VDD
WDIN High Level Input Voltage
WDEN Pull-down Resistor Value
WDEN Low Level Input Voltage
VWDINH
RWDEN
VWDENL
-
100
-
-
V
kΩ
V
50
150
VDD < 5 V
0.2
x VDD
-
0.8
x VDD
VDD
WDEN High Level Input Voltage
VWDENH
-
-
-
V
IWDOUT = -3 mA
IWDOUT = +3 mA
WDOUT Output High Voltage
WDOUT Output Low Voltage
VOHWDO
VOLWDO
-
V
V
-0.3
-
-
0.3
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BD39042MUF-C
Typical Performance Curves
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
VDD = 2.7 V
VDD = 4.1 V
VDD = 5.5 V
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDD Voltage : VDD [V]
-40 -25 -10 5 20 35 50 65 80 95 110125
Temperature [℃]
Figure 6. Circuit Current vs VDD Voltage
Figure 7. Circuit Current vs Temperature
Figure 8. RSTIN Power Good Low Detect Voltage
vs Temperature
Figure 9. RSTIN Power Good High Detect Voltage
vs Temperature
(“RSTIN UVD”, VDD = 3.3 V)
(“RSTIN OVD”, VDD = 3.3 V)
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BD39042MUF-C
Typical Performance Curves - continued
Figure 10. DIN1 Power Good Low Detect Voltage
vs Temperature
Figure 11. DIN1 Power Good High Detect Voltage
vs Temperature
(“DIN1 UVD”, VDD = 3.3 V)
(“DIN1 OVD”, VDD = 3.3 V)
Figure 12. DIN2 Power Good Low Detect Voltage
vs Temperature
Figure 13. DIN2 Power Good High Detect Voltage
vs Temperature
(“DIN2 UVD”, VDD = 3.3 V)
(“DIN2 OVD”, VDD = 3.3 V)
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BD39042MUF-C
Typical Performance Curves - continued
Figure 14. DIN3 Power Good Low Detect Voltage
vs Temperature
Figure 15. DIN3 Power Good High Detect Voltage
vs Temperature
(“DIN3 UVD”, VDD = 3.3 V)
(“DIN3 OVD”, VDD = 3.3 V)
Figure 16. DIN4 Power Good Low Detect Voltage
vs Temperature
Figure 17. DIN4 Power Good High Detect Voltage
vs Temperature
(“DIN4 UVD”, VDD = 3.3 V)
(“DIN4 OVD”, VDD = 3.3 V)
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BD39042MUF-C
Typical Performance Curves - continued
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
WDIN Input Voltage [V]
Figure 18. VDD Power On Reset Threshold Voltage
vs Temperature
Figure 19. WDIN Input Current vs WDIN Input Voltage
(“WDIN Pull-down Resistor Value”, VDD = 3.3 V)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
WDEN Input Voltage [V]
Figure 20. WDEN Input Current vs WDEN Input Voltage
(“WDEN Pull-down Resistor Value”, VDD = 3.3 V)
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BD39042MUF-C
Timing Chart
Figure 21 shows ON/OFF normal sequence.
When UVLO (2.55 V) monitoring the VDD pin is released, internal OSC for DIGITAL BLOCK starts to work. Then after RSTIN
voltage reaches UVD release (adjustable), BIST starts to do self-test. If the BIST is normal, XRSTOUT goes to High at 10 ms
after RSTIN UVD released. If the BIST is abnormal, XRSTOUT, PG1 to PG4 and WDOUT stays at Low.
XRSTOUT goes to Low when either of 2 monitoring functions (RSTIN UVD or Watchdog Timer) is detected.
WDT block has initial mask time (Typ 500 ms). Even though High voltage is given to WDEN within this time from RSTIN UVD
released, WDT is not enabled. For example, as Figure 22 shows, in WDEN tied to VDD case WDT is enabled 500 ms after
RSTIN UVD released.
WDEN input signal works as an enable of Watchdog Timer. Even though clocks are input to the WDIN pin, they are ignored
as long as WDEN = Low. WDOUT is just a buffered version output of WDEN input and processor can use this output to
confirm if WDEN is correctly controlled by itself.
UVLO
Detect
UVLO
Release
VDD
RSTIN UVD
Release
RSTIN UVD
Detect
RSTIN
DIGITAL_OSC
(internal)
BIST time
(internal)
tBIST
BIST is normal
tXRSTOUT
XRSTOUT
BIST is abnormal
UVD1, UVD2,
UVD1, UVD2,
UVD3, UVD4
Release
UVD3, UVD4 Release
tPG1, tPG2,
tPG3, tPG4
tPG1,tPG2,
tPG3,tPG4
BIST is abnormal
WDIN
WDT start
WDEN
Disabled
Enabled
Disabled
WDT function
(internal)
WDOUT
BIST is abnormal
Figure 21. Power ON/OFF Normal Sequence (WDEN is controlled by external signal)
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BD39042MUF-C
Timing Chart - continued
UVLO
Release
UVLO
Detect
VDD
RSTIN UVD
Release
RSTIN UVD
Detect
RSTIN
DIGITAL_OSC
(internal)
BIST time
(internal)
tBIST
BIST is normal
tXRSTOUT
XRSTOUT
BIST is abnormal
UVD1, UVD2,
UVD3, UVD4
Release
UVD1, UVD2,
UVD3, UVD4 Release
DIN1, DIN2,
DIN3, DIN4
tPG1, tPG2,
tPG3, tPG4
tPG1, tPG2,
tPG3, tPG4
PG1, PG2,
PG3, PG4
BIST is abnormal
WDIN
tWDIM (500 ms)
WDT start
WDEN
Disabled
Enabled
Disabled
WDT function(internal)
WDOUT
BIST is abnormal
Figure 22. Power ON/OFF Sequence (WDEN is externally pulled-up to VDD)
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BD39042MUF-C
Timing Chart - continued
Figure 23 shows monitoring sequence with VDD POR, DIN1, DIN2, DIN3 and DIN4 voltage detection and WDT monitoring.
XRSTOUT is qualified by either of RSTIN (VDD POR) and WDIN (WDT) and outputs Low level voltage when these are
detected.
When WDEN becomes Low, WDOUT goes to Low and WDT stops to work immediately.
PG1, PG2, PG3 and PG4 are de-asserted immediately de-bounce time by internal DIGITAL de-bounce filter when the
corresponding DIN1, DIN2, DIN3 and DIN4 input voltage goes out of PG window (±6 %). PG1, PG2, PG3 and PG4 are
asserted at 10 ms after DIN1, DIN2, DIN3 and DIN4 input voltage becomes inside PG window.
VDD
RSTIN OVD
Detect
+6 %
RSTIN OVD
Release
RSTIN
-6 %
RSTIN UVD
Release
RSTIN UVD
Detect
XRSTOUT
tXRSTOUT
tXRSTOUT
tXRSTOUT
tXRSTOUT
SLOW
Timeout
FAST
Timeout
SLOW
Timeout
FAST
Timeout
WDIN
WDT OFF
WDEN
tWDIM
tWDIM
tWDIM
tWDIM
WDOUT
WDT Monitoring time
WDT Unmonitored time
DIN1 UVD, DIN2 UVD,
DIN3 UVD, DIN4 UVD Detect
DIN1, DIN2,
DIN3, DIN4
+6%
DIN1 OVD, DIN2 OVD,
DIN3 OVD, DIN4 OVD Detect
-6 %
DIN1 UVD, DIN2 UVD,
DIN1 OVD, DIN2 OVD,
DIN3 UVD, DIN4 UVD Release
DIN3 OVD, DIN4 OVD Release
tPG1, tPG2,
tPG3, tPG4
tPG1, tPG2,
tPG3, tPG4
PG1, PG2,
PG3, PG4
Figure 23. Monitoring Sequence 1
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BD39042MUF-C
Timing Chart - continued
VDD
RSTIN OVD
+6 %
RSTIN OVD
Release
Detect
RSTIN
-6 %
RSTIN UVD
Release
RSTIN UVD
Detect
XRSTOUT
WDIN
tXRSTOUT
tXRSTOUT
WDEN
tWDIM
WDOUT
DIN1, DIN2,
DIN3, DIN4 = Normal
PG1, PG2,
PG3, PG4 = High
Figure 24. Monitoring Sequence 2 (2nd reset factor appears and disappears within tXRSTOUT
)
VDD
RSTIN OVD
RSTIN OVD
Release
+6 %
Detect
RSTIN
-6 %
RSTIN UVD
Detect
RSTIN UVD
Release
XRSTOUT
WDIN
tXRSTOUT
tXRSTOUT
WDEN
tWDIM
WDOUT
DIN1, DIN2,
DIN3, DIN4 = Normal
PG1, PG2,
PG3, PG4 = High
Figure 25. Monitoring Sequence 3 (2nd reset factor appears within tXRSTOUT and disappear after tXRSTOUT
)
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BD39042MUF-C
Application Example
VIN3
R9B2
VIN4
R11B
R11A
R9A
R12
R10
R9B1
10
12
11
9
PG4
DIN4
PG3
DIN3
PG2
R8
VIN2
13
14
15
16
8
7
6
5
WDEN
R7B
R7A
DIN2
PG1
WDIN
EXP-PAD
R15
R6
XRSTOUT
VIN1
R5B
WDOUT
DIN1
R5A
VDD
RSTIN
GND
RTW
1
2
3
4
U1
RRTW
C1
R2B
R2A
Figure 26. Typical Application Schematic
Example of Constant Setting
VDD = 3.3 V, RRTW = 27 kΩ, VIN1 = 3.3 V, VIN2 = 1.8 V, VIN3 = 1.5 V, VIN4 = 1.2 V
Recommended Parts
Range
Max
-
1.0
50
50
47
50
50
50
50
50
50
50
50
50
50
Item Value Unit
Parts Number
BD39042MUF-C
Company
ROHM
MURATA
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
Min
-
0.1
-
-
10
-
-
-
-
-
-
-
-
-
-
-
-
Unit
-
U1
-
-
C1
0.22
2.4
7.5
27
2.4
7.5
10
2.4
3.0
10
5.6
3.6
1.3
10
μF
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
GCM188R71C224KA01
MCR01MZPD2401
MCR01MZPD7501
MCR01MZPD2702
MCR01MZPD2401
MCR01MZPD7501
MCR01MZPD1002
MCR01MZPD2401
MCR01MZPD3001
MCR01MZPD1002
MCR01MZPD5601
MCR01MZPD3601
MCR01MZPD1301
MCR01MZPD1002
MCR01MZPD1801
MCR01MZPD3601
MCR01MZPD1002
MCR01MZPD1002
μF
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
R2A
R2B
RRTW
R5A
R5B
R6
R7A
R7B
R8
R9A
R9B1
R9B2
R10
R11A
R11B
R12
R15
1.8
3.6
10
50
50
50
50
-
-
10
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BD39042MUF-C
Application Example - continued
Procedure for Selecting Application Components
(1) Selecting input capacitor (C1)
Place a ceramic capacitor connect to GND nearest the IC for the VDD pin.
Please consider temperature change, DC bias characteristics and dispersion enough. Also it is necessary to choose the
product superior (over 0.1 µF at least) in thermal characteristics such as B characteristics or X7R characteristics.
The capacitor 1.5 times to 2 times larger than a limit is recommended about the pressure-resistant.
(2) Selecting a resistor of input pin (R2A, R2B, R5A, R5B, R7A, R7B, R9A, R9B1, R9B2, R11A, R11B
Set a resistor divider voltage 0.8 V to input voltage VDD, VIN1, VIN2, VIN3, VIN4.
It is recommended to set the total input impedance to be within 10 kΩ.
)
Because the detection voltage changes when noise is applied to the input pin.
푅2퐴
푅푆푇퐼푁 = 0.8 푉 = 푉퐷퐷
×
푅2퐴 + 푅2퐵
푅5퐴
ꢀ퐼푁1 = 0.8 푉 = 푉퐼푁1 ×
ꢀ퐼푁ꢁ = 0.8 푉 = 푉퐼푁ꢁ ×
푅5퐴 + 푅5퐵
푅7퐴
푅7퐴 + 푅7퐵
푅9퐴
ꢀ퐼푁3 = 0.8 푉 = 푉퐼푁3 ×
푅9퐴 + 푅9퐵ꢂ + 푅9퐵2
푅ꢂꢂ퐴
푅ꢂꢂ퐴 + 푅ꢂꢂ퐵
ꢀ퐼푁4 = 0.8 푉 = 푉퐼푁4 ×
(3) Selecting a resistor of output pin (R6, R8, R10, R12, R15)
Set more than 10 kΩ pull-up resistor connects to the VDD pin.
Please consider thermal characteristics and dispersion enough, and it is necessary to choose a resistor over 7.5 kΩ.
The PG1 to PG4 pins can be connected and used to OR output. In this case also, choose total impedance over 7.5 kΩ.
MCU
PG1
PG2
PG3
PG4
Figure 27. PG1, PG2, PG3, PG4 OR Output
(4) Selecting WDT (RRTW
)
Place a resistor nearest GND for the RTW pin.
Change RTW resistor value enables WDT setting time change. Settable range is 10 kΩ to 47 kΩ.
Please consider thermal characteristics and dispersion enough, and it is necessary to choose component under ±1.0 %.
Refer to Figure 5 for the setting time.
(5) EXP-PAD
The exposed thermal pad is highly recommended for GND connection.
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BD39042MUF-C
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
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BD39042MUF-C
Operational Notes - continued
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10.Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 28. Example of Monolithic IC Structure
11.Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12.Functional Safety
“ISO 26262 Process Compliant to Support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in
the datasheet.
“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional Safety Supportive Automotive Products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
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TSZ22111 • 15 • 001
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15.May.2021 Rev.001
23/26
BD39042MUF-C
Ordering Information
B D 3
9
0
4
2 M U F
-
CE2
Part Number
Package
MUF: VQFN16FV3030
Packaging and forming specification
C: for Automotive
E2: Embossed tape and reel
Marking Diagram
VQFN16FV3030 (TOP VIEW)
Part Number Marking
D 3 9
0 4 2
LOT Number
Pin 1 Mark
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15.May.2021 Rev.001
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BD39042MUF-C
Physical Dimension and Packing Information
Package Name
VQFN16FV3030
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15.May.2021 Rev.001
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BD39042MUF-C
Revision History
Date
Revision
Rev.001
Changes
15.May.2021
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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