BD3512MUV-E2 [ROHM]
Fixed Positive LDO Regulator, CMOS, 4 X 4 MM, VQFN-20;
| 型号： | BD3512MUV-E2 |
| 厂家： | 
ROHM |
| 描述： | Fixed Positive LDO Regulator, CMOS, 4 X 4 MM, VQFN-20 输出元件 调节器 |
| 文件： | 总19页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC Chipsets
with Power Good
BD3512MUV (3A)
● Description
The BD3512MUV ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal
performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to
minimize the input-to-output voltage differential to the ON resistance (RON=100mΩ) level. By lowering the dropout voltage in
this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the
switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3512MUV is designed to enable
significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage
configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up,
which can be programmed to whatever power supply sequence is required.
● Features
1) Internal high-precision reference voltage circuit (0.65V±1%)
2) Built-in VCC undervoltage lockout circuit (VCC=3.80V)
3) NRCS (soft start) function reduces the magnitude of in-rush current
4) Internal Nch MOSFET driver offers low ON resistance (65mΩ typ)
5) Built-in current limit circuit (3.0A min)
6) Built-in thermal shutdown (TSD) circuit (Timer latch)
7) Variable output (0.65～2.7V)
8) High-power package VQFN020V4040 : 4.0×4.0×1.0(mm)
9) Tracking function
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
Oct. 2008
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
VCC
VIN
Limit
6.0 *1
6.0 *1
6.0 *1
1
Unit
V
Input Voltage 1
Input Voltage 2
V
Input Voltage 3
VCC
VD
V
Input Voltage 4
V
Maximum Output Current
Enable Input Voltage
PGOOD Input Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
IO
3 *1
A
Ven
6.0
V
VPGOOD
Pd1
6.0
V
0.34 *2
0.70 *3
1.21 *4
3.56 *5
-10～+100
-55～+125
+150
W
W
W
W
℃
℃
℃
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
*1 Should not exceed Pd.
*2 Reduced by 2.7mW/℃ for each increase in Ta≧25℃(no heat sink)
*3 Reduced by 5.6mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:No substrate surface copper foil area.
*4 Reduced by 9.7mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:4 layers, substrate surface copper foil area 10.29mm2.
*5 Reduced by 28.5mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:4 layers, substrate surface copper foil area 5505mm2.
●Operating Voltage (Ta=25℃)
Parameter
Input Voltage 1
Symbol
VCC
VIN
Min.
4.3
Max.
5.5
VCC-1 *6
Unit
V
Input Voltage 2
0.7
V
Input Voltage 3
VCC
Vo
4.5
5.5
V
Output Voltage Setting Range
Enable Input Voltage
VFB
-0.3
2.7
V
Ven
5.5
V
*6 VCC and VIN do not have to be implemented in the order listed.
★This product is not designed for use in radioactive environments.
2/16
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, Vcc=5V, Ven=3V, VIN=1.7V, R1=3.9KΩ, R2=3.3KΩ)
Limit
Parameter
Bias Current
Symbol
Unit
Condition
Min.
Typ.
1.4
0
Max.
2.2
10
Icc
IST
Io
-
-
mA
uA
A
VCC Shutdown Mode Current
Maximum Output Current
Output Voltage Temperature
Coefficient
Ven=0V
3.0
-
-
Tcvo
VFB1
VFB2
-
0.01
0.650
0.650
-
%/℃
V
Feedback Voltage 1
0.643
0.637
0.657
0.663
Io=0 to 3A
Feedback Voltage 2
V
Tj=-10 to 100℃
Line Regulation 1
Line Regulation 2
Load Regulation
Reg.l1
Reg.l2
Reg.L
-
-
-
0.1
0.1
0.5
0.5
0.5
10
%/V Vcc=4.3V to 5.5V
%/V VIN=1.5V to 3.3V
mV
mV
mA
Io=0 to 3A
Io=1A,VIN=1.2V
Minimum dropout voltage
dVo
-
65
-
100
-
Standby Discharge Current
[ENABLE]
Iden
1
Ven=0V, Vo=1V
Enable Pin
Enhi
2
-
-
V
Input Voltage High
Enable Pin
Enlow
Ien
-0.2
-
-
0.8
10
V
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
6
uA
Ven=3V
Feedback Pin Bias Current
[NRCS]
IFB
-100
0
100
nA
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
Inrcs
14
-
20
0
26
50
uA
Vnrcs=0.5V
Ven=0V
VSTB
mV
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
VccUVLO
Vcchys
3.5
3.8
4.1
V
mV
V
Vcc:Sweep-up
Vcc:Sweep-down
VD:Sweep-up
100
160
220
VREF×
VREF×
VREF×
VDUVLO
0.6
0.7
0.8
SCP Startup Voltage
SCP Threshold Voltage
SCP Charge Current
SCP Standby Voltage
[PGOOD]
VOSCP
VSCPTH
ISCP
Vo×0.3 Vo×0.4 Vo×0.5
V
V
1.05
1.4
-
1.15
1.25
2.6
50
2
-
μA
mV
VSCPSTBY
Low-side Threshold Voltage
High-side Threshold Voltage
PGDLY Charge Current
Ron
VTHPGL Vo×0.87 Vo×0.9 Vo×0.93
VTHPGH Vo×1.07 Vo×1.1 Vo×1.13
V
V
Ipgdly
RPG
1.4
-
2.0
0.1
2.6
-
μA ※
kΩ
※PGOOD delay time is determined as in formula below.
C(pF)×1.23
tpgdly=
(μsec)
Ipgdly (μA)
3/16
●Reference Data
Vo
Vo
50mV/div
Vo
50mV/div
50mV/div
Io
Io
Io
1A/div
3.0A
1A/div
3.0A
3.0A
1A/div
Io=0A→3A/3μsec
Io=0A→3A/3μsec
T(4μsec/div)
T(10μsec/div)
Io=0A→3A/3μsec
T(4μsec/div)
Fig.2 Transient Response
(0→3A)
Fig.3 Transient Response
(0→3A)
Fig.1 Transient Response
(0→3A)
Co=100μF
Co=100μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
Vo
Vo
Vo
50mV/div
50mV/div
50mV/div
Io
Io
Io
3.0A
3.0A
3.0A
1A/div
1A/div
1A/div
Io=3A→0A/3μsec
T(100μsec/div)
Io=3A→0A/3μsec
Io=3A→0A/3μsec
T(100μsec/div)
T(40μsec/div)
Fig.6 Transient Response
(3→0A)
Fig.4 Transient Response
(3→0A)
Fig.5 Transient Response
(3→0A)
Co=100μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
Co=100μF
Ven
VCC
5V/div
Ven
2V/div
2V/div
Ven
VNRCS
1V/div
VNRCS
1V/div
2V/div
VIN
2V/div
Vo
Vo
500mV/div
500mV/div
Vo
1V/div
T(2msec/div)
T(100μsec/div)
VCC→VIN→Ven
Fig.9 Input sequence
Fig.7 Waveform at output start
Fig.8 Waveform at output OFF
VCC
VCC
VCC
5V/div
5V/div
5V/div
Ven
Ven
Ven
2V/div
2V/div
2V/div
VIN
VIN
VIN
2V/div
2V/div
2V/div
Vo
Vo
Vo
1V/div
1V/div
1V/div
Ven→VCC→VIN
VCC→Ven→VIN
VIN→VCC→Ven
Fig.10 Input sequence
Fig.11 Input sequence
Fig.12 Input sequence
4/16
●Reference Data
1.23
1.22
1.21
1.20
1.19
1.18
1.17
VCC
Ven
VCC
Ven
VIN
Vo
VIN
Vo
-50
-25
0
25
50
75
100
125
150
VIN→Ven→VCC
Ven→VIN→VCC
Tj [℃]
Fig.13 Input sequence
Fig.14 Input sequence
Fig.15 Tj-Vo
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
50
45
40
35
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125 150
-50
-25
0
25
50
75
100
125
150
Tj [℃]
℃
Tj [ ]
Tj [℃]
Fig.18 Tj-IINSTB
Fig.17 Tj-ISTB
Fig.16 Tj-ICC
24
22
20
18
16
14
12
10
9
8
7
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100
125 150
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tj [℃]
Tj [℃]
Tj [℃]
Fig.21 Tj-RON
(VCC=5V/VO=1.2V)
Fig.20 Tj-IEN
Fig.19 Tj-INRCS
80
70
60
50
40
30
20
10
0
50
45
40
35
Vo=2.5V
Vo=1.8V
Vo=1.7V
Vo=1.5V
Vo=1.2V
3
5
7
-50
-25
0
25
50
75
100
125
150
Vcc [V]
℃
Tj [
]
Fig.23 VCC-RON
5/16
Fig.22 Tj-RON
(VCC=5V/VO=1.5V)
●Block Diagram
VCC
C1
VCC
VD
8
6
VIN
UVLO2
VIN
9
UVLOLATCH
VCC
VCC
10
11
12
13
EN
UVLO1
VREF
×0.7
VIN
EN
Reference
Block
Current
Limit
CL
7
UVLO1
R2
R1
C2
VCC
VREF
NRCS
LATCH
VO
14
15
16
17
18
CL
UVLO1
UVLO2
TSD
SCP/TSD
LATCH
VO
NRCS×0.3
VREF×0.4
SCP
FB
EN
UVLO1
R2
CFB
EN
TSD
C3
SCP
CSCP
2
19
FB
R1
POWER
GOOD
NRCS
CNRCS
20
NRCS
EN/UVLO
5
3
1
4
VCC
PGDLY
PG
GND
●Pin Layout
●Pin Function Table
PIN No.
1
PIN name
PIN Function
GND1
Ground Pin 1
Vo2 Vo1 VIN5
VIN4
VIN3
11
SCP Delay Time Setting Capacitor
Connection Pin
2
3
SCP
15
14
13
12
PGOOD Delay Setting
Capacitor Connection Pin
Power Good Pin
PGDLY
16
17
18
19
20
10
Vo3
Vo4
Vo5
FB
VIN2
4
5
PG
VCC
VCC
EN
Power Supply Pin
9
8
7
6
VIN1
6
Power Supply Pin
FIN
7
Enable Input Pin
VD
8
VD
VIN Input Voltage Detect Pin
Input Voltage Pin 1
9
VIN1
VIN2
VIN3
VIN4
VIN5
Vo1
Vo2
Vo3
Vo4
Vo5
FB
EN
10
11
12
13
14
15
16
17
18
19
Input Voltage Pin 2
Input Voltage Pin 3
NRCS
VCC
Input Voltage Pin 4
Input Voltage Pin 5
1
2
3
4
5
Output Voltage Pin 1
Output Voltage Pin 2
Output Voltage Pin 3
Output Voltage Pin 4
Output Voltage Pin 5
Reference Voltage Feedback Pin
In-rush Current Protection (NRCS)
Capacitor Connection Pin
Connected to heatsink and GND
PGDLY
GND1 SCP
PG VCC
20
NRCS
FIN
bottom
* Please short N.C to the GND line.
6/16
●Operation of Each Block
・AMP
This is an error amp compares the reference voltage (0.65V) with VO to drive the output Nch FET (Ron=50mΩ). Frequency
optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input
voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active,
output goes LOW and the output of the NchFET switches OFF.
・EN
The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin VO, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is independent
of the input sequence.
・UVLO
To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and VO. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.
・CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored to the parameter value.
・NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20μ
A (TYP) constant current source to charge the external capacitor. Capacitors with low susceptibility (0.001μF～1μF) to
temperature are recommended, in order to assure a stable soft-start time.
・TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
・VIN
The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the VCC pin and the ESD protection diode) is necessary, VIN operates independent of the input
sequence. However, since an output NchFET body diode exists between VIN and VO, a VIN-VO electric (diode) connection is
present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from VO.
・PGOOD
It outputs the status of the output voltage. This is open drain pin and connects to VCC pin through the pull-up resistance
(100kΩ or so). When the output voltage range is VO×0.9 to VO×1.1(TYP), the status is high.
7/16
●Timing Chart
EN ON/OFF
VIN
VCC
EN
0.65V(typ)
NRCS
Vo
Startup
Vo×0.9V(typ)
60μs(typ)
(typ@ C=100pF)
t
PGOOD
VCC ON/OFF
VIN
VCC
EN
UVLO
Hysteresis
0.65V(typ)
NRCS
Startup
Vo×0.9V(typ)
Vo
60μs (typ@100pF)
t
PGOOD
8/16
VIN ON/OFF
VIN
VD=VREF×0.7(typ)
UVLO (latch)
(detect in VD)
VD
VCC
EN
0.65V(typ)
NRCS
Vo×0.9V
Vo
60μs(typ@ C=100pF)
PGOOD
9/16
●Evaluation Board
■ BD3512MUV Evaluation Board Schematic
C9
C10
C11 C12
VO
1
VIN
RLD
U2
C15 C16
INF
RF1
1
R14
C14
U1
RF2
16
VIN2
VO3
VO4
VO5
FB
10
9
VCC
JPF2
JP9
INV
VO_S
VIN1
VD
17
18
1
EN
JPF1
R9
R8
JP18
VINS
1
VCC
H
VD
U3
8
C18
1
R7
R18
19
EN
FB
7
SW1
L
C7
R19
20
1
VCC
VCC
NRCS
6
RF2
NRCS
CF
C6
C20
C3
1
VDD
C2
C5
SGND
PGDLY
GND1 GND2
1
PG
JP4B
SCP
VPG
R4
1
VCC
JP4
■ BD3512MUV Evaluation Board Standard Component List
Component Rating
Manufacturer Product Name
Component Rating
Manufacturer Product Name
U1
C2
C3
R4
C5
C6
R7
-
ROHM
BD3512MUV
R8
3.9kΩ ROHM
3.3kΩ ROHM
MCR03EZPF3901
100pF MURATA
100pF MURATA
100kΩ ROHM
CRM1882C1H101JA01
CRM1882C1H101JA01
MCR03EZPF1003
CM05104K10A
R9
MCR03EZPF3301
CM21B106M06A
C9
10uF
22uF
KYOCERA
KYOCERA
C16
R18
R19
V20
CM316B226M06A
MCR03EZPF3301
MCR03EZPF3901
GRM188B11H102KA01
0.1uF
1uF
KYOCERA
KYOCERA
-
3.3kΩ ROHM
3.9kΩ ROHM
0.01uF MURATA
CM105B105K06A
jumper
0Ω
■ BD3512MUV Evaluation Board Layout
Silk Screen (Bottom)
Middle Layer_2
10/16
Silk Screen (Top)
TOP Layer
Middle Layer_1
Bottom Layer
●Recommended Circuit Example
Vo (1.2V/3A)
VIN
C9
C16
15
14
13
12
11
16
17
18
19
20
10
9
CFB
R18
R19
R9
R8
8
7
VEN
6
C20
VCC
C6
1
2
3
4
5
C2
C3
R4
C5
VCC
VPGOOD
Recommended
Component
Value
Programming Notes and Precautions
R18/R19
3.3k/3.9k
IC output voltage can be set with a configuration formula VFB×(R18+R19)/R19 using the
values for the internal reference output voltage (VFB) and the output voltage resistors (R18,
R19). Select resistance values that will avoid the impact of the FB bias current (±100nA).
The recommended total resistance value is 10KΩ.
R4
100k
This is the pull-up resistance for open drain pin. It is recommended to set the value about
100kΩ.
C16
22μF
To assure output voltage stability, please be certain the Vo1～Vo5 pins and the GND pins
are connected. Output capacitors play a role in loop gain phase compensation and in
mitigating output fluctuation during rapid changes in load level. Insufficient capacitance
may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate
output voltage fluctuation under rapid load change conditions. While a 22μF ceramic
capacitor is recomended, actual stability is highly dependent on temperature and load
conditions. Also, note that connecting different types of capacitors in series may result in
insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC) input pins. If the impedance of this power supply were to increase, input voltage
(VCC) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 1μF / 0.1μF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
C6/C5
1μF/0.1μF
C9
10μF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VIN) input pins. If the impedance of this power supply were to increase, input voltage
(VIN) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 10 μF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
C20
0.01μF
The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
CFB
1000pF
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
11/16
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100 ℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
＜Reference values＞
IC only
θj-a:VQFN020V4040 249.5℃/W
1-layer substrate (copper foil area : 0mm2)
4-layer substrate (copper foil area : 10.29mm2)
4-layer substrate (copper foil area : 5505mm2)
160.1℃/W
82.6℃/W
31.2℃/W
Substrate size: 74.2×74.2×1.6mm3 (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable
to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the
number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3512MUV is generated from the output Nch FET. Power loss is determined by the
total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3512MUV) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (Vo≒VREF) ×Io(Ave)
Example) Where VIN=1.5V, VO=1.25V, Io(Ave) = 4A,
Power consumption (W)
=
1.5(V)-1.2(V) ×4.0(A)
= 1.0(W)
12/16
●Input-Output Equivalent Circuit Diagram
VCC
VCC
VCC
1kΩ
1kΩ
NRCS
1kΩ
1kΩ
VIN1
VIN2
VIN3
VIN4
GATE
1kΩ
10kΩ
10kΩ
1kΩ
VIN5
VCC
VCC
EN
1kΩ
1kΩ
FB
Vo1
350kΩ
1kΩ
100kΩ
100kΩ
Vo2
50kΩ
10kΩ
Vo3
Vo4
Vo5
20pF
13/16
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,
not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation.
Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD on temperature [°C] (typ.)
175
Hysteresis temperature [°C] (typ.)
15
BD3512MUV
10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
14/16
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
B
Pin A
Pin B
Pin B
C
E
Pin A
B
C
E
N
N
N
P+
P+
P+
P+
N
P
P
Parasitic
element
N
N
Parasitic
element
P substrate
P substrate
GND
GND
GND
GND
Parasitic element
Parasitic element
Other adjacent elements
Example of IC structure
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
●Heat Dissipation Characteristics
◎VQFN020V4040
①
②
4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1℃/W
4.0
4 layers (Copper foil area : 10.29m2)
copper foil in each layers.
θj-a=103.3℃/W
①3.56W
③
④
no copper foil area
θj-a=178.6℃/W
IC only.
3.0
θj-a=367.6℃/W
2.0
②1.21W
1.0
0
③0.70W
④0.34W
0
25
50
75 100105 125
150
Ambient temperature:Ta [℃]
15/16
●Type Designations (Ordering Information)
―
B
D
3
5
1
2
M
U
E
2
V
Package Type
Product Name
E2 Emboss tape reel opposite draw-out side: 1 pin
・BD3512
・MUV : VQFN020V4040
VQFN020V4040
<Dimension>
4.0 0.1
<Tape and Reel information>
Tape
Embossed carrier tape (with dry pack)
2500pcs
E2
Quantity
Direction
of feed
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
S
0.08 S
2.1 0.1
C0.2
1
5
20
6
16
10
15
11
Direction of feed
1.0
1pin
Reel
+0.05
-0.04
0.25
(Unit:mm)
0.5
※When you order , please order in times the amount of package quantity.
Catalog No.08T429A '08.10 ROHM ©
Daattaasshheeeett
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
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Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
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(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
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[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
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H2S, NH3, SO2, and NO2
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[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
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Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
Rev.002
© 2014 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
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2. You agree that application notes, reference designs, and associated data and information contained in this document
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Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
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1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
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3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
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Other Precaution
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Notice - GE
Rev.002
© 2014 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
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2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
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Notice – WE
Rev.001
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