BA7630F [ROHM]

Video switch for CANAL-Plus decoder; 视频开关CANAL加解码器
BA7630F
型号: BA7630F
厂家: ROHM    ROHM
描述:

Video switch for CANAL-Plus decoder
视频开关CANAL加解码器

解码器 开关 消费电路 商用集成电路 光电二极管
文件: 总12页 (文件大小:171K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Multimedia ICs  
Video switch for CANAL-Plus decoder  
BA7630S / BA7630F  
The BA7630S and BA7630F are decoder switching ICs for the scrambled broadcasts in France. The ICs include a 3-  
input multiplexer, 2-input multiplexers with 6dB amplifiers, and a 9-bit serial-to-parallel converter.  
These ICs greatly simplify decoder switching, and can be connected to a control microprocessor using just two lines.  
Applications  
Video cassette recorders  
Features  
1) All the switching functions required for SECAM  
CANAL plus decoder integrated onto one chip.  
2) Built-in 9-bit serial-to-parallel converter for decoder  
and TV control reduces number of microprocessor  
wiring connections required.  
3) Inputs have a sync-tip clamp.  
4) The switch section can be used independently.  
5) Low power consumption off a 5V supply.  
Absolute maximum ratings (Ta = 25°C)  
Parameter  
Symbol  
VCC  
Limits  
Unit  
1
Power supply voltage  
9
V
2
BA7630S  
BA7630F  
500  
Power dissipation  
Pd  
mW  
3
600  
Topr  
Tstg  
– 25 ~ + 70  
°C  
°C  
Operating temperature  
Storage temperature  
1 13V for switches 1 to 9.  
– 55 ~ + 125  
2 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.  
3 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C.  
Recommended operating conditions (Ta = 25°C)  
Parameter  
Symbol  
VCC  
Min.  
4.5  
Typ.  
5.0  
Max.  
5.5  
Unit  
Power supply voltage  
V
1
Multimedia ICs  
BA7630S / BA7630F  
Block diagram  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
BA7630S  
BUFF  
BUFF  
SW4  
CONTROL  
LOGIC  
LATCHES  
6dB  
AMP  
SW  
3
SW12  
SW12  
SHIFT  
REGISTER  
SW  
SW  
2
1
LOGIC  
6dB  
AMP  
SW4  
SW1  
SW2  
SW3  
1
2
3
4
5
6
7
8
9
10  
11  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
BA7630F  
BUFF  
BUFF  
SW4  
CONTROL  
LOGIC  
LATCHES  
6dB  
AMP  
SW3  
SW12  
SW12  
SHIFT  
REGISTER  
SW  
SW  
2
1
LOGIC  
6dB  
AMP  
SW4  
SW  
1
SW2  
SW3  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Pin descriptions  
Pin No.  
Pin name  
Pin No.  
Pin name  
1
2
3
4
5
6
7
8
9
IN 4  
12 (15) OUT 2  
13 (16) GND  
CC  
V
IN 1  
14 (17) SW 4 IN / OUT  
15 (20) SW 5 OUT  
16 (21) SW 6 OUT  
17 (22) SW 7 OUT  
18 (23) SW 8 OUT  
19 (24) CLOCK IN  
20 (26) DATA IN  
21 (27) SW 9 OUT  
22 (28) OUT 1  
(5)  
(6)  
(7)  
(8)  
(9)  
RESET IN  
IN 2  
GND  
IN 3  
SW 1 IN / OUT  
(10) SW 2 IN / OUT  
10 (13) SW 3 IN / OUT  
11 (14) OUT 3  
Pin numbers in parentheses are for the BA7630F.  
2
Multimedia ICs  
BA7630S / BA7630F  
Electrical characteristics (unless otherwise noted Ta = 25°C and VCC = 5.0V)  
Measurement  
Parameter  
Symbol  
ICC  
Min.  
Typ.  
28  
Max.  
40  
Unit  
mA  
Conditions  
Circuit  
Supply current  
Analog  
Fig.1  
Maximum output level  
Voltage gain 1  
2.5  
– 0.5  
5.5  
2.8  
0
f = 1kHz, THD = 0.5%  
f = 1MHz, VIN = 1.0VP-P  
f = 1MHz, VIN = 1.0VP-P  
Vom  
GV1  
GV2  
VP-P  
dB  
0.5  
6.5  
Voltage gain 2  
6.0  
dB  
10MHz / 1MHz  
VIN = 1.0VP-P  
Fig.1  
Frequency characteristic  
Interchannel crosstalk  
– 4.0 – 1.5 + 1.0  
dB  
Gf  
f = 4.43MHz  
VIN = 1.0P-P  
– 60  
2.0  
– 45  
3.0  
dB  
V
CTM  
SW1 ~ SW4 switch level  
Digital  
VTH1 ~ 4  
1.0  
"H" input voltage  
3.0  
2
1.0  
10  
V
V
VIH  
VIL  
Fig.3  
Fig.2  
"L" input voltage  
"H" input current  
µA  
µA  
µA  
µA  
V
IIH  
"L" input current  
IIL  
– 80 – 100 – 150  
"H" output leakage current 1  
"H" output leakage current 2  
"L" output voltage  
Maximum clock frequency  
Setup time  
150  
230  
0
350  
50  
VCC = 12V  
VCC = 12V  
ICC = 2mA  
IQH1 ~ 4  
IQH5 ~ 9  
VQL  
fMax.  
tsu  
0.1  
500  
0.1  
0.5  
250  
kHz  
µs  
Fig.1  
1.0  
3
Multimedia ICs  
BA7630S / BA7630F  
Measurement circuits  
BA7630S  
Distortion  
meter  
Distortion  
meter  
V
~
V
~
1
1
2
2
SW  
K
SWJ  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
BUFF  
SW  
4
BUFF  
CONTROL  
LOGIC  
LATCHES  
6dB  
AMP  
SW12  
SW  
3
SW12  
SHIFT  
REGISTER  
SW  
SW  
2
1
LOGIC  
6dB  
AMP  
SW  
4
SW  
1
SW  
2
SW  
3
V
CC5.0V  
1
2
3
4
5
6
7
8
9
10  
11  
A
47µ  
1µ  
1µ  
1µ  
1µ  
+
+
+
+
SW  
1
B
SWC  
SW  
D
SW  
E
SW  
F
SW  
1
G
SW  
1
H
SW  
1
I
SW  
1
A
2
2
2
2
2
2
1
1
1
1
2
2
2
OSC  
Distortion  
meter  
V
~
~
~
~
~
3V  
1V  
Fig.1  
4
Multimedia ICs  
BA7630S / BA7630F  
BA7630S  
Output  
Measurement Circuit  
VCC = 5.0V  
Input  
Measurement Circuit  
47µ  
1
22  
21  
BIAS  
BUFF  
+
5.0V  
2
3
Input  
SW12  
Measurement Circuit  
A1  
A
20  
SHIFT  
REGISTER  
CONTROL  
LOGIC  
SW  
1
4
5
6
19  
18  
17  
Output  
Measurement Circuit  
A2  
V
A
SW1SW2  
SW0  
Output  
Measurement Circuit  
A3  
12V  
SW12  
LOGIC  
7
8
9
16  
15  
14  
LATCHES  
SW  
1
V
Output  
V1  
Measurement Circuit  
SW2  
Output  
Measurement Circuit  
SW  
4
SW  
3
10  
11  
13  
12  
Output  
Measurement Circuit  
SW  
3
6dB  
AMP  
6dB  
AMP  
BUFF  
BUFF  
Output  
Measurement Circuit  
Output  
Measurement Circuit  
Fig.2  
5
Multimedia ICs  
BA7630S / BA7630F  
BA7630S  
VCC = 5.0V  
12V  
47µ  
22  
21  
20  
19  
18  
17  
1
BIAS  
BUFF  
PG  
C
L
+
R
L
SW  
9
2
3
SW12  
50Ω  
50Ω  
PG  
SHIFT  
REGISTER  
CONTROL  
LOGIC  
4
5
CL  
50Ω  
RL  
SW8  
C
L
L
SW1SW2  
R
L
L
PG  
SW  
7
6
6
7
C
SW12  
R
LOGIC  
SW  
16  
12V  
C
L
L
LATCHES  
CL  
R
L
L
SW  
1
RL  
SW  
5
4
15  
14  
8
9
C
SW  
1
C
L
L
R
SW  
4
SW  
2
RL  
SW  
SW  
SW  
2
3
SW  
4
C
RL  
SW  
3
13  
12  
10  
11  
SW  
3
6dB  
AMP  
6dB  
AMP  
BUFF  
BUFF  
Fig.3  
6
Multimedia ICs  
BA7630S / BA7630F  
Measurement conditions  
Measure-  
ment  
Switch setting  
Parameter  
Symbol  
ICC  
SWA  
2
SWB  
2
SWC  
2
SWD  
2
SWE  
SWF  
SWG  
SWH  
2
SWI  
SWJ  
SWK  
method  
Current  
2
2
2
×
×
×
dissipation  
Vom1-1  
Vom2-1  
Vom3-1  
2
2
2
1
2
2
2
1
2
2
2
1
1
1
2
1
2
×
×
×
×
×
×
×
×
×
×
×
×
×
2
2
2
Maximum  
output level  
Note 1  
Note 2  
Note 3  
Vom1-2  
Vom3-2  
2
2
1
2
2
2
2
1
×
×
×
×
×
×
×
×
1
1
2
×
×
×
×
×
×
×
×
1
2
×
1
2
×
×
×
2
2
×
×
1
2
×
×
2
2
2
2
×
×
×
×
×
×
×
×
1
1
1
Vom2-3  
Vom4-3  
2
1
2
2
1
2
2
2
×
×
1
2
×
×
1
2
Gv11-2  
Gv13-2  
Gv12-3  
Gv14-3  
2
2
2
1
1
2
2
2
2
2
1
2
2
1
2
2
×
×
1
×
×
2
Voltage gain 1  
Voltage gain 2  
×
×
×
2
2
×
Gv21-1  
Gv22-1  
Gv23-1  
2
2
2
1
2
2
2
1
2
2
2
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Gf1-1  
Gf2-1  
Gf3-1  
2
2
2
1
2
2
2
1
2
2
2
1
1
1
2
2
2
2
Frequency  
characteristics  
Gf1-2  
Gf3-2  
2
2
1
2
2
2
2
1
×
×
2
2
×
×
×
×
2
2
×
×
Gf2-3  
Gf4-3  
2
1
2
2
1
2
2
2
×
×
×
×
×
×
1
2
2
2
×
×
×
×
CTM1-1-2  
CTM1-1-3  
CTM2-1-1  
CTM2-1-3  
CTM3-1-1  
CTM3-1-2  
2
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
1
2
1
2
1
2
2
1
1
1
1
2
2
1
1
2
2
2
2
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
1
1
1
1
1
Note 4  
Interchannel  
crosstalk  
CTM1-2-3  
CTM3-2-1  
2
2
2
1
2
2
1
2
×
×
×
×
1
2
×
×
×
×
1
1
×
×
CTM2-3-4  
CTM4-3-2  
1
2
2
2
2
1
2
2
×
×
×
×
×
×
1
2
1
1
×
×
×
×
The measurements in the above table were made with switching voltage levels for SW1 to SW4 of "L" = 1V, and "H" = 3V.  
Note 1: Connect distortion meters to the outputs. Adjust the input level so that the output distortion is 0.5% for a f = 1kHz sine wave input.  
This output voltage is the maximum output level Vom (VP-P).  
Note 2: Input a f = 1MHz, 1VP-P sine wave. The voltage gain GV = 20 log VOUT / VIN (dB).  
Note 3: Input a f = 1MHz and 10MHz, 1VP-P sine wave. The frequency characteristic Gf = 20 log VOUT (f = 10M) / VOUT (f = 1M) (dB).  
Note 4: Input a f = 4.43MHz, 1VP-P sine wave.  
0dB amplifier SW crosstalk is CTM0, and the 6dB amplifier SW crosstalk is CTM6.  
CTM0 = 20 log VOUT / VIN (dB)  
CTM6 = 20 log VOUT / VIN + 6 (dB)  
7
Multimedia ICs  
BA7630S / BA7630F  
Circuit operation  
Digital block truth table  
INPUT  
OUTPUT  
SW ···························SW  
H····································H  
Note  
1
9
Reset Clock  
Data  
×
×
×
H
H
L
L
L
L
L
×
L
H
1-O  
9-O  
9-O  
9-O  
SW ·····················SW  
1-O  
SW ·····················SW  
1-O  
SW ·····················SW  
Data "L" sent to internal shift register  
Data "H" sent to internal shift register  
Internal shift register data unchanged  
L
SW1-O·····················SW9-O  
1-O  
9-O  
L
SW ·····················SW  
Contents of internal shift register sent to  
internal latch  
1-N  
9-N  
L
H
SW ·····················SW  
Note 1: H: high level  
Note 2: L: low level  
Note 3: ×: either H or L  
Note 4: : L to H transition  
Note 5: : H to L transition  
Note 6: SW1-O to SW9-O: SW1 to SW9 levels before establishing the input conditions shown in the table.  
Note 7: SW1-N to SW9-N  
nearest clock transition.  
Analog truth table  
(1) OUT1 switch  
SW1  
L
SW2  
L
RESET  
SELECT  
IN1  
H
H
H
H
L
H
IN2  
H
L
IN3  
H
H
IN3  
(2) OUT2 switch  
SW3  
L
RESET  
SELECT  
H
H
IN1  
IN3  
H
(3) OUT3 switch  
SW4  
L
RESET  
SELECT  
IN2  
H
H
H
IN4  
Note: When using the switches independently  
without the digital block, the RESET pin  
must be set to "H".  
8
Multimedia ICs  
BA7630S / BA7630F  
Digital circuit operation  
(1) Introduction  
The BA7630S has 9-bit serial-to-parallel converter and  
latch circuit that has been included to expand the num-  
ber of microprocessor output ports. The breakdown  
voltage of the output pins is 13V, so switch them in the  
range 0 to 12V. In addition to controlling the BA7630S  
switching block, these outputs can be used to control  
audio switching, scrambling decoders, and television  
sets.  
(3) Pulse timing  
The pulse timing diagrams are given below.  
CLK  
DATA  
t
su  
t
su  
0.1µs (Typ.) 1.0µs (Max.)  
(2) Using the serial-to-parallel convertor block  
Signal input is basically done using clock and date  
pulses. As shown in Fig.10, the date is read on the ris-  
ing edge of the clock pulses. If the date is “H” on the  
rising edge of the clock pulse, a “L” data bit is input to  
the shift register, and if the data is “L” on the rising  
edge of the clock pulse, a “H” data bit is input to the  
shift register. The shift register is sequentially incre-  
mented by the bit corresponding to SW1. Data in  
excess of 9 bits is sequentially discarded.  
Fig. 6 Clock rising edge and data relationship  
(setup time)  
CLK  
DATA  
t
su  
tsu  
If the data is “H” on a falling edge of the clock, the con-  
tents of the shift register are read into the internal latch,  
and simultaneously output to the output port (the data  
polarity is inverted on output). This output is maintained  
until the latch is setup again.  
0.1µs (Typ.) 1.0µs (Max.)  
Fig. 7 Clock falling edge and data relationship  
(setup time)  
To reset, set the RESET pin to “H”. The internal shift  
register and latch contents go low (latch output all “H”),  
for the duration that RESET is held high.  
RESET  
SW  
1 ~ SW9  
OUT  
CLK  
t
PLH  
tPHL  
0.26µs (Typ.) 2.0µs (Max.)  
DATA  
Fig. 8 Reset and output relationship  
(reset transmission time)  
1
2
3
4
5
At points 1 to 4 data is input to the shift register.  
At point 5 the contents of the shift register are transferred to the  
latch and simultaneously output.  
Fig. 4 CLK and DATA relationship  
Data flow  
CLK  
DATA  
Data in  
Shift register  
1
2
3
4
5
6
7
8
9
SW1 ~ SW9  
OUT  
Latch  
Reset  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Latch  
t
PLH9  
tPHL  
1.2µs (Typ.) 5.0µs (Max.)  
SW1 SW2  
SW9  
Fig. 9 Clock falling edge and output relationship  
(latch transmission time)  
Fig. 5 Digital block  
9
Multimedia ICs  
BA7630S / BA7630F  
Timing chart  
RESET  
DATA  
CLOCK  
SW1  
SW2  
SW3  
SW4  
SW5  
SW6  
SW7  
SW8  
SW9  
RESET  
DATA  
DATA  
RESET  
Fig.10  
10  
Multimedia ICs  
BA7630S / BA7630F  
Application examples  
(1) Analog block  
BA7630S pin layout  
V
CC1  
V
CC  
IN1  
IN2  
from  
3
5
2
5V  
VTR TUNER OUT  
1µF  
75Ω  
+
47µF  
OUT1  
OUT2  
from  
DECODER OUT  
22  
12  
11  
13  
to VCR  
V
CC2  
1µF  
75Ω  
R
75Ω  
75Ω  
to  
DECODER IN  
470 ~ 1000µF  
2SA933  
6dB  
AMP  
IN3  
IN4  
from  
7
1
6
V
CC2  
TV OUT  
1µF  
75Ω  
R
to  
OUT3  
GND  
TV IN  
470 ~ 1000µF  
2SA933  
6dB  
AMP  
from  
VIDEO OUT  
VCC2  
5V  
R
1µF  
75Ω  
100  
390  
GND  
12V  
Fig.11  
(2) Digital block  
VCC 4.5 ~ 13V  
22k  
SW OUT  
SW1 ~ SW9  
SW1 ~ SW4  
ONLY  
OPEN  
COLLECTOR  
50kΩ  
28kΩ  
Fig.12  
11  
Multimedia ICs  
BA7630S / BA7630F  
Electrical characteristic curves  
0
– 10  
– 20  
3pin-22pin  
5pin-22pin  
7pin-22pin  
3pin-22pin  
5pin-22pin  
7pin-22pin  
1pin-11pin  
5pin-11pin  
3pin-12pin  
7pin-12pin  
Input 1VP-P  
VIN  
=
10VP-P  
VIN = 1.0VP-P  
0
– 2  
– 4  
– 6  
– 8  
– 10  
– 12  
– 14  
– 16  
– 18  
– 20  
6
4
2
0
– 2  
– 4  
– 6  
– 8  
– 10  
– 12  
– 14  
– 30  
– 40  
– 50  
– 60  
– 70  
100k 200k 500k 1M 2M  
5M 10M 20M30M  
100k 200k 500k 1M 2M 5M 10M 20M30M  
FREQUENCY (Hz)  
100k 200k 500k 1M 2M  
5M 10M 20M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Fig. 13 Frequency characteristic(OUT1)  
Fig. 15 Frequency characteristic  
(OUT2 and OUT3)  
Fig. 14 Crosstalk characteristic (OUT1)  
0
1pin-11pin  
5pin-11pin  
3pin-12pin  
7pin-12pin  
Input 1VP-P  
– 10  
– 20  
– 30  
– 40  
– 50  
– 60  
– 70  
100k 200k 500k 1M 2M  
5M 10M 20M  
FREQUENCY (Hz)  
Fig. 16 Crosstalk characteristic  
(OUT2 and OUT3)  
External dimensions (Units: mm)  
BA7630S  
BA7630F  
18.5 ± 0.2  
19.4 ± 0.3  
28  
15  
22  
12  
7.62  
1
11  
1
14  
0° ~ 15°  
1.27  
0.4 ± 0.1  
1.778  
0.5 ± 0.1  
0.3Min.  
0.15  
SDIP22  
SOP28  
12  

相关型号:

BA7630F-E1

Consumer Circuit, Bipolar, PDSO28, SOP-28
ROHM

BA7630F-E2

Consumer Circuit, PDSO28, SOP-28
ROHM

BA7630F-T1

Consumer Circuit, PDSO28, SOP-28
ROHM

BA7630F-T2

Consumer Circuit, PDSO28, SOP-28
ROHM

BA7630FE1

SPECIALTY CONSUMER CIRCUIT, PDSO28, SOP-28
ROHM

BA7630FE2

SPECIALTY CONSUMER CIRCUIT, PDSO28, SOP-28
ROHM

BA7630FT1

SPECIALTY CONSUMER CIRCUIT, PDSO28, SOP-28
ROHM

BA7630FT2

SPECIALTY CONSUMER CIRCUIT, PDSO28, SOP-28
ROHM

BA7630S

Video switch for CANAL-Plus decoder
ROHM

BA7630S/F

マルチメディアLSI
ETC

BA7631

Video switch for CANAL-Plus decoder
ROHM

BA7631/F

Multimedia LSIs
ROHM