X28C513JI-15 [ROCHESTER]
EEPROM, 64KX8, 150ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | X28C513JI-15 |
| 厂家： | 
Rochester Electronics |
| 描述： | EEPROM, 64KX8, 150ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512K
64K x 8 Bit
X28C512/X28C513
5 Volt, Byte Alterable EEPROM
FEATURES
• Two PLCC and LCC pinouts
—X28C512
• X28C010 EPROM pin compatible
—X28C513
• Access time: 90ns
• Simple byte and page write
—Single 5V supply
• No external high voltages or V control
circuits
—Self-timed
• Compatible with lower density EEPROMs
PP
DESCRIPTION
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
—Active: 50mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable Direct Write™ cell
—Endurance: 100,000 write cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
The X28C512/513 is a 64K x 8 EEPROM, fabricated
with Xicor’s proprietary, high performance, floating
gate CMOS technology. Like all Xicor programmable
nonvolatile memories, the X28C512/513 is a 5V only
device. The X28C512/513 features the JEDEC
approved pin out for byte wide memories, compatible
with industry standard EPROMS.
The X28C512/513 supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less
than 2.5 seconds. The X28C512/513 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28C512/513 supports
the software data protection option.
—Toggle bit polling
BLOCK DIAGRAM
512Kbit
EEPROM
Array
X Buffers
Latches and
Decoder
A –A
7
15
I/O Buffers
and Latches
Y Buffers
Latches and
Decoder
A –A
0
6
I/O –I/O
0
7
Data Inputs/Outputs
CE
Control
Logic and
Timing
OE
WE
V
V
CC
SS
Characteristics subject to change without notice. 1 of 24
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X28C512/X28C513
PIN CONFIGURATIONS
TSOP
A
A
A
A
A14
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
PLCC/LCC
11
9
8
A
10
CE
I/O
13
7
Plastic DIP
CERDIP
FLAt Pack
SOIC (R)
I/O6
30
29
4
3
2
32 31
I/O
I/O
I/O
5
4
3
A
A
A
5
A
14
7
6
5
1
A
28
6
7
13
A
27
26
8
WE
NC
NC
V
V
A
A
A
9
CC
NC
X28C512
8
9
4
3
X28C512
(Top View)
NC
NC
V
SS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
25
24
23
22
CC
11
NC
NC
NC
A15
A
A
A
A
A
NC
A
A
10
11
OE
2
1
2
WE
NC
NC
I/O
A
10
2
A
3
A
12
13
CE
I/O1
15
12
0
I/O
12
7
6
5
4
0
I/O
I/O
7
0
15 16 17 18 19 20
4
A
A
14
A
21
0
14
A
1
A
A
5
A
A
13
7
6
5
2
3
A
8
A
6
A
A
7
A
9
PGA
8
A
4
3
2
1
0
11
X28C512
I/O
15
I/O
17
I/O
I/O
21
I/O
22
0
2
1
3
5
4
6
7
A
OE
9
19
30
29
A
A
10
11
12
13
14
15
16
10
4
3
2
32 31
CE
24
A
5
A
8
A
13
A
I/O
16
V
SS
18
I/O
20
I/O
23
6
5
4
1
0
1
14
A
CE
I/O
A
A
A
9
28
6
7
A
OE
26
27
26
11
A
A
A
10
25
2
3
A
5
A
A
NC
OE
12
11
8
9
3
2
X28C513
(Top View)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
25
24
23
22
4
3
2
1
0
1
2
A
A
A
A
9
28
4
5
11
Bottom
View
A
A
A
10
11
10
9
7
10
27
1
0
CE
I/O
A
A
A
A
13
30
6
7
8
NC
I/O
12
13
7
29
8
I/O
0
6
15 16 17 18 19 20
SS
21
14
A
NC
V
NC
34
NC
32
A
A
14
31
15
CC
12
6
5
4
2
36
NC
NC
NC
1
NC
33
WE
35
3
PIN DESCRIPTIONS
Addresses (A0–A15)
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28C512/513.
The Address inputs select an 8-bit memory location
during a read or write operation.
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Chip Enable (CE)
0
15
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
I/O –I/O
0
7
WE
CE
OE
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
V
CC
V
Ground
SS
Data In/Data Out (I/O –I/O )
0
7
NC
No Connect
Data is written to or read from the X28C512/513
through the I/O pins.
Characteristics subject to change without notice. 2 of 24
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X28C512/X28C513
DEVICE OPERATION
Read
Write Operation Status Bits
The X28C512/513 provides the user two write opera-
tion status bits. These can be used to optimize a sys-
tem write cycle time. The status bits are mapped onto
the I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Reserved
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28C512/513 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
Toggle Bit
DATA Polling
DATA Polling (I/O )
7
The X28C512/513 features DATA polling as a method
to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
X28C512/513, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O will reflect true
Page Write Operation
The page write feature of the X28C512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28C512/513, prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
7
7
data.
Toggle Bit (I/O )
6
source address), but the page address (A through
7
The X28C512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete, the toggling will cease, and the device will
be accessible for additional read or write operations.
A ) for each subsequent valid write cycle to the part
15
during this operation must be the same as the initial
page address.
6
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by
the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a sub-
sequent WE HIGH to LOW transition is not detected
within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively, the page write window is infinitely
wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
Characteristics subject to change without notice. 3 of 24
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X28C512/X28C513
DATA POLLING I/O
7
Figure 2a. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28C512/513
Ready
A –A
A
A
A
A
A
A
A
n
0
15
n
n
n
n
n
n
Figure 2b. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28C512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The soft-
ware flow diagram in Figure 2b illustrates one method
of implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
No
7
Compare?
Yes
Ready
Characteristics subject to change without notice. 4 of 24
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X28C512/X28C513
THE TOGGLE BIT I/O
6
Figure 3a. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
V
HIGH Z
OH
I/O
6
*
*
V
X28C512/513
Ready
OL
* Beginning and ending state of I/O will vary.
6
Figure 3b. Toggle Bit Software Flow
provide a method for status checking in multiprocessor
applications.The timing diagram in Figure 3a illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3b illustrates a method for polling the
Toggle Bit.
Last Write
HARDWARE DATA PROTECTION
The X28C512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
Load Accum
From Addr N
– Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
– Default V
Sense—All write functions are inhibited
is 3.6V.
CC
Compare
Accum with
Addr N
when V
CC
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
No
Compare
Ok?
Yes
SOFTWARE DATA PROTECTION
X28C512
Ready
The X28C512/513 offers a software controlled data
protection feature. The X28C512/513 is shipped from
Xicor with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to imple-
ment DATA Polling. This can be especially helpful in an
array comprised of multiple X28C512/513 memories
that is frequently updated. Toggle Bit Polling can also
and write access of the device once V was stable.
CC
Characteristics subject to change without notice. 5 of 24
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X28C512/X28C513
The X28C512/513 can be automatically protected dur-
ing power-up and power-down without the need for
external circuits by employing the software data pro-
tection feature. The internal software data protection
circuit is enabled after the first write operation utilizing
the software algorithm. This circuit is nonvolatile and
will remain set for the life of the device unless the reset
command is issued.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 4a and 4b for the
sequence. The three byte sequence opens the page
write window, enabling the host to write from one to
one hundred twenty-eight bytes of data. Once the page
load cycle has been completed, the device will auto-
matically be returned to the data protected state.
Once the software protection is enabled, the X28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device. Note: The data in the three-byte
enable sequence is not written to the memory array.
Software Data Protection
Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write
V
CC
(V
)
CC
0V
Data
Addr
AAA
5555
55
2AAA
A0
5555
Writes
ok
t
Write
Protected
WC
CE
≤ t
Byte
or
Page
BLC MAX
WE
Note: All other timings and control pins are per page write timing requirements
Characteristics subject to change without notice. 6 of 24
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X28C512/X28C513
Figure 4b. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
X28C512/513 will automatically disable further writes,
unless another command is issued to cancel it. If no
further commands are issued the X28C512/513 will be
write protected during power-down and after any sub-
Write Data AA
to Address
5555
sequent power-up. The state of A while executing the
15
algorithm is don’t care.
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data 80
to Address
5555
Write Data XX
to any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After t
WC
Re-Enters Data
Protected State
Characteristics subject to change without notice. 7 of 24
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X28C512/X28C513
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
V
CC
Data
Addr
AAA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Standard
Operating
Mode
≥ t
WC
CE
WE
Note: All other timings and control pins are per page write timing requirements
Figure 5b. Software Sequence to Deactivate
Software Data Protection
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Write Data AA
to Address
5555
Because the X28C512/513 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion and eliminate the possibility of contention where
multiple I/O pins share the same bus.
Write Data 55
to Address
2AAA
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the pri-
mary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is/are outputting data on the bus.
Write Data A0
to Address
5555
Write Data AA
to Address
5555
Because the X28C512/513 has two power modes,
(standby and active), proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
be used between V
Depending on the size of the array, the value of the
capacitor may have to be larger.
and V
at each device.
CC
SS
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t
,
WC
the X28C512/513 will be in standard operating mode.
Characteristics subject to change without notice. 8 of 24
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X28C512/X28C513
In addition, it is recommended that a 4.7µF electrolytic
I
(RD) by Temperature Over Frequency
CC
bulk capacitor be placed between V
and V
for
CC
SS
70
each 8 devices employed in the array. This bulk capaci-
tor is employed to overcome the voltage droop caused
by the inductive effects of the PC board traces.
5.0 V
CC
60
50
40
30
20
10
–55°C
+25°C
+125°C
Active Supply Current vs. Ambient Temperature
14
V
= 5V
CC
13
12
11
10
9
3
6
9
12
15
0
Frequency (MHz)
8
–55
–10
+35
+80
+125
Ambient Temperature (°C)
Standby Supply Current vs. Ambient Temperature
0.24
V
= 5V
CC
0.22
0.2
0.18
0.16
0.14
0.12
0.1
–10
+35
+80
+125
–55
Ambient Temperature (°C)
Characteristics subject to change without notice. 9 of 24
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X28C512/X28C513
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28C512/513...................................–10°C to +85°C
X28C512I/513I...............................–65°C to +135°C
X28C512M/513M...........................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on any pin with
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature
(soldering, 10 seconds) ..................................300°C
RECOMMEND OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28C512/513
5V 10ꢀ
–40°C
–55°C
Military
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
CE = OE = V , WE = V , All I/O’s = open,
address inputs = .4V/2.4V Levels @ f = 5MHz
I
V
V
current (active) (TTL inputs)
50
mA
CC
CC
IL
IH
I
I
current (standby) (TTL
3
mA
µA
CE = V , OE = VIL, All I/O’s = open, other
SB1
SB2
CC
IH
inputs)
inputs = V
IH
V
current (standby) (CMOS
500
CE = V – 0.3V, OE = VIL, All I/O’s = Open,
CC
Other Inputs = V
IH
CC
inputs)
I
Input leakage current
Output leakage current
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V , CE = V
SS CC IH
LO
OUT
(1)
V
–1
2
0.8
lL
(1)
V
V
+ 1
V
IH
CC
V
0.4
V
I
I
= 2.1mA
OL
OL
V
2.4
V
= –400µA
OH
OH
Note: (1) V min. and V max. are for reference only and are not tested.
IL
IH
POWER-UP TIMING
Symbol
Parameter
Max.
100
5
Unit
µs
(2)
t
Power-up to read operation
Power-up to write operation
PUR
(2)
t
ms
PUW
Characteristics subject to change without notice. 10 of 24
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X28C512/X28C513
CAPACITANCE T = +25°C, F = 1MHZ, V
= 5V
A
CC
Symbol
Parameter
Input/output capacitance
Input capacitance
Max.
10
Unit
pF
Test Conditions
(2)
C
V
= 0V
= 0V
I/O
I/O
(2)
C
10
pF
V
IN
IN
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Unit
Endurance
Endurance
10,000
Cycles per byte
Cycles per page
Years
100,000
100
Data retention
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
10ns
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
Must be
steady
Will be
steady
1.5V
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
MODE SELECTION
CE OE WE
Mode
Read
Write
I/O
Power
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
L
L
H
L
D
Active
Active
OUT
H
D
IN
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Standby and
write inhibit
High Z
Standby
H
X
X
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
Output
1.37KΩ
100pF
Note: (2) This parameter is periodically sampled and not 100ꢀ
tested.
Characteristics subject to change without notice. 11 of 24
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X28C512/X28C513
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25
X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25
Symbol
Parameter
Read cycle time
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
90
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
Chip enable access time
Address access time
90
90
40
120
120
50
150
150
50
200
200
50
250
250
50
CE
t
AA
OE
t
Output enable access time
CE LOW to active output
OE LOW to active output
CE HIGH to high Z output
OE HIGH to high Z output
(3)
t
0
0
0
0
0
0
0
0
0
0
LZ
(3)
t
OLZ
(3)
t
40
40
50
50
50
50
50
50
50
50
HZ
(3)
t
OHZ
t
Output hold from address
change
0
0
0
0
0
OH
Read Cycle
t
RC
Address
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
AA
HIGH Z
Data I/O
Data Valid
Data Valid
Note: (3) t min., t , t
min., and t
are periodically sampled and not 100ꢀ tested. t max. and t
max. are measured, with C = 5pF
LZ
HZ OLZ
OHZ
HZ
OHZ L
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Characteristics subject to change without notice. 12 of 24
REV 1.0 6/27/00
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X28C512/X28C513
WRITE CYCLE LIMITS
Symbol
Parameter
Write cycle time
Min.
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
(4)
t
10
WC
t
Address setup time
Address hold time
Write setup time
Write hold time
CE pulse width
OE HIGH setup time
OE HIGH hold time
WE pulse width
WE High recovery
Data valid
0
50
0
AS
AH
CS
CH
t
t
t
0
t
100
10
10
100
100
CW
t
OES
OEH
t
t
WP
t
WPH
t
t
1
DV
DS
DH
Data setup
50
0
t
Data hold
t
Delay to next write
Byte load cycle
10
0.2
DW
t
100
BLC
WE Controlled Write Cycle
t
WC
Address
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
t
DV
Data In
Data Out
Data Valid
t
t
DH
DS
HIGH Z
Note: (4) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to complete the internal write operation.
Characteristics subject to change without notice. 13 of 24
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X28C512/X28C513
CE Controlled Write Cycle
t
WC
Address
t
t
AH
AS
t
CW
CE
OE
t
WPH
t
OES
t
OEH
t
t
t
CS
CH
WE
t
DV
Data Valid
Data In
t
DS
DH
HIGH Z
Data Out
Page Write Cycle
OE(5)
CE
t
t
BLC
WP
WE
t
WPH
Address*(6)
Last Byte
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
7
15
writes to an unknown address could occur.
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively per-
forming a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Characteristics subject to change without notice. 14 of 24
REV 1.0 6/27/00
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X28C512/X28C513
DATA Polling Timing Diagram(7)
Address
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
D
= X
OUT
I/O
7
IN
OUT
t
WC
Toggle Bit Timing Diagram
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
*Starting and ending state will vary, depending upon actual t
.
WC
Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Characteristics subject to change without notice. 15 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Hermetic Dual In-Line Package Type D
1.690 (42.95)
Max.
0.610 (15.49)
0.500 (12.70)
Pin 1
0.005 (0.13) Min.
0.100 (2.54) Max.
Seating
Plane
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.033 (0.84)
Typ. 0.055 (1.40)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° Ref.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
Pin 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
0.015 (0.38)
TYP. (4) PLCS.
Min.
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.050 (1.27) BSC
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.120 (3.05)
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: 1ꢀ NLT 0.005 (0.127)
Characteristics subject to change without notice. 17 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Ceramic Flat Pack Type F
1.228 (31.19)
1.000 (25.40)
Pin 1 Index
0.019 (0.48)
0.015 (0.38)
1
32
0.050 (1.27) BSC
0.830 (21.08) Max.
0.045 (1.14) Max.
0.005 (0.13) Min.
0.488
0.430 (10.93)
0.120 (3.05)
0.090 (2.29)
0.007 (0.18)
0.004 (0.10)
0.370 (9.40)
0.270 (6.86)
0.045 (1.14)
0.026 (0.66)
0.347 (8.82)
0.330 (8.38)
0.030 (0.76)
Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 18 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
0.045 (1.14) x 45°
0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
Ref.
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
Ref.
(10.16)
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
Characteristics subject to change without notice. 19 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Plastic Dual In-Line Package Type P
1.665 (42.29)
1.644 (41.76)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.500 (38.10)
Ref.
0.160 (4.06)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.070 (17.78)
0.030 (7.62)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
15°
Typ. 0.010 (0.25)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 20 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom.
See Detail “A”
For Lead
Information
0.020 Min.
0.165 Typ.
0.035 Typ.
0.340
0.007
0.015 R Typ.
0.015 R
Typ.
0.035 Min.
Detail “A”
0.050"
Typical
0.0192
0.0138
0.050"
Typical
0.560"
Typical
0.840
Max.
0.750
0.005
0.030" Typical
32 Places
0.050
FOOTPRINT
0.440 Max.
0.560 Nom.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
Characteristics subject to change without notice. 21 of 24
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X28C512/X28C513
PACKAGING INFORMATION
36-Lead Ceramic Pin Grid Array Package Type K
15
17
16
19
18
21
20
22
23
25
27
29
32
33
A
A
0.008 (0.20)
0.050 (1.27)
13
12
10
8
14
11
9
24
26
28
30
31
NOTE:Leads 5, 14,23, & 32
7
Typ. 0.100 (2.54)
All Leads
6
5
2
3
36
1
34
35
Typ. 0.180 (.010)
(4.57 .25)
4 Corners
4
Typ. 0.180 (.010)
(4.57 .25)
4 Corners
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
Pin 1 Index
0.770 (19.56)
0.750 (19.05)
SQ
0.020 (0.51)
0.016 (0.41)
A
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 24
REV 1.0 6/27/00
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X28C512/X28C513
PACKAGING INFORMATION
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
(0.038)
0.965
Pin #1 Ident
0.035 (0.889)
0.005 (0.127) Dp.
O 0.040 (1.016)
X
O 0.030 (0.762) 0.003 (0.076) Dp.
0.048 (1.219)
0.0197 (0.500)
1
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° Typ.
Seating
Plane
0.010 (0.254)
0.006 (0.152)
0.040 (1.016)
A
0.0025 (0.065)
Seating
Plane
Detail A
0.032 (0.813) Typ.
0.557 (14.148)
0.547 (13.894)
0.006 (0.152)
0.017 (0.432)
0.017 (0.432)
Typ.
4° Typ.
0.020 (0.508) Typ.
14.80 0.05
(0.583 0.002)
0.30 0.05
(0.012 0.002)
Solder
Pads
Typical
40 Places
15 Eq. Spc.@ 0.50 0.04
0.0197 0.016 = 9.50 0.06
(0.374 0.0024) Overall
Tol. Non-Cumulative
0.17 (0.007)
0.03 (0.001)
0.50 0.04
(0.0197 0.0016)
1.30 0.05
(0.051 0.002)
FOOTPRINT
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
Characteristics subject to change without notice. 23 of 24
REV 1.0 6/27/00
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X28C512/X28C513
Ordering Information
X28C512
X
X
-X
Access Time
–90 = 90ns
Device
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
X28C513
X
X
-X
Package
D = 32-Lead CerDip
E = 32-Pad LCC
Access Time
Device
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
P = 32-Lead Plastic Dip
R = 32-Lead Ceramic SOIC
T = 40-Lead TSOP
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
Package
E = 32-Pad LCC
J = 32-Lead PLCC
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 24 of 24
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