W185-5H [ROCHESTER]
75MHz, OTHER CLOCK GENERATOR, PDSO24, 0.209 INCH, MO-150AD, SSOP-24;
| 型号： | W185-5H |
| 厂家： | 
Rochester Electronics |
| 描述： | 75MHz, OTHER CLOCK GENERATOR, PDSO24, 0.209 INCH, MO-150AD, SSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W185
Six Output Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread output of Reference input
• Integrated loop filter components
W185
W185-5
Output
SS%
Output
0
F
F
in ≥ Fout ≥ Fin – 1.25% Fin + 0.625% ≥ Fin≥
– 0.625%
1
in ≥ Fout ≥ Fin – 3.75% Fin + 1.875% ≥ Fin≥
–1.875%
• Operates with a 3.3V or 5V supply
• Low power CMOS design
Table 2. Frequency Range Selection
• Available in 24-pin SSOP (Shrink Small Outline
Package)
• Outputs may be selectively disabled
FS2
0
FS1
0
Frequency Range
28 MHz ≤ FIN ≤ 38 MHz
38 MHz ≤ FIN ≤ 48 MHz
46 MHz ≤ FIN ≤ 60 MHz
58 MHz ≤ FIN ≤ 75 MHz
0
1
Key Specifications
1
0
Supply Voltages:...........................................VDD = 3.3V±5%
or VDD = 5V±10%
1
1
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range:................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage:....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Table 3. Output Enable
EN1
EN2
CLK0:4
CLK5
0
0
1
1
0
1
0
1
Low
Low
Low
Active
Low
Active
Active
Active
Simplified Block Diagram
Pin Configuration
3.3V or 5.0V
SSOP
REFOUT
FS2
SSON#
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
RESET
FS1
X1
X1
XTAL
Input
40MHz
max.
X2
VDD
VDD
X2
Spread Spectrum
Output
(EMI suppressed)
W185
GND
NC
SS%
EN2
GND
EN1
CLK5
3.3V or 5.0V
VDD
CLK0
VDD
CLK1
CLK2
10
11
CLK4
GND
15
14
12
CLK3
13
Oscillator or
Reference Input
Spread Spectrum
W185
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07159 Rev. **
Revised September 25, 2001
W185
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CLK0:5
9, 11, 12, 13,
15, 17
O
I
Modulated Frequency Outputs: Frequency modulated copies of the unmod-
ulated input clock (SSON# asserted).
CLKIN or X1
3
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
SS%
4
6
I
I
Crystal Connection: If using an external reference, this pin must be left un-
connected.
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistor.
Reset
23
1
I
ModulationProfileRestart:Arisingedgeonthisinputrestartsthemodulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
REFOUT
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
EN1:2
18, 7
24
I
I
Output Enable Select Pins: These pins control the activity of specific output
buffers. See Table 3 on page 1.
SSON#
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
FS1:2
22, 2
I
Frequency Selection Bit 1 and 2: These pins select the frequency of opera-
tion. Refer to Table 1. These pins have internal pull-up resistors.
VDD
GND
NC
10, 16, 20, 21
5, 8, 14
19
P
G
Power Connection: Connected to 3.3V or 5V power supply.
Ground Connection: This should be connected to the common ground plane.
No Connect: This pin should be left floating.
NC
Document #: 38-07159 Rev. **
Page 2 of 9
W185
times the reference frequency. (Note: For the W184 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Overview
The W185 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage may be selected as either
1.25% or 3.75% (see Table 1).
The W185 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
VDD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
Σ
VCO
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Document #: 38-07159 Rev. **
Page 3 of 9
W185
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07159 Rev. **
Page 4 of 9
W185
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
TSTG
TA
°C
°C
°C
W
Operating Temperature
TB
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
PD
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
18
32
5
tON
Power Up Time
First locked clock cycle after Power
Good
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.8
0.4
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
2.4
V
2.4
V
Note 1
–50
µA
µA
mA
mA
pF
kΩ
Ω
IIH
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
Note 1
50
7
IOL
IOH
CI
@ 0.4V, VDD = 3.3V
@ 2.4V, VDD = 3.3V
15
15
RP
500
25
ZOUT
Note:
1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07159 Rev. **
Page 5 of 9
W185
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
30
tON
Power Up Time
First locked clock cycle after
Power Good
5
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.15VDD
0.4
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
0.7VDD
V
2.4
V
Note 1
–100
µA
µA
mA
mA
pF
kΩ
Ω
IIH
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
Note 1
50
7
IOL
IOH
CI
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
24
24
RP
500
25
ZOUT
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
fOSC
Internal Xtal Oscillator
Frequency
Xtal connected to X1, X2
28
40
MHz
fIN
Input Frequency
External reference
28
28
75
75
MHz
MHz
fOUT
Output Frequency
Spread Off, FS2:1 per
Table 2
tR
Output Rise Time
Output Fall Time
15-pF load 0.8V–2.4V
15-pF load 2.4 –0.8V
15-pF load
2
2
5
5
ns
ns
%
tF
tOD
Output Duty Cycle
Input Duty Cycle
40
40
60
60
300
tID
%
tJCYC
EMIRED
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
dB
fout = 40 MHz, third harmonic
measured, reference board,
15-pF load
8
tSK
Output to Output Skew
300
ps
Document #: 38-07159 Rev. **
Page 6 of 9
W185
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
Figure 5 shows a recommended 2-layer board layout.
R
Reference Output
1
2
3
24
23
22
Logic Input
XTAL Connection or Reference Input
XTAL Connection or NC
4
5
6
7
8
21
20
C2
0.1 µF
C3
0.1
NC
19
18
17
16
15
14
µF
R
Output
Clock
Clock Output
9
R
10
11
12
C4
0.1
R
Output
Output
Clock
Clock
Clock Output
µF
R
R
R
13
Clock Output
C1
µF
0.1
FB
C5
10
3.3V or 5V System Supply
µF Tantalum
Figure 4. Recommended Circuit Configuration
High frequency supply decoupling
C1....C4 =
µF recommended).
capacitor (0.1-
C5 =
Common supply low frequency
Xtal Connection or Reference Input
Xtal Connection or NC
-µF tantalum
decoupling capacitor (10
recommended).
C2
C3
G
G
R =
Match value to line impedance
=
Ferrite Bead
G
FB
G
=
Via To GND Plane
R
G
R
Clock Output
G
C4
R
G
C1
R
G
G
Power Supply Input
(3.3V or 5V)
FB
C5
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Package
Name
Ordering Code
Package Type
W185
H
24-Pin SSOP (209-mil)
W185-5
Document #: 38-07159 Rev. **
Page 7 of 9
W185
Package Diagram
24-Pin Shrink Small Outline Package (SSOP, 209-mil)
Document #: 38-07159 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W185
Document Title: W185 Six Output Peak Reducing EMI Solution
Document Number: 38-07159
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
110269
10/28/01
SZV
Change from Spec number: 38-00809 to 38-07159
Document #: 38-07159 Rev. **
Page 9 of 9
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