TCM29C16ADW [ROCHESTER]
MU-LAW, PCM CODEC, PDSO16;
| 型号： | TCM29C16ADW |
| 厂家： | 
Rochester Electronics |
| 描述： | MU-LAW, PCM CODEC, PDSO16 PC 光电二极管 |
| 文件： | 总26页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
FEATURES TABLE
Replace Use of TCM2910A and TCM2911A
in Tandem With TCM2912B/C
29C13A 29C14A 29C16A 29C17A
129C13A 129C14A 129C16A 129C17A
FEATURE
Reliable Silicon-Gate CMOS Technology
Number of Pins:
Low Power Consumption:
24
20
16
X
X
Operating Mode . . . 80 mW Typical
Power-Down Mode . . . 5 mW Typical
X
X
X
µ-Law/A-Law Coding:
µ-Law
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
X
X
X
X
A-Law
No External Components Needed for
Sample, Hold, and Autozero Functions
Gain Timing Rates:
Variable Mode
64 kHz to 2.048 MHz
X
X
X
X
X
X
Precision Internal Voltage References
Fixed Mode
1.536 MHz
1.544 MHz
2.048 MHz
X
X
X
X
X
X
Improved Version of TCM29C13 Series
and TCM129C13 Series
Loopback Test Capability
8th-Bit Signaling
X
X
description
The TCM29C13A, TCM29C14A, TCM29C16A,
TCM29C17A, TCM129C13A, TCM129C14A,
TCM129C16A, and TCM129C17A are single-chip PCM codecs (pulse-code-modulated encoders and
decoders)andPCMlinefilters. Thesedevicesprovideallthefunctionsrequiredtointerfaceafull-duplex(4-wire)
voice telephone circuit with a time-division-multiplexed (TDM) system. These devices are intended to replace
the TCM2910A or TCM2911A in tandem with the TCM2912C. Primary applications include:
•
Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone
systems
•
•
•
•
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data storage systems
Digital signal processing
TCM29C13A, TCM129C13A
DW OR N PACKAGE
TCM29C14A, TCM129C14A
DW PACKAGE
TCM29C16, TCM29C16A,
TCM129C16, TCM129C17A
DW OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
V
V
CC
GSX
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
BB
V
V
CC
19 GSX
1
2
3
4
5
6
7
8
9
10
20
BB
V
V
CC
GSX
PWRO+
PWRO–
GSR
1
2
3
4
5
6
7
8
16
15
14
13
BB
PWRO+
PWRO–
GSR
PWRO+
PWRO–
PDN
ANLG IN–
ANLG IN+
ANLG GND
NC
18
17
16
15
14
13
12
11
ANLG IN–
ANLG IN+
ANLG GND
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
ANLG IN–
ANLG GND
PDN
PDN
DCLKR
12 TSX/DCLKX
CLKSEL
ANLG LOOP
SIGR
CLKSEL
DCLKR
11
10
9
PCM IN
PCM OUT
FSX/TSXE
CLKR/CLKX
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
FSR/TSRE
DGTL GND
PCM IN
FSR/TSRE
DGTL GND
DCLKR
PCM IN
FSR/TSRE 11
DGTL GND 12
14 CLKX
13 CLKR
NC – No internal connection
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
description (continued)
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are
intended to be used at the analog termination of a PCM line or trunk.
The TCM29C13A, TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A,
and TCM129C17A provide the band-pass filtering of the analog signals prior to encoding and after decoding.
These combination devices perform the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information. These devices contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below –55 dBm0.
The TCM29C13A, TCM29C14A, TCM29C16A, and TCM29C17A are characterized for operation from 0°C to
70°C. The TCM129C13A, TCM129C14A, TCM129C16A, and TCM129C17A are characterized for operation
from –40°C to 85°C.
functional block diagram
Transmit Section
Autozero
PCM OUT
Filter
Sample
and Hold
and DAC
ANLG IN+
ANLG IN–
GSX
Successive
Approximation
Output
Register
Comparator
TSX/DCLKX
SIGX/ASEL
Analog-
to-Digital
Control
Logic
FSX/TSXE
CLKX
Reference
CLKSEL
Receive Section
Control
Section
Control
Logic
PDN
Filter
‡
Gain
Σ
ANLG
LOOP
GSR
†
Set
Buffer
Digital-
to-Analog
Control
Logic
PCM IN
DCLKR
Sample
and Hold
and DAC
PWRO–
Input
Register
PWRO+
†
SIGR
Reference
FSR/TSRE
CLKR
†
DGTL ANLG
GND GND
V
CC
V
BB
†
‡
TCM29C14A and TCM129C14A only.
TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and TCM129C17A only
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
Terminal Functions
TERMINAL
NO.
TCM29C16A
TCM29C17A
TCM129C16A
TCM129C17A
I/O
DESCRIPTION
NAME
TCM29C13A
TCM129C13A TCM129C14A
TCM29C14A
ANLG GND
ANLG IN+
16
17
20
21
13
Analog ground return for all internal voice circuits. ANLG GND is
internally connected to DGTL GND.
I
Noninverting analog input to uncommitted transmit operational
amplifier. ANLG IN+ is internally connected to ANLG GND on
TCM29C16A, TCM129C16A, TCM29C17A, and TCM129C17A.
ANLG IN–
18
11
22
7
14
9
I
I
Invertinganaloginputtouncommittedtransmitoperationalamplifier.
ANLG LOOP
Provides loopback test capability. When ANLG LOOP is high,
PWRO+ is internally connected to ANLG IN.
CLKR
13
I
Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. CLKR and
CLKX are internally connected together for the TCM29C13A,
TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and
TCM129C17A.
CLKSEL
CLKX
6
11
7
6
14
9
I
I
I
Clock-frequency selection. CLKSEL must be connected to V
,
,
BB
BB
V
,orGNDtoreflectthemasterclockfrequency.WhentiedtoV
CC
CLK is 2.048 MHz. When tied to GND, CLK is 1.544 MHz.
When tied to V , CLK is 1.536 MHz.
CC
9
5
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. CLKR and
CLKX are internally connected for the TCM29C13A, TCM29C16A,
TCM29C17A, TCM129C13A, TCM129C16A, and TCM129c17A.
DCLKR
Selects fixed- or variable-data-rate operation. When DCLKR is
connected to V , the device operates in the fixed-data-rate mode.
BB
When DCLKR is not connected to V , the device operates in the
BB
variable-data-rate mode and DCLKR becomes the receiver data
clock, which operates at frequencies from 64 kHz to 2.048 MHz.
DGTL GND
FSR/TSRE
10
9
12
11
8
7
Digital ground for all internal logic circuits. DGTL GND is internally
connected to ANLG GND.
I
I
Frame-synchronization clock input/time-slot enable for receive
channel. In the fixed-data-rate mode, FSR distinguishes between
signaling and nonsignaling frames by a double- or single-length
pulse, respectively. In the variable-data-rate mode, this signal must
remain high for the duration of the time slot. The receive channel
enters the standby state when FSR is TTL low for 300 ms.
FSX/TSXE
12
15
10
15
Frame-synchronization clock input/time-slot enable for transmit
channel. FSX/TSXE operates independently of, but in an analagous
manner to, FSR/TSRE. The transmit channel enters the standby
state when FSX is low for 300 ms.
GSR
GSX
4
4
I
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending
upon the voltage at GSR.
19
23
O
Output terminal of internal uncommitted operational amplifier.
Internally, this is the voice signal input to the transmit filter.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
Terminal Functions (Continued)
TERMINAL
NO.
TCM29C16A
TCM29C17A
TCM129C16A
TCM129C17A
I/O
DESCRIPTION
NAME
TCM29C13A
TCM129C13A TCM129C14A
TCM29C14A
PCM IN
8
10
16
6
I
Receive PCM input. PCM data is clocked in on PCM IN on eight
consecutive negative transitions of the receive data clock, which is
CLKR in fixed-data-rate timing and DCLKR in variable-data-rate
timing.
PCM OUT
13
11
O
TransmitPCM output. PCM data is clocked out on PCM OUT on eight
consecutive positive transitions of the transmit data clock, which is
CLKX in fixed-data-rate timing and DCLKX in variable-data-rate
timing.
PDN
5
2
5
2
4
2
I
Power-down select. The device is inactive with a TTL low-level input
to this PDN and active with a TTL high-level input to this PDN.
PWRO+
O
Noninverting output of power amplifier. PWRO+ drives transformer
hybrids or high-impedance loads directly in either a differential or a
single-ended configuration.
PWRO–
SIGR
3
3
8
3
O
O
Inverting output of power amplifier. PWRO– is functionally identical
with and complementary to PWRO+.
Signaling bit output, receive channel. In the fixed-data-rate mode,
SIGR outputs the logical state of the 8th bit (LSB) of the PCM word
in the most recent signaling frame.
SIGX/ASEL
15
18
I
A-law and µ-law operation select. When connected to V , A-law is
BB
selected. When connected to V
or GND, µ-law is selected. When
CC
not connected to V , it is a TTL-level input that is transmitted as the
BB
eighth bit (LBS) of the PCM word during signaling frames on PCM
OUT (TCM29C14A and TCM129C14A only). SIGX/ASEL is
internally connected to provide µ-law operational for TCM29C16A
and TCM129C16A and A-law operation for TCM29C17A and
TCM129C17A.
TSX/DCLKX
14
17
12
I/O Transmitchannel time-slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, TSX/DCLKX is an
open-drain output to be used as an enable signal for a 3-state output
buffer. In the variable-data-rate mode, DCLKX becomes the transmit
data clock, which operates at a TTL level from 64 kHz to 2.048 MHz.
V
V
1
1
1
Most negative supply voltage. Input is –5 V ±5%.
Most positive supply voltage. Input is 5 V ±5%.
BB
20
24
16
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Output voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
CC
O
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
I
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . 1375 mW
Operating free-air temperature range, T : TCM29CxxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TCM129CxxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to V
.
BB
recommended operating conditions (see Note 2)
MIN
4.75
NOM
5
MAX
5.25
UNIT
V
V
Supply voltage (see Note 3)
V
V
V
V
V
CC
Supply voltage
–4.75
–5
0
–5.25
BB
Digital ground voltage, with respect to ANLG GND
High-level input voltage, all inputs except CLKSEL
Low-level input voltage, all inputs except CLKSEL
2.048 MHz
V
V
2.2
IH
0.8
IL
V
BB
0
V
+0.5
BB
V
I
CLKSEL input voltage
1.544 MHz
0.5
CC
V
1.536 MHz
V
–0.5
10
V
CC
GSX
kΩ
R
C
Load resistance
L
L
PWRO+ and/or PWRO–
GSX
300
Ω
50
Load capacitance
pF
PWRO+ and/or PWRO–
TCM29CxxA
TCM129CxxA
100
70
0
T
A
Operating free-air temperature
°C
–40
85
NOTES: 2. ToavoidpossibledamagetotheseCMOSdevicesandresultingreliabilityproblems, thepower-upproceduredescribedinthedevice
power-up sequence paragraphs later in this document should be followed.
3. Voltage is at analog inputs and outputs. V
to DGTL GND unless otherwise noted.
and V terminals are with respect to ANLG GND. All other voltages are referenced
BB
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, f
= 2.048 MHz, outputs not loaded
TEST CONDITIONS
DCLK
TCM29CxxA
TCM129CxxA
PARAMETER
UNIT
†
†
MIN TYP
MAX
9
MIN TYP
MAX
13
Operating
7
8
Supply current
from V
Standby
FSX or FSR at V after 300 ms
IL
0.5
0.3
–7
1.1
0.9
–9
–1
–0.9
90
0.7
0.4
–8
1.5
1
I
I
mA
CC
CC
Power down
Operating
Standby
PDN V after 300 ms
IL
–13
–1.5
–1.1
130
15
Supply current
from V
FSX or FSR at V after 300 ms
IL
–0.5
–0.3
70
–0.7
–0.4
80
mA
BB
BB
Power down
Operating
Standby
PDN V after 300 ms
IL
P
Power dissipation
FSX or FSR at V after 300 ms
IL
5
10
7
mW
D
Power down
3
8
4
10
PDN V after 300 ms
IL
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
ground terminals
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC resistance between ANLG GND and DGTL GND
34
Ω
digital interface
TCM29CxxA
†
TCM129CxxA
†
MAX
TEST CONDI-
TIONS
PARAMETER
UNIT
MIN TYP
MAX
MIN TYP
PCM OUT
SIGR
I
I
= –9.6 mA
= –1.2 mA
2.4
2.4
2.4
2.4
OH
V
V
High-level output voltage
V
V
OH
OH
Low-level output voltage at PCM OUT, TSX,
SIGR
I
= 3.2 mA
0.4
0.5
OL
OL
I
I
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
V = 2.2 V to V
CC
10
10
10
12
12
10
µA
µA
pF
pF
IH
I
V = 0 to 0.8 V
I
IL
C
C
5
5
5
5
i
Output capacitance
o
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
transmit amplifier input
†
PARAMETER
Input current at ANLG IN+, ANLG IN –
TEST CONDITIONS
MIN TYP
MAX
±100
±25
UNIT
nA
Input offset voltage at ANLG IN+, ANLG IN –
Common-mode rejection at ANLG IN +, ANLG IN –
Open-loop voltage amplification at GSX
Open-loop unity-gain bandwidth at GSX
Input resistance at ANLG IN+, ANLG IN –
V = –2.17 V to 2.17 V
I
mV
dB
55
5000
1
MHz
10
MΩ
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
receive filter output
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
mV
Ω
Output offset voltage at PWRO+, PWRO– (single ended)
Output resistance at PWRO+, PWRO–
Relative to ANLG GND
80
1
180
†
6
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
gain and dynamic range, V
(unless otherwise noted)
= 5 V, V
= 5 V, T = 25°C (see Notes 4, 5, and 6)
BB A
CC
PARAMETER
Encoder milliwatt response (transmit gain tolerance)
TEST CONDITIONS
MIN
TYP
MAX
±
UNIT
dBm0
dB
Signal input = 1.064 Vrms for µ-law,
Signal input = 1.068 Vrms for A-law
±
±
Encoder milliwatt response (nominal supplies and temperature)
T
= 0°C to 70°C, Supplies = ± 5%
± 0.08
±
A
Digital milliwatt response (receive tolerance gain) relative to
zero-transmission level point
Signal input per CCITT G.711,
Output signal = 1 kHz
dBm0
dB
Digital milliwatt response variation with temperature and supplies
T
A
= 0°C to 70°C, Supplies = ± 5%
± 0.08
µ-law
2.76
2.79
1
R
R
R
R
= 600 Ω
L
L
L
L
A-law
Zero-transmission-level point, transmit channel (0 dBm0)
µ-law
dBm
dBm
= 900 Ω
= 600 Ω
= 900 Ω
A-law
1.03
5.76
5.79
4
µ-law
A-law
Zero-transmission-level point, receive channel (0 dBm0)
µ-law
A-law
4.03
NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of
the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
5. The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz
sine wave through an ideal encoder.
6. Receive output is measured single ended in the maximum-gain configuration. To set the output amplifier for maximum gain, GSR is
connected to PWRO– and the output is taken at PWRO+. All output levels are (sin x)/x corrected.
gain tracking over recommended ranges of supply voltage and operating free-air temperature,
reference level = –10 dBm0
PARAMETER
TEST CONDITIONS
MIN
MAX
±0.25
±0.5
UNIT
3 ≥ input level ≥ –40 dBm0
–40 > input level ≥ –50 dBm0
–50 > input level ≥ –55 dBm0
3 ≥ input level ≥ –40 dBm0
–40 > input level ≥ –50 dBm0
–50 > input level ≥ –55 dBm0
Transmit gain-tracking error, sinusoidal input
dB
±1.2
±0.25
±0.5
Receive gain-tracking error, sinusoidal input
dB
±1.2
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
noise over recommended ranges of supply voltage and operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
‡
Transmit noise, C-message weighted
ANLG IN+ = ANLG GND,
ANLG IN– = GSX
ANLG IN– = GSX,
1
7
dBrnC0
Transmit noise, C-message weighted with 8-bit
signaling (TCM129C14A and TCM29C14A only)
ANLG IN+ = ANLG GND,
6th frame signaling
13 dBrnC0
Transmit noise, psophometrically weighted‡
ANLG IN+ = ANLG GND,
ANLG IN– = GSX
–82
2
–80 dBm0p
PCM IN = 11111111 (µ-law),
PCM IN = 10101010 (A-law),
Measured at PWRO+
Receive noise, C-message-weighted quiet code
5
dBrnC0
Input to PCM IN is zero code with sign bit
toggled at 1-kHz rate
Receive noise, C-message-weighted sign bit toggled
Receive noise, psophometrically weighted
3
6
dBrnC0
PCM = lowest positive decode level
–81 dBm0p
†
‡
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
This parameter is achieved through the use of patented circuitry and is not recommended for applications in which composite signals on the
transmit side are below –55 dBm0.
power supply rejection ratio and crosstalk attenuation over recommended ranges of supply
voltage and operating free-air temperature
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT
0 ≤ f < 30 kHz
30 ≤ f < 50 kHz
0 ≤ f < 30 kHz
30 ≤ f < 50 kHz
0 ≤ f < 30 kHz
30 ≤ f < 50 kHz
0 ≤ f < 30 kHz
30 ≤ f < 50 kHz
–40
–45
–35
–55
–40
–45
–40
–45
V
supply-voltage rejection ratio,
CC
dB
transmit channel
Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT
V
supply-voltage rejection ratio,
BB
transmit channel
dB
dB
dB
Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PWRO+
V
supply-voltage rejection ratio,
CC
receive channel (single ended)
Idle channel,
Supply signal = 200 mV(peak-to-peak),
Narrow-band f measured at PWRO+
V
supply-voltage rejection ratio,
BB
receive channel (single ended)
ANLG IN+ = 0 dBm0,
f = 1.02 kHz,
PCM IN = lowest decode level,
Measured at PWRO+
Unity gain,
Crosstalk attenuation, transmit to receive (single ended)
75
75
dB
dB
PCM IN = 0 dBm0, f = 1.02 kHz,
Measured at PCM OUT
Crosstalk attenuation, receive to transmit (single ended)
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
BB
CC
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
distortion over recommended ranges of supply voltage and operating free-air temperature
†
PARAMETER
TEST CONDITIONS
0 ≥ ANLG IN+ ≥ –30 dBm0
MIN TYP
MAX
UNIT
36
30
25
36
30
25
Transmit signal-to-distortion ratio, sinusoidal
input (CCITT G.712 – Method 2)
–30 > ANLG IN+ ≥ –40 dBm0
–40 > ANLG IN+ ≥ –45 dBm0
0 ≥ ANLG IN+ ≥ –30 dBm0
–30 > ANLG IN+ ≥ –40 dBm0
–40 > ANLG IN+ ≥ –45 dBm0
AT&T Advisory #64 (3.8),
AT&T Advisory #64 (3.8),
CCITT G.712 (7.1)
dB
Receive signal-to-distortion ratio, sinusoidal
input (CCITT G.712 – Method 2)
dB
Transmit single-frequency distortion products
Receive single-frequency distortion products
Input signal = 0 dBm0
Input signal = 0 dBm0
–46 dBm0
–46 dBm0
–35
CCITT G.712 (7.2)
–49
Intermodulation distortion, end to end spurious
out-of-band signals, end to end
dBm0
–25
CCITT G.712 (6.1)
CCITT G.712 (9)
–40
Fixed-data rate,
Input to ANLG IN+ 1.02 kHz at 0 dBm0
f
= 2.048 MHz,
245
µs
CLKX
Transmit absolute delay time to PCM OUT
f = 500 Hz to 600 Hz
170
95
f = 600 Hz to 1000 Hz
f = 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
Fixed data rate,
Transmit differential envelope delay time
relative to transmit absolute delay time
µs
µs
µs
45
105
Receive absolute delay time to PWRO+
f
= 2.048 MHz,
190
CLKR
Digital input is DMW codes
f = 500 Hz to 600 Hz
45
35
f = 600 Hz to 1000 Hz
f = 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
Receive differential envelope delay time
relative to transmit absolute delay time
85
110
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
transmit filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
TEST CONDITIONS
16.67 Hz
MIN
MAX
–30
–25
–23
UNIT
50 Hz
60 Hz
Input amplifier set for unity gain,
Noninverting maximum gain output,
Input signal at ANLG IN+ is 0 dBm0
200 Hz
–1.8 –0.125
Gain relative to gain at 1.02 kHz
dB
300 Hz to 3 kHz
3.3 kHz
3.4 kHz
4 kHz
–0.15
–0.35
–1
0.15
0.15
–0.1
–14
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
TEST CONDITIONS
Below 200 Hz
MIN
MAX
0.15
0.15
0.15
0.15
–0.1
–14
–30
UNIT
200 Hz
–0.5
–0.15
–0.35
–1
300 Hz to 3 kHz
3.3 kHz
Gain relative to gain at 1.02 kHz
Input signal at PCM IN is 0 dBm0
dB
3.4 kHz
4 kHz
4.6 kHz
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 3 and 4)
MIN NOM
MAX
UNIT
ns
t
Clock period for CLKX, CLKR (2.048-MHz systems)
Rise and fall times for CLKX and CLKR
488
5
c(CLK)
t , t
30
ns
r f
t
Pulse duration for CLKX and CLKR (see Note 7)
220
220
ns
w(CLK)
t
Pulse duration, DCLK (f
= 64 Hz to 2.048 MHz) (see Note 7)
] for CLKX and CLKR
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.
ns
w(DCLK)
DCLK
Clock duty cycle, [t
/t
w(CLK) c(CLK)
45%
50%
55%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
MIN
100
0
MAX
–100
UNIT
ns
t
t
t
Frame-sync delay time
t
c(CLK)
d(FSX)
Setup time before bit 7 falling edge of CLKX (TMC29C14A and TCM129C14A only)
Hold time after bit 8 falling edge of CLKX (TCM29C14A and TCM129C14A only)
ns
su(SIGX)
h(SIGX)
0
ns
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
MIN
100
50
MAX
–100
UNIT
ns
t
t
t
Frame-sync delay time
Receive data setup time
Receive data hold time
t
c(CLK)
d(FSR)
ns
su(PCM IN)
h(PCM IN)
60
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
MIN
140
100
488
MAX
–140
UNIT
ns
t
t
t
Time-slot delay time from DCLKX (see Note 8)
Frame sync delay time
t
d(DCLKX)
d(TSDX)
t
–100
c(CLK)
ns
d(FSX)
Clock period for DCLKX
15620
ns
c(DCLKX)
NOTE 8:
t
minimum requirement overrides the t maximum requirement for 64-kHz operation.
d(TSDX)
FSLX
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MIN
140
100
50
MAX
–140
UNIT
ns
t
t
t
t
t
t
Time-slot delay time from DCLKR (see Note 9)
Frame-sync delay time
t
d(DCLKR)
d(TSDR)
t
–100
c(CLK)
ns
d(FSR)
Receive data setup time
ns
su(PCM IN)
h(PCM IN)
c(DCLKR)
(SER)
Receive data hold time
60
ns
Data clock period
488
0
15620
ns
Time-slot end receive time
ns
NOTE 9:
t
minimum requirement overrides the t maximum requirement for 64-kHz operation.
d(TSDR)
FSLR
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
MIN
488
MAX
UNIT
ns
t
t
t
Transmit frame-sync minimum down time
Receive frame-sync minimum down time
Pulse duration, data clock
FSLX
FSX = TTL high for remainder of frame
1952
ns
FSLR
10
µs
w(DCLK)
switching characteristics
delay time over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate
mode (see Figure 3 and 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)
t
t
C
C
= 0 to 100 pF
= 0 to 100 pF
0
145
ns
pd1
L
L
From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)
0
145
ns
pd2
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)
t
t
C
C
= 0
60
0
215
145
ns
ns
pd3
L
L
From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)
= 0 to 100 pF
pd4
From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)
t
t
C
= 0
60
0
190
2
ns
pd5
L
From rising edge of channel time slot to SIGR update (TCM29C14A and
TCM129C14A only)
µs
pd6
NOTE 10: Timing parameters t
, t
, and t
are referenced to the high-impedance state.
pd5
pd1 pd3
delay time over recommended ranges of operating conditions, variable-data-rate mode (see Note 11 and
Figure 5)
PARAMETER
Delay time from DCLKX
TEST CONDITIONS
MIN
0
MAX
100
50
UNIT
ns
t
t
t
t
pd7
pd8
pd9
pd10
Delay from time-slot enable to PCM OUT
Delay from time-slot disable to PCM OUT
Delay time from FSX
C
= 0 to 100 pF
0
ns
L
0
80
ns
t
= 80 ns
0
140
ns
d(TSDX)
NOTE 11: Timing parameters t
and t
pd9
are referenced to the high-impedance state.
pd8
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
CLKR and CLKX selection requirements for DSP-based applications
CLKX and CLKR must be selected as follows:
CLKR, CLKX
CLKSEL
DEVICE TYPE
(BETWEEN 1 MHz to 3 MHz)
TCM29C13A/14A/16A/17A
TCM129C13A/14A/16A/17A
TCM29C13A/14A
†
= (256) × (frame-sync frequency)
–5 V
0 V
5 V
= (193) × (frame-sync frequency)
= (192) × (frame-sync frequency)
TCM129C13A/14A
TCM29C13A/14A
TCM129C13A/14A
†
CLKSEL is internally set to –5 V for TCM29C16A/1A7 and TCM129C16A/17A e.g., for
frame-sync frequency = 9.6 kHz
CLKR, CLKX
(BETWEEN 1 MHz to 3 MHz)
CLKSEL
DEVICE TYPE
TCM29C13A/14A/16A/17A
TCM129C13A/14A/16A/17A
TCM29C13A/14A
†
= 2.4576 MHz
–5 V
0 V
5 V
= 1.8528 MHz
= 1.8432 MHz
TCM129C13A/14A
TCM29C13A/14A
TCM129C13A/14A
†
CLKSEL is internally set to –5 V for TCM29C16A/1A7 and TCM129C16A/17A.
Corner frequency at 8-kHz frame-sync frequency = 3 kHz, therefore, the corner frequency = (3/8) × (frame-sync
frequency for nonstandard frame sync).
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
0.15 dB
300 Hz
0.15 dB
3000 Hz
0.15 dB
3300 Hz
–0.125 dB
200 Hz
–0.10 dB
3400 Hz
0
0
–0.15 dB
3000 Hz
–0.35 dB
3300 Hz
–1dB
3400 Hz
–0.15 dB
300 Hz
Typical Filter
Transfer Function
–1
–1
–1.8 dB
200 Hz
0
–10
–20
–30
–40
0
–10
–20
–30
–40
–14 dB
4000 Hz
–23 dB
60 Hz
Typical Filter
Transfer Function
–25 dB
50 Hz
–32 dB
4600 Hz
–30 dB
16.67 Hz
–50
–60
–50
–60
10
50
100
1 k
10 k
f – Frequency – Hz
Figure 1. Transmit Filter Transfer Characteristics
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
2
2
1
0
1
0.15 dB
3000 HZ
0.15 dB
200 Hz
0.15 dB
300 Hz
0.15 dB
3300 HZ
–0.10 dB
3400 Hz
0
–0.5 dB
200 Hz
–0.15 dB
3000 Hz
–0.35 dB
3300 Hz
–1dB
3400 Hz
–0.15 dB
300 Hz
–1
–1
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
–14 dB
4000 Hz
–30 dB
4800 Hz
100
1 k
10 k
f – Frequency – Hz
NOTE A: This is a typical transfer function of the receive filter component.
Figure 2. Receive Filter Transfer Characteristics
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot 1
CLKX
1
2
3
4
5
6
7
8
t
d(FSX)
t
r
t
f
t
d(FSX)
FSX
(nonsignaling
frames)
t
w(CLK)
t
c(CLK)
t
d(FSX)
t
FSX
(signaling
frames)
d(FSX)
FRAME SYNCHRONIZATION TIMING
Time Slot N
1
2
3
4
5
6
7
8
CLKX
t
t
t
pd3
pd1
pd2
†
†
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
t
Bit 8
PCM OUT
t
pd4
pd5
TSX
t
h(SIGX)
t
su(SIGX)
Valid
Don’t Care
SIGX
Don’t Care
OUTPUT TIMING
†
Bit 1 = MSB = sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
Figure 3. Transmit Timing (Fixed-Data Rate)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot 1
5
CLKR
t
1
2
3
4
6
7
8
t
r
t
f
t
d(FSR)
t
d(FSR)
w(CLK)
FSR
(nonsignaling
frames)
t
c(CLK)
t
d(FSR)
t
FSR
(signaling
frames)
d(FSR)
FRAME SYNCHRONIZATION TIMING
Time Slot N
CLKR
t
1
2
t
3
4
5
6
7
8
t
pd6
su(PCM IN)
h(PCM IN)
PCM IN
†
†
Bit 1
Bit 2
Valid
Bit 3
Valid
Bit 4
Valid
Bit 5
Valid
Bit 6
Valid
Bit 7
Valid
Bit 8
Valid
Valid
Valid
Valid
SIGR
INPUT TIMING
†
Bit 1 = MSB = sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
Figure 4. Receive Timing (Fixed-Data Rate)
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot
FSX
t
d(TSDX)
1
2
3
4
5
6
7
8
DCLKX
CLKX
t
d(FSX)
t
pd8
t
t
pd9
t
pd7
pd10
†
†
Bit 8
PCM OUT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 5. Transmit Timing (Variable-Data Rate)
FSR
t
d(TSDR)
1
2
3
4
5
6
7
8
DCLKR
CLKR
t
(SER)
t
d(FSR)
t
t
su(PCM IN)
h(PCM IN)
PCM IN
Don’t Care
†
Bit 1
†
Bit 8
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 6. Receive Timing (Variable-Data Rate)
†
Bit 1 = MSB = sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: All timing parameters are referenced to V and V except t
IH IL
and t , which references the high-impedance state.
pd9
pd8
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
system reliability and design considerations
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A, and
TCM129C17A system reliability and design considerations are described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM29CxxA and TCM129CxxA devices are heavily protected against latch-up, it is still
possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more
terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the
negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after
power has been applied but before the ground is connected. This can happen if the device is hot-inserted into
a card with the power applied, or if the device is mounted on a card that has an edge connector, and the card
is hot-inserted into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V — 1N5711 or equivalent), between
each power supply and GND (see Figure 7). If it is possible that a TCM29CxxA- or TCM129CxxA-equipped card
that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that
the ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.
device power-up sequence
Latch-up also can occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply V (most negative voltage).
BB
4. Apply V
(most positive voltage).
CC
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power-down condition.
8. Apply FSX and/or FXR synchronization pulses.
9. Apply signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
V
CC
DGND
V
BB
Figure 7. Diode Configuration for Latch-Up Protection Circuitry
internal sequencing
On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for
approximately four frames (500µs) after power up or application of V . Afterthisdelay, PCMOUT, TSX,
V
BBor CC
and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Valid digital
information, such as on/off hook detection, is available almost immediately, while analog information is available
after some delay.
On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up
or application of V or V . SIGR remains low until it is updated by a signalling frame.
BB
CC
To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately
20 µs after an interruption of CLKX. SIGR is held low approximately 20 µs after an interruption of CLKR. These
interruptions could possibly occur with some kind of fault condition.
power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced 15 mW.
Three standby modes give the user the options of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is
held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the
entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for
power-down and standby procedures.
Table 1. Power-Down and Standby Procedures
TYPICAL POWER
CONSUMPTION
DEVICE STATUS
Power down
PROCEDURE
PDN low
FSX and FSR are low
DIGITAL OUTPUT STATUS
TSX and PCM OUT are in the high-impedance state;
SIGR goes low within 10 µs.
3 mW
TSX and PCM OUT are in the high-impedance state;
SIGR goes low within 300 ms.
Entire device on standby
3 mW
TSX and PCM OUT are placed in the high-impedance
state within 300 ms.
Only transmit on standby
Only receive on standby
FSX is low,
FSR is low,
FSR is high
FSX is high
40 mW
30 mW
SIGR is placed in the high-impedance state within 300 ms.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
fixed-data-rate timing (see Figure 8)
Fixed-data-rate timing is selected by connecting DCLKR to V
and uses master clocks CLKX and CLKR,
BB
frame-synchronizer clocks FSX and FSR, and the output TSX. FSX and FSR are 8-kHz inputs that set the
sampling frequency and distinguish between signaling and nonsignaling frames by their pulse durations. A
frame synchronization pulse one master-clock period long designates a nonsignaling frame, while a
double-length sync pulse enables the signaling function (TCM12914A and TCM29C14A only). Data is
transmitted on PCM OUT on the first eight positive transitions of CLKX following the rising edge of FSX. Data
is received on PCM IN on the first eight falling edges of CLKR following FSR. A digital-to-analog (D/A)
conversion is performed on received digital word, and the resulting analog sample is held on an internal
sample-and-hold capacitor until transferred to the receive filter.
The clock-selection terminal (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM29C13A,
TCM29C14A, TCM129C13A, and TCM129C14A only). The TCM29C13A, TCM29C14A, TCM129C13A, and
TCM129C14Afixed-data-rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz. The
TCM29C16A, TCM29C17A, TCM129C16A, and TCM129C17A fixed-data-rate mode operates at 2.048 MHz
only.
192/193/256
Other
Time Slots
TS1X
TS1X
CLKX
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
192/193/256
Transmit Signal Frame
FSX
B
B
SIGX
8
7
PCM OUT
B
B
B
B
B
B
B
B
B B B B B B
1 2 3 4 5 6
1
2
3
4
5
6
7
8
TSX
Don’t Care
SIGX
Don’t Care
Valid
192/193/256
Other
Time Slots
TS1R
TS1R
CLKR
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
192/193/256
Receive Signal Frame
FSR
SIGR
PCM IN
B
B
B
B
B
B B
6
B
B
B
B
B
B
B
B
B
7 8
1
2
3
4
5
7
8
1
2
3
4
5
6
SIGR
Previous Value
New Value
Figure 8. Signaling Timing (Fixed-Data Rate Only)
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to V . It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization
BB
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 2.048 MHz. Master clocks in the TCM129C13A, TCM129C14A, TCM29C13A, and TCM29C14A are
restricted to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing
mode. The master clock for the TCM129C16A, TCM129C17A, TCM29C16A, and TCM29C17A is restricted to
2.048 MHz.
When the FSX/TSXE is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
ThetransmittedPCMwordisrepeatedinallremainingtimeslotsinthe125-µsframeaslongasDCLKXispulsed
and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than
once per frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the
fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling
frame.
signaling
Only the TCM29C14A provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are independent of each other and are selected by a double-width frame-sync pulse on the
appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for the least
significant bit (LSB) of the encoded PCM word. In a receive signaling frame, the codec decodes the seven most
significant bits in accordance with CCITT G.733 recommendations and outputs the logical state of the LSB on
SIGR until it is updated in the next signaling frame. Timing relationships for signaling operations are shown in
Figure 8. The signaling path is used to transmit digital signaling information such as ring control, rotary dial
pulses, and off-hook and disconnect supervision. The voice path is used to transmit prerecorded messages as
well as the call progress tones: dial tone, ring-back tone, busy tone, and reorder tone.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
analog loopback
A distinctive feature of the TCM29C14A and TCM129C14A is the analog loopback capability. With this feature,
the user can test the line circuit remotely by comparing the signals sent into the receive channel (PCM IN) with
those generated on the transmit channel (PCM OUT). The test is accomplished by sending a control signal that
internally connects the analog input and output ports. When ANLG LOOP is TTL high, the receive output
(PWRO+) is internally connected to ANLG IN+, GSR is internally connected to PWRO–, and ANLG IN– is
internally connected to GSX (see Figure 8).
ANLG LOOP
ANLG IN–
GSX
+
_
Transmit
Voice
PCM OUT
A/D
D/A
Digitized PCM
Loopback
Response
ANLG
IN+
+
_
PWRO+
PWRO–
PCM IN
Digitized PCM
Test Tone
GSR
Figure 9. TCM29C14A and TCM129C14A Analog Loopback Configuration
Due to the difference in the transmit and receive transmission levels, a 0-dBm0 code into PCM IN emerges from
PCM OUT as a 3-dBm0 code, an implicit gain of 3 dB. Because of this, the maximum signal that can be tested
by analog loopback is 0 dBm0.
precision voltage references
Voltage references that determine the gain dynamic range characteristics of the device are generated internally.
No external components are required to provide the voltage references. A difference in subsurface charge
densitybetweentwosuitablyimplantedMOSdevicesisusedtoderiveatemperature-andbias-stablereference
voltage, which is calibrated during the manufacturing process. Separate references are supplied to the transmit
and receive sections, and each is calibrated independently. Each reference value is then further trimmed in the
gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically ±0.04 dB can
be achieved in absolute gain for each half channel, providing the user a significant margin to compensate for
error in other system components.
conversion laws
The TCM29C13A, TCM29C14A, TCM129C13A, and TCM129C14A provide pin-selectable µ-law operation as
specified by CCITT G.711 recommendation. A-law operation is selected when ASEL is connected to V , and
BB
µ-lawoperationisselectedbyconnectingASELtoV orGND. SignalingisnotallowedduringA-lawoperation.
CC
If µ-law operation is selected, SIGX is a TTL-level input that can be used in the fixed-data-rate timing mode to
modify the LSB of the PCM output is signaling frames.
The TCM29C16A and TCM129C16A are µ-law only; the TCM29C17A and TCM129C17A are A-law only.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kΩ in parallel with less than 50 pF. The input signal on ANLG IN+ can be either ac or dc coupled. The input
operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing filter section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.
The pass-band section provides flatness and stop-band attenuation that fulfills the AT&T D3/D4 channel bank
transmission specification and CCITT recommendation G.712. The device specifications meet or exceed digital
class 5 central office switching-systems requirements.
A high-pass section configuration has been chosen to reject low-frequency noise from 50-Hz and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation
at 200 Hz. This feature allows the use of low-cost transformer hybrids without external components.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal
sample-and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor
array. Digital data representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses the
sign-bit-averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from
the input to the encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog
conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold
capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T
D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the
(sin x)/x response of such decoders.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
receive output power amplifiers
A balanced-output amplifier allows maximum flexibility in output configuration. Either of the two outputs can be
used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively, the differential
output directly drives a bridged load. The output stage is capable of driving loads as low as 300-Ω single-ended
to a level of 12 dBm or 600 Ω differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulation of GSR. GSR
is internally connected to an analog gain-setting network. When GSR is connected to PWRO–, the receive level
is maximum. When GSR is connected to PWRO+, the level is minimum. The output transmission level is
adjustedbetween0and –12dBasGSRisadjusted(withanadjustableresistor)betweenPWRO+andPWRO–.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).
APPLICATION INFORMATION
output gain-set design considerations (see Figure 9)
PWRO+ and PWRO– are low-impedance complementary outputs. The voltages at the nodes are:
V
V
V
at PWRO+
at PWRO–
O+
O–
= V
– V
(total differential response)
O–
O
O+
R1 and R2 are a gain-setting resistor network with the center tap connected to the GSR input.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and R sets the total loading.
L
ThetotalcapacitanceattheGSRinputandtheparallelcombinationofR1andR2defineatimeconstantthat
has to be minimized to avoid inaccuracies.
V represents the maximum available digital milliwatt output response (V = 3.006 Vrms).
A
A
V
= A • V
A
OD
where A =
1 + (R1/R2)
4 + (R1/R2)
2
4
3
PWRO+
GSR
TCM29C13A
TCM29C14A
TCM29C16A
TCM29C17A
TCM129C13A
TCM129C14A
TCM129C16A
TCM129C17A
V
O
R1
V
OD
R
L
R2
PWRO–
PCM IN
V
O–
Digital Milliwatt
Sequence Per
CCITT G. 711
Figure 10. Gain-Setting Configuration
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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