PCI7420GHK [ROCHESTER]
400Mbps, FLASH MEMORY DRIVE CONTROLLER, PBGA288, PLASTIC, BGA-288;
| 型号： | PCI7420GHK |
| 厂家： | 
Rochester Electronics |
| 描述： | 400Mbps, FLASH MEMORY DRIVE CONTROLLER, PBGA288, PLASTIC, BGA-288 数据传输 PC 驱动 外围集成电路 驱动器 |
| 文件： | 总8页 (文件大小：916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCI7620/PCI7420
www.ti.com
SLLA252–JULY 2006
Dual Socket CardBus and Smart Card Controller With Integrated 1394a-2000 OHCI
Two-Port PHY/Link-Layer Controller and Dedicated SD/MS-Pro Sockets
FEATURES
•
Full IEEE Std 1394a-2000 support includes:
connection debounce, arbitrated short reset,
multispeed concatenation, arbitration
acceleration, fly-by concatenation, and port
disable/suspend/resume
•
PC Card Standard 8.0 compliant
•
PCI Bus Power Management Interface
Specification 1.1 compliant
•
•
Advanced Configuration and Power Interface
(ACPI) Specification 2.0 compliant
•
Power-down features to conserve energy in
battery-powered applications include:
automatic device power down during
suspend, PCI power management for
link-layer, and inactive ports powered down,
ultralow-power sleep mode
PCI Local Bus Specification Revision 2.3
compliant
•
•
PC 98/99 and PC2001 compliant
Compliant with the PCI Bus Interface
Specification for PCI-to-CardBus Bridges
•
•
Two IEEE Std 1394a-2000 fully compliant
cable ports at 100M bits/s, 200M bits/s, and
400M bits/s
•
Fully compliant with provisions of IEEE Std
1394-1995 for a high-performance serial bus
and IEEE Std 1394a-2000
Cable ports monitor line conditions for active
connection to remote node
•
•
Fully compliant with 1394 Open Host
Controller Interface Specification 1.1
•
•
•
Cable power presence monitoring
1.8-V core logic and 3.3-V I/O cells with
internal voltage regulator to generate 1.8-V
core VCC
Separate cable bias (TPBIAS) for each port
Physical write posting of up to three
outstanding transactions
•
•
•
Universal PCI interfaces compatible with
3.3-V and 5-V PCI signaling environments
•
•
•
•
•
•
•
•
PCI burst transfers and deep FIFOs to
tolerate large host latency
Supports PC Card or CardBus with hot
insertion and removal
External cycle timer control for customized
synchronization
Supports 132-MBps burst transfers to
maximize data throughput on both the PCI
bus and the CardBus
Extended resume signaling for compatibility
with legacy DV components
PHY-Link logic performs system initialization
and arbitration functions
•
•
•
Supports serialized IRQ with PCI interrupts
Programmable multifunction terminals
PHY-Link encode and decode functions
included for data-strobe bit level encoding
Serial ROM interface for loading subsystem
ID and subsystem vendor ID
PHY-Link incoming data resynchronized to
local clock
•
ExCA-compatible registers are mapped in
memory or I/O space
Node power class information signaling for
system power management
•
•
Intel 82365SL–DF register compatible
Supports ring indicate, SUSPEND, and PCI
CCLKRUN protocol and PCI bus Lock (LOCK)
Register bits give software control of
contender bit, power class bits, link active
control bit, and IEEE Std 1394a-2000 features
•
•
Provides VGA/palette memory and I/O, and
subtractive decoding options, LED activity
terminals
•
•
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous
transmit requests
Fully interoperable with FireWire™ and
i.LINK™ implementations of IEEE Std 1394
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Corporation of America.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
PCI7620/PCI7420
www.ti.com
SLLA252–JULY 2006
•
•
•
Register access fail interrupt when the PHY
SCLK is not active
•
•
PME support per 1394 Open Host Controller
Interface Specification
PCI power-management D0, D1, D2, and D3
power states
Advanced submicron, low-power CMOS
technology
Initial bandwidth available and initial
channels available registers
DESCRIPTION
The Texas Instruments PCI7620 device is an integrated dual-socket PC Card controller, Smart Card controller,
IEEE 1394 open HCI host controller, and PHY, Secure Digital (SD)/MultiMediaCard (MMC), Memory Stick
(MS)/MS-Pro controller. This high-performance integrated solution provides the latest in PC Card, Smart Card,
IEEE 1394, SD, MMC, and Memory Stick technology.
The Texas Instruments PCI7420 device is an integrated dual-socket PC Card controller, IEEE 1394 Open HCI
host controller, and PHY, SD/MMC MS/MS-Pro controller. This high-performance integrated solution provides
the latest in PC Card, IEEE 1394, SD, MMC, and Memory Stick technology.
For the remainder of this document, the PCI7x20 device refers to both devices: PCI7620 and PCI7420.
The PCI7620 and PCI7420 are four-function PCI devices compliant with PCI Local Bus Specification, Revision
2.3.
Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard
(Release 8.0). The PCI7x20 device provides features that make it the best choice for bridging between the PCI
bus, PC Cards, and Smart Cards and supports any combination of 16-bit, CardBus PC Cards, or Smart Card
adapter in the socket powered at 5 V or 3.3 V, as required.
There are no PCMCIA card and socket service software changes required to move systems from the existing
CardBus socket controller to the PCI7x20 device. The PCI7x20 device is register compatible with the Intel
82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI7x20
internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for
maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed
performance level with sustained bursting. The PCI7x20 device can be programmed to accept posted writes to
improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external
buffering.
Function 2 of the PCI7x20 device is an integrated IEEE 1394a–2000 open host controller interface (OHCI)
PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus
Power Management Interface Specification, IEEE Std 1394–1995, IEEE Std 1394a–2000, and the 1394 Open
Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the
1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI7x20 device provides two 1394 ports that have
separate cable bias (TPBIAS). The PCI7x20 device also supports the IEEE Std 1394a–2000 power-down
features for battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a–2000, internal control
registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the
PCI7x20 device is compliant with the PCI Bus Power Management Interface Specification. The PCI7x20 device
supports the D0, D1, D2, and D3 power states.
The PCI7x20 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at
132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are
provided to buffer the IEEE 1394 data.
The PCI7x20 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The PCI7x20 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, advanced internal arbitration, and bus-holding buffers.
The PCI7x20 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port
node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission.
2
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PCI7620/PCI7420
www.ti.com
SLLA252–JULY 2006
The PCI7x20 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An
external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop
(PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to
provide the clock signals that control transmission of the outbound encoded strobe and data information. A
49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization
of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC
and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or
S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded
data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe
information is transmitted differentially on the twisted-pair A (TPA) cable pair(s).
Function 3 of the PCI7620 and PCI7420 devices is a dedicated socket that supports SD, MMC, Memory Stick,
and Memory Stick-Pro cards. The Flash Media dedicated socket provides separate terminals for SD/MMC and
Memory Stick signals so that both an SD/MMC card and a Memory Stick/Memory Stick-Pro card can be used
concurrently.
Various implementation specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PCI LOCK, serial and parallel
interrupts, PC Card activity indicator LEDs, and other platform specific signals. PCI-compliant general-purpose
events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant
programming interface is included for the general-purpose inputs and outputs.
The PCI7x20 device is compliant with the latest PCI Bus Power Management Specification, and provides
several low-power modes, which enable the host power system to further reduce power consumption.
The PCI7x20 device also has a three-pin serial interface compatible with both the Texas Instruments TPS2226
and TPS2228 power switches. The TPS2226 or TPS2228 power switch provides power to the two CardBus
sockets on the PCI7x20 device. The power to each dedicated socket is controlled through separate power
control terminals. Each of these power control pins can be connected to an external 3.3-V power switch.
NOTE:
This product is for high-volume PC applications only. For a complete datasheet or
more information contact support@ti.com.
3
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PCI7420GHK
OBSOLETE BGA MI
GHK
288
288
288
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
CROSTA
R
PCI7420ZHK
PCI7620GHK
OBSOLETE BGA MI
ZHK
GHK
CROSTA
R
NRND
BGA MI
CROSTA
R
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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