NCV8501PDW50R2G [ROCHESTER]
5V FIXED POSITIVE LDO REGULATOR, 0.6V DROPOUT, PDSO16, LEAD FREE, SOIC-16;
| 型号： | NCV8501PDW50R2G |
| 厂家： | 
Rochester Electronics |
| 描述： | 5V FIXED POSITIVE LDO REGULATOR, 0.6V DROPOUT, PDSO16, LEAD FREE, SOIC-16 光电二极管 输出元件 调节器 |
| 文件： | 总17页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV8501 Series
Micropower 150 mA LDO
Linear Regulators
with ENABLE, DELAY,
RESET, and Monitor FLAG
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The NCV8501 is a family of precision micropower voltage
regulators. Their output current capability is 150 mA. The family has
output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V.
The output voltage is accurate within 2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature
drawing only 90 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET (with
DELAY), and a FLAG monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending RESET
signal. The use of the FLAG monitor allows the microprocessor to
finish any signal processing before the RESET shuts the
microprocessor down.
The active RESET circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments. The
device has also been optimized for EMC conditions.
SO−8
D SUFFIX
8
CASE 751
1
SOIC 16 LEAD
WIDE BODY
16
EXPOSED PAD
PDW SUFFIX
CASE 751AG
1
MARKING DIAGRAMS
SOW−16
E PAD
SO−8
16
8
1
8501x
ALYW
G
8501x
AWLYYWWG
1
Features
x
= Voltage Ratings as Indicated Below:
A = Adjustable
2 = 2.5 V
3 = 3.3 V
5 = 5.0 V
8 = 8.0 V
• Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V
•
2.0% Output
• Low 90 mA Quiescent Current
• Fixed or Adjustable Output Voltage
• Active RESET
0 = 10 V
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
• ENABLE
• 150 mA Output Current Capability
• Fault Protection
♦ +60 V Peak Transient Voltage
♦ −15 V Reverse Voltage
♦ Short Circuit
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
♦ Thermal Overload
• Early Warning through FLAG/MON Leads
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
January, 2009 − Rev. 29
NCV8501/D
NCV8501 Series
PIN CONNECTIONS, ADJUSTABLE OUTPUT
SO−8
SOW−16 E PAD
1
8
1
16
V
IN
V
OUT
V
ADJ
FLAG
V
NC
NC
GND
NC
MON
ENABLE
NC
V
OUT
NC
NC
NC
NC
ADJ
FLAG
GND
NC
V
IN
NC
MON
ENABLE
PIN CONNECTIONS, FIXED OUTPUT
SO−8
SOW−16 E PAD
1
8
1
16
V
V
OUT
FLAG
RESET
NC
NC
GND
NC
IN
V
MON
ENABLE
DELAY
FLAG
RESET
GND
OUT
NC
NC
NC
NC
NC
V
MON
DELAY
ENABLE
IN
V
BAT
V
IN
V
OUT
V
DD
10 mF
10 mF
NCV8501
R
R
RST
10 k
FLG
10 k
DELAY
MON
C
DELAY
V
ADJ
(Adjustable
Output Only)
ENABLE
FLAG
RESET
I/O
I/O
GND
Figure 1. Application Diagram
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2
NCV8501 Series
MAXIMUM RATINGS*
Rating
Value
−15 to 45
60
Unit
V
V
IN
(dc)
Peak Transient Voltage (46 V Load Dump @ V = 14 V)
V
IN
Operating Voltage
45
V
V
(dc)
−0.3 to 16
−0.3 to 10
V
OUT
Voltage Range (RESET, FLAG)
V
Input Voltage Range (MON)
Input Voltage Range (VAOJ)
−0.3 to 10
−0.3 to 16
V
Input Voltage Range (ENABLE)
−0.3 to 10**
2.0
V
ESD Susceptibility (Human Body Model)
kV
°C
°C
Junction Temperature, T
−40 to +150
−55 to 150
J
Storage Temperature, T
S
Package Thermal Resistance, SO−8:
Junction−to−Case, R
Junction−to−Ambient, R
45
165
°C/W
°C/W
q
JC
q
JA
Package Thermal Resistance, SOW−16 E PAD:
Junction−to−Case, R
Junction−to−Ambient, R
15
56
35
°C/W
°C/W
°C/W
q
JC
q
JA
Junction−to−Pin, R
(Note 1)
q
JP
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 2)
260 Peak
(Note 3)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*During the voltage range which exceeds the maximum tested voltage of V , operation is assured, but not specified. Wider limits may apply.
IN
Thermal dissipation must be observed closely.
**Reference Figure 15 for switched−battery ENABLE application.
1. Measured to pin 16.
2. 150 second maximum above 217°C.
3. −5°C / +0°C allowable conditions.
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3
NCV8501 Series
ELECTRICAL CHARACTERISTICS (I
= 1.0 mA, ENABLE = 5.0 V, −40°C ≤ T ≤ 150°C; V dependent on voltage option
OUT
J
IN
(Note 4); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage
Output Voltage for 2.5 V Option
6.5 V < V < 16 V, 100 mA ≤ I
≤ 150 mA
≤ 150 mA
2.450
2.425
2.5
2.5
2.550
2.575
V
V
IN
OUT
OUT
5.5 V < V < 26 V, 100 mA ≤ I
IN
Output Voltage for 3.3 V Option
Output Voltage for 5.0 V Option
7.3 V < V < 16 V, 100 mA ≤ I
≤ 150 mA
≤ 150 mA
3.234
3.201
3.3
3.3
3.366
3.399
V
V
IN
OUT
OUT
5.5 V < V < 26 V, 100 mA ≤ I
IN
9.0 V < V < 16 V, 100 mA ≤ I
≤ 150 mA
≤ 150 mA
4.90
4.85
5.0
5.0
5.10
5.15
V
V
IN
OUT
OUT
6.0 V < V < 26 V, 100 mA ≤ I
IN
Output Voltage for 8.0 V Option
Output Voltage for 10 V Option
9.0 V < V < 26 V, 100 mA ≤ I
≤ 150 mA
≤ 150 mA
7.76
9.7
8.0
10
8.24
10.3
V
V
IN
OUT
11 V < V < 26 V, 100 mA ≤ I
IN
OUT
Output Voltage for Adjustable Option
V
OUT
= V
(Unity Gain)
ADJ
6.5 V < V < 16 V, 100 mA < I
< 150 mA
< 150 mA
1.254
1.242
1.280
1.280
1.306
1.318
V
V
IN
OUT
5.5 V < V < 26 V, 100 mA < I
IN
OUT
Dropout Voltage (V − V
(5.0 V, 8.0 V, 10 V, and
Adj. > 5.0 V Options Only)
)
I
I
= 150 mA
= 1.0 mA
−
−
400
100
600
150
mV
mV
IN
OUT
OUT
OUT
Load Regulation
V
= 14 V, 5.0 mA ≤ I
≤ 150 mA
−30
5.0
15
30
60
mV
mV
IN
OUT
Line Regulation
[V
(Typ) + 1.0] < V < 26 V, I = 1.0 mA
OUT OUT
−
IN
Quiescent Current, Low Load
2.5 V Option
3.3 V Option
5.0 V Option
8.0 V Option
I
= 100 mA, V = 12 V, MON = V
OUT IN OUT
−
−
−
−
−
−
90
90
90
100
100
50
125
125
125
150
150
75
mA
mA
mA
mA
mA
mA
10 V Option
Adjustable Option
Quiescent Current, Medium Load
All Options
I
= 75 mA, V = 14 V, MON = V
OUT
−
−
−
4.0
12
12
6.0
19
30
mA
mA
mA
OUT
IN
Quiescent Current, High Load
All Options
I
= 150 mA, V = 14 V, MON = V
OUT IN OUT
Quiescent Current, (I )
ENABLE = 0 V, V = 12 V
Q
IN
Sleep Mode
Current Limit
−
151
40
300
190
180
−
−
−
mA
mA
°C
Short Circuit Output Current
Thermal Shutdown
V
= 0 V
OUT
(Guaranteed by Design)
150
Reset Function (RESET)
RESET Threshold for 2.5 V Option
5.5 V ≤ V ≤ 26 V (Note 5)
IN
HIGH (V
)
V
OUT
V
OUT
Increasing
Decreasing
2.28
2.25
2.350
2.300
0.98 × V
V
V
RH
)
OUT
LOW (V
RL
0.97 × V
OUT
RESET Threshold for 3.3 V Option
HIGH (V
5.5 V ≤ V ≤ 26 V (Note 5)
IN
)
V
OUT
V
OUT
Increasing
Decreasing
3.00
2.97
3.102
3.036
0.98 × V
0.97 × V
V
V
RH
OUT
LOW (V
)
RL
OUT
RESET Threshold for 5.0 V Option
HIGH (V
)
V
OUT
V
OUT
Increasing
Decreasing
4.55
4.50
4.70
4.60
0.98 × V
0.97 × V
V
V
RH
OUT
LOW (V
)
RL
OUT
RESET Threshold for 8.0 V Option
HIGH (V
)
V
OUT
V
OUT
Increasing
Decreasing
7.05
7.00
7.52
7.36
0.98 × V
0.97 × V
V
V
RH
OUT
LOW (V
)
RL
OUT
4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.
5. For V ≤ 5.5 V, a RESET = Low may occur with the output in regulation.
IN
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4
NCV8501 Series
ELECTRICAL CHARACTERISTICS (I
= 1.0 mA, ENABLE = 5.0 V, −40°C ≤ T ≤ 150°C; V dependent on voltage option
OUT
J
IN
(Note 4); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Reset Function (RESET)
RESET Threshold for 10 V Option
HIGH (V
)
V
V
Increasing
Decreasing
8.60
8.50
9.40
9.20
0.98 × V
0.97 × V
V
V
RH
)
OUT
OUT
OUT
LOW (V
RL
OUT
Output Voltage
Low (V
)
1.0 V ≤ V
≤ V , R
= 10 k
−
0.1
1.8
−
0.4
2.2
0.1
3.5
−
V
V
RLO
OUT
RL
RESET
DELAY Switching Threshold (V
DELAY Low Voltage
)
DT
−
1.4
−
V
OUT
< RESET Threshold Low(min)
V
DELAY Charge Current
DELAY Discharge Current
DELAY = 1.0 V, V
> V
1.5
5.0
2.5
−
mA
mA
OUT
OUT
RH
DELAY = 1.0 V, V
= 1.5 V
FLAG/Monitor
Monitor Threshold
Hysteresis
Increasing and Decreasing
1.10
20
1.20
50
1.31
100
0.5
V
mV
mA
V
−
Input Current
MON = 2.0 V
−0.5
−
0.1
0.1
Output Saturation Voltage
MON = 0 V, I
= 1.0 mA
0.4
FLAG
Voltage Adjust (Adjustable Output only)
Input Current
ENABLE
V
ADJ
= 1.28 V
−0.5
−
0.5
mA
Input Threshold
Low
High
−
3.0
−
−
0.5
−
V
V
Input Current
ENABLE = 5.0 V
−
1.0
5.0
mA
4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.
5. For V ≤ 5.5 V, a RESET = Low may occur with the output in regulation.
IN
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5
NCV8501 Series
PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT
Package Pin Number
SOW−16
E PAD
SO−8
Pin Symbol
Function
1
2
3
4
7
8
9
V
Input Voltage.
IN
MON
ENABLE
NC
Monitor. Input for early warning comparator. If not needed connect to V
ENABLE control for the IC. A high powers the device up.
No connection.
OUT.
3−6, 10−12,
14, 15
5
6
7
8
13
16
1
GND
Ground. All GND leads must be connected to Ground
Open collector output from early warning comparator.
.
FLAG
V
ADJ
Voltage Adjust. A resistor divider from V
2.0%, 150 mA output.
to this lead sets the output voltage.
OUT
2
V
OUT
PACKAGE PIN DESCRIPTION, FIXED OUTPUT
Package Pin Number
SOW−16
E PAD
SO−8
Pin Symbol
Function
1
2
3
4
5
6
7
8
−
7
8
V
Input Voltage.
IN
MON
ENABLE
DELAY
GND
Monitor. Input for early warning comparator. If not needed connect to V
ENABLE control for the IC. A high powers the device up.
Timing capacitor for RESET function.
OUT.
9
10
13
16
1
Ground. All GND leads must be connected to Ground
.
RESET
FLAG
Active reset (accurate to V
≥ 1.0 V)
OUT
Open collector output from early warning comparator.
2.0%, 150 mA output.
2
V
OUT
3−6, 11, 12,
14, 15
NC
No connection.
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6
NCV8501 Series
TYPICAL PERFORMANCE CHARACTERISTICS
5.01
5.00
4.99
4.98
3.35
V
V
= 3.3 V
= 14 V
= 5.0 mA
OUT
V
V
= 5.0 V
= 14 V
= 5.0 mA
OUT
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
IN
IN
I
OUT
I
OUT
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 2. Output Voltage vs. Temperature
Figure 3. Output Voltage vs. Temperature
1.2
14
12
10
8
V
= 12 V
V
= 12 V
IN
IN
1.0
0.8
0.6
0.4
0.2
0
+125°C
+125°C
+25°C
+25°C
−40°C
6
−40°C
4
2
0
0
5
10
I
15
(mA)
20
25
0
15 30 45 60 75 90 105 120 135 140
(mA)
I
OUT
OUT
Figure 4. Quiescent Current vs. Output Current
Figure 5. Quiescent Current vs. Output Current
7
6
5
4
3
2
1
0
120
T = 25°C
T = 25°C
100
80
60
49
20
0
I
= 100 mA
OUT
I
= 100 mA
OUT
I
I
= 50 mA
= 10 mA
OUT
OUT
6
8
10 12 14 16 18 20 22 24 26
(V)
6
8
10 12 14 16 18 20 22 24 26
(V)
V
V
IN
IN
Figure 6. Quiescent Current vs. Input Voltage
Figure 7. Quiescent Current vs. Input Voltage
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7
NCV8501 Series
TYPICAL PERFORMANCE CHARACTERISTICS
450
400
350
300
250
200
150
100
50
16
14
12
10
V
= 12 V
IN
+125°C
+25°C
−40°C
8
6
4
2
0
V
OUT
= 5.0 V, 8.0 V, or 10 V
0
0
25
50
75
100
125
150
−40 −25 −10
5
20 35 50 65 80 95 110 125
I
(mA)
Temperature (°C)
OUT
Figure 8. Dropout Voltage vs. Output Current
Figure 9. Sleep Mode IQ vs. Temperature
1000
100
10
1000
C
= 10 mF
Unstable Region
Unstable Region
Vout
100
10
C
= 0.1 mF
Vout
10 V
8 V
5 V
2.5 V
3.3 V
1.0
1.0
Stable Region
Stable Region
0.1
0.1
C
= 10 mF
VOUT
0.01
0.01
0
10
20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
0
10 20 30 40 50 60 70 80 90 100 110
OUTPUT CURRENT (mA)
Figure 10. Output Stability with Output
Voltage Change
Figure 11. Output Stability with Output
Capacitor Change
70
60
50
40
I
= 10 mA
out
I
= 80 mA
out
I
= 150 mA
30
20
out
0.1
1.0
10
100
(kHz)
Figure 12. Audio Frequency Power Supply
Rejection Ratio
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8
NCV8501 Series
V
OUT
V
IN
Current Source
(Circuit Bias)
ENABLE
I
BIAS
Current Limit
Sense
+
+
−
I
BIAS
+
V
BG
−
Error Amplifier
V
BG
RESET
+
Fixed Voltage only
1.8 V
−
Thermal
Protection
3.0 mA
V
ADJ
Bandgap
Reference
20 k
Adjustable
Version only
Delay
MON
I
V
BG
BIAS
GND
V
BG
I
BIAS
FLAG
+
−
Figure 13. Block Diagram
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NCV8501 Series
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8501 contains the microprocessor compatible
control function RESET (Figure 14).
The DELAY lead provides source current (typically 2.5 mA)
to the external DELAY capacitor during the following
proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
V
IN
RESET
Threshold
V
OUT
DELAY
RESET
DELAY
Threshold
(V
)
DT
FLAG/Monitor Function
T
T
d
d
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 16). The typical
threshold is 1.20 V on the MON pin.
Figure 14. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V is within 6.0% of the regulated output
OUT
voltage, or when V
drops out of regulation,and is lower
OUT
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
as 1.0 V.
as low
OUT
V
BAT
V
OUT
V
CC
V
IN
mP
ENABLE Function
NCV8501
C
OUT
The part stays in a low I sleep mode when the ENABLE
I/O
Q
MON
FLAG
pin is held low. The part has an internal pull down if the pin
is left floating. This is intended for failure modes only. An
external connection (active pulldown, resistor, or switch) for
normal operation is recommended.
R
RESET
ADJ
RESET
GND
DELAY
The integrity of the ENABLE pin allows it to be tied
directly to the battery line through an external resistor. It will
withstand load dump potentials in this configuration.
Figure 16. FLAG/Monitor Function
Voltage Adjust
Figure 17 shows the device setup for a user configurable
output voltage. The feedback to the V pin is taken from
V
BAT
V
OUT
V
IN
ADJ
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.28 V
typical).
NCV8501
10 k
ENABLE
GND
≈5.0 V
V
OUT
C
OUT
15 k
NCV8501
Figure 15. ENABLE Function
V
ADJ
1.28 V
5.1 k
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
Figure 17. Adjustable Output Voltage
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10
NCV8501 Series
APPLICATION NOTES
V
IN
V
OUT
C
0.1 mF
*
IN
C
10 mF
**
NCV8501
OUT
R
NCV8501
RST
MJD31C
V
IN
V
OUT
RESET
5.0 V
>1 Amp
V
ADJ
R1
294 k
C2
0.1 mF
V
BAT
C1
47 mF
*C required if regulator is located far from the power supply filter
IN
R2
100 k
**C
required for stability. Capacitor must operate at minimum
temperature expected
OUT
Figure 20. Test and Application Circuit Showing
Output Compensation
Figure 18. Additional Output Current
Adding Capability
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
Figure 18 shows how the adjustable version of parts can
be used with an external pass transistor for additional current
capability. The setup as shown will provide greater than 1
Amp of output current.
ƪ
C
ƫ
(V * Reset Delay Low Voltage)
DELAY dt
t
+
DELAY
Delay Charge Current
FLAG MONITOR
Figure 19 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 16. As the output voltage
Example:
Using C
= 33 nF.
DELAY
Assume reset Delay Low Voltage = 0.
Use the typical value for V = 1.8 V.
falls (V ), the Monitor threshold is crossed. This causes
OUT
dt
the voltage on the FLAG output to go low sending a warning
signal to the microprocessor that a RESET signal may occur
Use the typical value for Delay Charge Current = 2.5 mA.
ƪ
ƫ
in a short period of time. T
is the time the
33 nF(1.8 * 0)
2.5 mA
WARNING
t
+
+ 23.8 ms
DELAY
microprocessor has to complete the function it is currently
working on and get ready for the RESET shutdown signal.
STABILITY CONSIDERATIONS
V
OUT
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints.
MON
The value for the output capacitor C
should work for most applications, however it is not
necessarily the optimized solution.
shown in Figure 20
OUT
FLAG Monitor
Ref. Voltage
RESET
FLAG
T
WARNING
Figure 19. FLAG Monitor Circuit Waveform
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11
NCV8501 Series
UNDERSTANDING THE NCV8501 ENABLE PIN
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 22) is:
INPUT CURRENT
VCC
D1
P
+ [V
* V
]I
OUT(min) OUT(max)
D(max)
IN(max)
) V
R2
(eq. 1)
1.2M
I
IN(max) Q
~3.85V
N1
where:
D2
P1
D3
D4
D5
D6
V
V
I
is the maximum input voltage,
IN(max)
OUT(min)
OUT(max)
R1
ENABLE
is the minimum output voltage,
is the maximum output current for the
Internal
power
rail
20K
application, and
I
I
is the quiescent current the regulator consumes at
.
Q
Internal
reference
Z1 11V Z2
7V
OUT(max)
5μA
Once the value of P
permissible value of R
is known, the maximum
D(max)
Z3 1.25V
(max)
can be calculated:
GND
qJA
T
150C *
A
(eq. 2)
R
+
QJA
P
Figure 21. NCV8501 Enable Function Equivalent
Circuit
D
The value of R
can then be compared with those in the
qJA
Z1, R1, and Z2 provide ESD and overvoltage protection.
Note that, for ENABLE pin voltages in excess of 10 V, an
external series resistor is required to limit the current into
Z1.
For ENABLE pin voltages less than +7 V, the 5 mA
(maximum value) current source dominates the input
current, as the opposing P1 base current is negligible by
comparison.
package section of the data sheet. Those packages with
’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
R
qJA
I
I
IN
OUT
For ENABLE pin voltages between +7 V and +11 V, the
input current is given by:
SMART
REGULATOR®
V
IN
V
OUT
5 mA + ((V
− 7) / 20 kW)
ENABLE
Control
For ENABLE pin voltages in excess of 10 V (Z1
breakover voltage can be as low as 10 V), the input current
is dominated by the external series resistor. For the case
}
Features
I
Q
where V
= 12 V; R
= 10 kW, the input current can
ENABLE
EXT
be up to (2 V/10 kW), = 200 mA.
Figure 22. Single Output Regulator with Key
Performance Parameters Labeled
The ENABLE threshold is that voltage required to
achieve ~3.85 V at the base of N1, or approximately (3.85 V
− 2 Vbe). At +20°C, this threshold is ~2.55 V. At −40°C, it
can be as high as 3 V.
100
If the value of R
is increased to ~200 kW, to reduce
EXT
90
80
70
60
ENABLE input current, then the worst−case drop across
must be added to 3 V to determine the effective
R
EXT
maximum ENABLE threshold. At V
need to consider the 5 mA current sink.
Max effective threshold = 3 V + (5 mA * 220 kW)
< 7 V, we only
ENABLE
= 3 V + 1.1 V
= 4.1 V
50
40
0
200
400
Copper Area (mm )
600
800
2
Figure 23. 16 Lead SOW (Exposed Pad), qJA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625, G−10/R−4
http://onsemi.com
12
NCV8501 Series
HEATSINKS
where:
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
R
qJC
R
qCS
R
qSA
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
R
qJA
appears in the package section of the data sheet. Like
qJC
R
, it too is a function of package type. R
and R
are
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers.
determine the value of R
:
qJA
(eq. 3)
R
+ R
) R
) R
qCS qSA
qJA
qJC
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13
NCV8501 Series
ORDERING INFORMATION
Device
Output Voltage
Package
Shipping†
NCV8501DADJG
SO−8
(Pb−Free)
Adjustable
98 Units/Rail
NCV8501DADJR2G
NCV8501PDWADJG
NCV8501PDWADJR2G
NCV8501D25G
SO−8
Adjustable
Adjustable
Adjustable
2.5 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
98 Units/Rail
SO−8
(Pb−Free)
NCV8501D25R2G
NCV8501PDW25G
NCV8501PDW25R2G
NCV8501D33G
SO−8
2.5 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
2.5 V
SOW−16 Exposed Pad
(Pb−Free)
2.5 V
1000 Tape & Reel
98 Units/Rail
SO−8
(Pb−Free)
3.3 V
NCV8501D33R2G
NCV8501PDW33G
NCV8501PDW33R2G
NCV8501D50G
SO−8
3.3 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
3.3 V
SOW−16 Exposed Pad
(Pb−Free)
3.3 V
1000 Tape & Reel
98 Units/Rail
SO−8
(Pb−Free)
5.0 V
NCV8501D50R2G
NCV8501PDW50G
NCV8501PDW50R2G
NCV8501D80G
SO−8
5.0 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
5.0 V
SOW−16 Exposed Pad
(Pb−Free)
5.0 V
1000 Tape & Reel
98 Units/Rail
SO−8
(Pb−Free)
8.0 V
NCV8501D80R2G
NCV8501PDW80G
NCV8501PDW80R2G
NCV8501D100G
SO−8
8.0 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
8.0 V
SOW−16 Exposed Pad
(Pb−Free)
8.0 V
1000 Tape & Reel
98 Units/Rail
SO−8
(Pb−free)
10 V
NCV8501D100R2G
NCV8501PDW100G
NCV8501PDW100R2G
SO−8
10 V
2500 Tape & Reel
47 Units/Rail
(Pb−Free)
SOW−16 Exposed Pad
(Pb−Free)
10 V
SOW−16 Exposed Pad
(Pb−Free)
10 V
1000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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14
NCV8501 Series
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
NCV8501 Series
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD
PDW SUFFIX
CASE 751AG−01
ISSUE A
−U−
A
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
16
1
9
P
B
M
M
W
0.25 (0.010)
R x 45
_
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
−W−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
G
14 PL
PIN 1 I.D.
DETAIL E
TOP SIDE
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.45
7.60
2.65
0.49
0.90
MAX
0.411
0.299
0.104
0.019
0.035
C
A
B
C
D
F
10.15
7.40
2.35
0.35
0.50
0.400
0.292
0.093
0.014
0.020
F
−T−
0.10 (0.004)
T
SEATING
K
D16 PL
0.25 (0.010)
H
PLANE
G
H
J
1.27 BSC
0.050 BSC
M
S
S
T
U
W
J
3.45
0.25
0.00
4.72
0
3.66
0.32
0.10
4.93
7
0.136
0.010
0.000
0.186
0
0.144
0.012
0.004
0.194
7
DETAIL E
K
L
M
P
R
_
_
_
_
SOLDERING FOOTPRINT*
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
1
8
9
EXPOSED PAD
0.350
Exposed
Pad
L
0.175
0.050
16
BACK SIDE
C
L
0.188
0.200
0.376
C
L
0.074
0.024
0.150
DIMENSIONS: INCHES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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