MT58L128L32P1T-10_技术文档

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

4Mb SYNCBURST^™

SRAM

MT58L256L18P1, MT58L128L32P1,

MT58L128L36P1; MT58L256V18P1,

MT58L128V32P1, MT58L128V36P1

3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle

Deselect

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V^DD

1

100-PINTQFP

)

• Separate +3.3V or +2.5V isolated output buffer

supply (V^DDQ)

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium^®BSRAM-compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion

and address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 165-pin FBGA package

2

165-BALLFBGA

• 100-pin TQFP package

• Low capacitive bus loading

• x18, x32, and x36 versions available

OPTIONS

MARKING

• Timing (Access/Cycle/MHz)

2.6ns/4.4ns/225 MHz

2.8ns/5ns/200 MHz

3.5ns/6ns/166 MHz

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

-4.4

-5

-6

-7.5

-10

NOTE: 1. JEDEC-standardMS-026BHA(LQFP).

2. The 165-ball FBGA is not recommended for new

designs in the 4Mb density.

• Configurations

3.3V I/O

256K x 18

128K x 32

128K x 36

2.5V I/O

MT58L256L18P1

MT58L128L32P1

MT58L128L36P1

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://www.micron.com/support/index.html. The 165-ball

FBGA is not recommended for new designs in the 4Mb density.

** Industrial temperature range offered in specific speed grades and

configurations. Contact factory for more information.

256K x 18

128K x 32

128K x 36

MT58L256V18P1

MT58L128V32P1

MT58L128V36P1

GENERALDESCRIPTION

• Packages

The Micron^®SyncBurst^™SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

100-pin TQFP

165-pin FBGA

T

F*

• Operating Temperature Range

Commercial (0°C to +70°C)

Micron’s 4Mb SyncBurst SRAMs integrate a

256K x 18, 128K x 32, or 128K x 36 SRAM core with ad-

vanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

None

IT

Industrial (-40°C to +85°C)**

Part Number Example:

MT58L256L18P1T-6

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

FUNCTIONALBLOCKDIAGRAM

256K x 18

18

16

18

2

ADDRESS

REGISTER

SA0, SA1, SA

MODE

SA0, SA1

Q1

SA1'

ADV#

CLK

BINARY

COUNTER AND

LOGIC

SA0'

CLR

Q0

ADSC#

ADSP#

BYTE “b”

WRITE DRIVER

BYTE “b”

WRITE REGISTER

9

OUTPUT

BUFFERS

BWb#

256K x 9 x 2

MEMORY

ARRAY

DQs

DQPa

DQPb

OUTPUT

REGISTERS

SENSE

AMPS

18

BYTE “a”

WRITE DRIVER

E

BYTE “a”

WRITE REGISTER

BWa#

BWE#

INPUT

REGISTERS

GW#

18

ENABLE

REGISTER

CE#

CE2

PIPELINED

ENABLE

CE2#

OE#

2

FUNCTIONALBLOCKDIAGRAM

128K x 32/36

17

15

17

ADDRESS

REGISTER

SA0, SA1, SA

MODE

SA0, SA1

SA1'

Q1

BINARY

COUNTER

ADV#

CLK

SA0'

CLR

Q0

ADSC#

ADSP#

BYTE “d”

WRITE DRIVER

BYTE “d”

WRITE REGISTER

9

BWd#

BWc#

128K x 8 x 4

(x32)

BYTE “c”

WRITE DRIVER

BYTE “c”

WRITE REGISTER

DQs

DQPa

OUTPUT

BUFFERS

OUTPUT

REGISTERS

128K x 9 x 4

(x36)

SENSE

AMPS

36

E

BYTE “b”

WRITE DRIVER

MEMORY

ARRAY

BYTE “b”

WRITE REGISTER

9

DQPd

BWb#

BYTE “a”

WRITE DRIVER

BYTE “a”

WRITE REGISTER

BWa#

BWE#

INPUT

REGISTERS

36

GW#

CE#

CE2

ENABLE

REGISTER

PIPELINED

ENABLE

CE2#

OE#

4

NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams

for detailed information.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

2

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

GENERALDESCRIPTION(continued)

(CE#), two additional chip enables for easy depth ex-

pansion (CE2, CE2#), burst control inputs (ADSC#,

ADSP#, ADV#), byte write enables (BWx#) and global

write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is

also a burst mode input (MODE) that selects between

interleaved and linear burst modes. The data-out (Q),

enabled by OE#, is also asynchronous. WRITE cycles

can be from one to two bytes wide (x18) or from one to

four bytes wide (x32/x36), as controlled by the write

control inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) inputs. Subsequent burst addresses can be

internally generated as controlled by the burst advance

input (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls DQb

pins and DQPb. During WRITE cycles on the x32 and

x36 devices, BWa# controls DQa pins and DQPa; BWb#

controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. GW#

LOW causes all bytes to be written. Parity bits are only

available on the x18 and x36 versions.

This device incorporates a single-cycle deselect fea-

ture during READ cycles. If the device is immediately

deselected after a READ cycle, the output bus goes to a

t

High-Z state KQHZ nanoseconds after the rising edge

of clock.

Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V

V^DDpower supply, and all inputs and outputs are TTL-

compatible. Users can choose either a 3.3V or 2.5V I/O

version. The device is ideally suited for Pentium and

PowerPC pipelined systems and systems that benefit

from a very wide, high-speed data bus. The device is

also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-

wide applications.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

3

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFP PIN ASSIGNMENT TABLE

PIN #

1

2

3

4

5

6

7

8

x18

NC

x32/x36

NC/DQPc*

DQc

PIN #

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

x18

x32/x36

VSS

VDDQ

DQd

NC/DQPd*

MODE

PIN #

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

x18

NC

x32/x36

NC/DQPa*

DQa

PIN #

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

x18

x32/x36

VSS

VDDQ

NC

DQc

NC

DQa

NC

SA

DQb

NC/DQPb*

SA

ADV#

ADSP#

ADSC#

OE#

BWE#

GW#

CLK

VSS

VDD

CE2#

BWa#

BWb#

VDDQ

VSS

VDDQ

VSS

NC

DQb

DQc

NC

DQa

SA

DQa

VSS

VDDQ

DQa

ZZ

VDD

NC

VSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VSS

VDDQ

SA

SA1

SA0

DNU

VSS

VDD

NF**

SA

DQb

DQc

VDD

NC

VSS

DQb

DQd

DQa

DQb

VDDQ

VSS

SA

VDDQ

VSS

NC

BWc#

BWd#

DQb

DQPb

NC

DQd

DQa

DQPa

NC

DQb

CE2

CE#

SA

*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

4

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

PINASSIGNMENT(TOPVIEW)

100-PINTQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

ADV#

ADSP#

ADSC#

OE#

SA

BWE#

GW#

CLK

SA

NF**

V

SS

DD

V

DD

SS

V

x18

CE2#

BWa#

BWb#

NC

DNU

SA0

SA1

SA

NC

CE2

CE#

SA

100

MODE

1

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

ADV#

ADSP#

ADSC#

OE#

SA

BWE#

GW#

CLK

SA

NF**

V

SS

DD

V

DD

SS

V

x32/x36

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

SA

CE#

SA

100

MODE

1

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

5

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFPPINDESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

37

36

37

36

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered and

must meet the setup and hold times around the rising edge of

CLK.

32–35, 44–50, 32–35, 44–50,

80–82, 99,

100

81, 82, 99,

100

93

94

–

93

94

95

96

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb. For the x32 and x36 versions, BWa# controls DQa pins and

DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. Parity is only

available on the x18 and x36 versions.

–

87

88

89

87

88

89

BWE#

GW#

CLK

Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

Input Clock: This signal registers the address, data, chip enable, byte write

enables and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock’s rising

edge.

98

92

97

98

92

97

CE#

CE2#

CE2

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

86

83

86

83

OE#

Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

ADV#

Input Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on this pin effectively causes wait

states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge

of the first clock after an ADSP# cycle is initiated.

84

ADSP#

Input Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

(continued on next page)

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

6

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFPPINDESCRIPTIONS(continued)

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

85

ADSC#

Input Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to

be registered. A READ or WRITE is performed using the new

address if CE# is LOW. ADSC# is also used to place the chip into

power-down state when CE# is HIGH.

31

64

31

64

MODE

ZZ

Input Mode: This input selects the burst sequence. A LOW on this pin

selects “linear burst.” NC or HIGH on this pin selects “interleaved

burst.” Do not alter input state while device is operating.

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in

the memory array is retained. When ZZ is active, all other inputs

are ignored.

(a) 58, 59,

62, 63, 68, 69, 56–59, 62, 63

72, 73

(b) 8, 9, 12,

13, 18, 19, 22, 72–75, 78, 79

(a) 52, 53,

DQa

DQb

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte

Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa

pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is

DQd pins. Input data must meet setup and hold times around

the rising edge of CLK.

(b) 68, 69

23

(c) 2, 3, 6-9,

12, 13

(d) 18, 19,

22–25, 28, 29

DQc

DQd

74

24

–

51

80

1

NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are

NC/DQPb

NC/DQPc

NC/DQPd

I/O

No Connect (NC). On the x18 version, Byte “a” parity is DQPa;

Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is

DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d”

parity is DQPd.

–

30

14, 15, 41, 65, 14, 15, 41, 65,

91 91

V^DD

VDDQ

V^SS

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4, 11, 20, 27, 4, 11, 20, 27,

54, 61, 70, 77 54, 61, 70, 77

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics

and Operating Conditions for range.

5, 10, 17, 21, 5, 10, 17, 21,

26, 40, 55, 60, 26, 40, 55, 60,

67, 71, 76, 90 67, 71, 76, 90

Supply Ground: GND.

38, 39

DNU

NC

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1–3, 6, 7, 16,

25, 28–30,

51–53, 56, 57,

66, 75, 78, 79,

95, 96

16, 66

No Connect: These signals are not internally connected and

may be connected to ground to improve package heat

dissipation.

42, 43

NF

–

No Function: These pins are internally connected to the die and

have the capacitance of input pins. It is allowable to leave these

pins unconnected or driven by signals. Reserved for address

expansion; pin 43 becomes an SA at 8Mb density and pin 42

becomes an SA at 16Mb density.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

7

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

PINLAYOUT(TOPVIEW)

165-PINFBGA

x18

x32/x36

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

NC

SA

CE# BWb#

NC

CE2# BWE# ADSC# ADV#

SA

NC

SA

CE# BWc# BWb# CE2# BWE# ADSC# ADV#

SA

NC

CE2

NC

BWa# CLK

GW# OE# (G#) ADSP# SA

CE2 BWd# BWa# CLK

GW# OE# (G#) ADSP# SA

NC

V

DD

Q

V

SS

VSS

V

SS

V

SS

V

SS

V

DD

Q

NC

DQPa

DQa

ZZ

NC/DQPc* NC

V

DD

Q

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

Q

NC NC/DQPb*

DQb DQb

DQb

V

Q

VDD

DQc

VDD

NC

F

NC

G

H

J

G

H

J

G

H

J

G

H

J

NC

V

DD

DQb

DQPb

NC

VSS

NC

VDD

VSS

NC

ZZ

NC

V

DD

Q

V

DD

Q

DQa

NC

DQd DQd

NC/DQPd* NC

V

DD

Q

V

DD

Q

DQa

K

L

K

L

K

L

K

L

V

Q

V

Q

NC

V

Q

V

Q

NC

M

N

P

M

N

P

M

N

P

M

N

P

NC

V

SS

NC

SA1

SA0

VSS

NC

V

SS

NC

SA1

SA0

VSS

NC NC/DQPa*

SA

DNU

SA

NC

SA

DNU

SA

NC

SA

R

MODE NC

(LBO#)

SA

MODE NC

(LBO#)

TOP VIEW

*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

NOTE: 1. Pins 11P, and 6N reserved for address pin expansion; 8Mb, and 16Mb respectively.

2. The 165-ball FBGA is not recommended for new designs in the 4Mb density.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

8

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

FBGAPINDESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

6R

6P

2A, 2B, 3P,

3R, 4P, 4R,

6R

6P

2A, 2B, 3P,

3R, 4P, 4R,

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered and

must meet the setup and hold times around the rising edge of

CLK.

8P, 8R, 9P, 9R, 8P, 8R, 9P,

10A, 10B, 10P, 9R, 10A, 10B,

10R, 11A, 11R 10P, 10R, 11R

5B

4A

–

5B

5A

4A

4B

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For

the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#

controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#

controls DQds and DQPd. Parity is only available on the x18 and x36

versions.

–

7A

7B

6B

7A

7B

6B

BWE#

GW#

CLK

Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

Input Clock: This signal registers the address, data, chip enable, byte write

enables, and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock’s rising

edge.

3A

6A

3A

6A

CE#

CE2#

ZZ

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

11H

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

3B

CE2

Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

8B

9A

8B

9A

OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

ADV#

Input Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on ADV# effectively causes wait

states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge

of the first clock after an ADSP# cycle is initiated.

(continued on next page)

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

9B

ADSP#

Input Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

8A

1R

8A

1R

ADSC#

Input Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

MODE

(LB0#)

Input Mode: This input selects the burst sequence. A LOW on this input

selects “linear burst.” NC or HIGH on this input selects “interleaved

burst.” Do not alter input state while device is operating.

(a) 10J, 10K, (a) 10J, 10K,

10L, 10M, 11D, 10L, 10M, 11J,

11E, 11F, 11G 11K, 11L, 11M

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;

Output Byte “b” is associated with DQbs. For the x32 and x36 versions,

Byte “a” is associated with DQas; Byte “b” is associated with

DQbs; Byte “c” is associated with DQcs; Byte “d” is associated

with DQds. Input data must meet setup and hold times around

the rising edge of CLK.

(b) 1J, 1K,

(b) 10D, 10E,

1L, 1M, 2D, 10F, 10G, 11D,

2E, 2F, 2G

11E, 11F, 11G

(c) 1D, 1E,

1F, 1G, 2D,

2E, 2F, 2G

(d) 1J, 1K, 1L,

1M, 2J, 2K,

2L, 2M

11C

1N

–

11N

11C

1C

NC/DQPa

NC/DQPb

NC/DQPc

NC/DQPd

NC/ No Connect/Parity Data I/Os: On the x32 version, these are No

I/O

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;

Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is

DQPd.

–

1N

1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

VDDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics

and Operating Conditions for range.

(continued on next page)

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C,

VSS

Supply Ground: GND.

5D, 5E 5F,

5G, 5H, 5J,

5K, 5L, 5M,

5D, 5E 5F,

5G, 5H, 5J,

5K, 5L, 5M,

6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,

6G, 6H, 6J,

6K, 6L, 6M,

7C, 7D, 7E,

7F, 7G, 7H,

7J, 7K, 7L,

6G, 6H, 6J,

6K, 6L, 6M,

7C, 7D, 7E,

7F, 7G, 7H,

7J, 7K, 7L,

7M, 7N, 8C, 8N 7M, 7N, 8C, 8N

5P, 5R, 7P, 7R 5P, 5R, 7P, 7R

DNU

NC

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1A, 1B, 1C,

1D, 1E, 1F,

1G, 1P, 2C,

2J, 2K,

1A, 1B, 1P,

2C, 2N,

2P, 2R, 3H,

5N, 6N,

No Connect: These signals are not internally connected and

may be connected to ground to improve package heat

dissipation. Pins 11P, and 6N reserved for address pin

expansion; 8Mb, and 16Mb respectively.

2L, 2M, 2N,

2P, 2R, 3H,

4B, 5A, 5N,

6N, 9H, 10C,

10D, 10E, 10F,

10G, 10H,

10N, 11B,

11J, 11K,

9H, 10C,

10H, 10N,

11A, 11B,

11P

11L, 11M,

11N, 11P

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)

FUNCTION

READ

GW#

H

BWE#

BWa#

BWb#

H

L

X

H

L

X

H

L

READ

H

WRITE Byte “a”

WRITE Byte “b”

WRITE All Bytes

H

L

H

L

H

L

H

L

X

PARTIALTRUTHTABLEFORWRITECOMMANDS(x32/x36)

FUNCTION

READ

GW#

BWE#

BWa#

BWb#

BWc#

BWd#

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

READ

WRITE Byte “a”

WRITE All Bytes

L

X

NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TRUTHTABLE

OPERATION

ADDRESS

USED

CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#

CLK

DQ

DESELECT Cycle, Power-Down None

H

L

X

H

X

H

X

L

X

L

H

L

X

L

X

L

X

L

X

L

X

L

L-H High-Z

L

X

L

H

X

L

X

H

X

L

SNOOZE MODE, Power-Down

READ Cycle, Begin Burst

None

External

L

X

L

X

High-Z

Q

L-H

READ Cycle, Begin Burst

L

H

X

L

L-H High-Z

WRITE Cycle, Begin Burst

READ Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

L-H

D

Q

L

H

L

READ Cycle, Begin Burst

L

H

L

L-H High-Z

L-H

L-H High-Z

L-H

L-H High-Z

READ Cycle, Continue Burst

WRITE Cycle, Continue Burst

READ Cycle, Suspend Burst

WRITE Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

Q

H

L

Q

H

X

L

L-H

D

Q

L

Current

H

L

H

L

L-H High-Z

L-H

L-H High-Z

Q

H

X

L-H

D

L

NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.

2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or

GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.

3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s

and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.

DQPc and DQPd are only available on the x36 version.

4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH

throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing

diagram for clarification.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Maximum junction temperature depends upon

package type, cycle time, loading, ambient tempera-

ture and airflow. See Micron Technical Note TN-05-14

for more information.

ABSOLUTEMAXIMUMRATINGS*

Voltage on VDD Supply

Relative to VSS .................................... -0.5V to +4.6V

Voltage on V^DDQ Supply

Relative to V^SS.................................... -0.5V to +4.6V

V^IN-0.5V to VDDQ + 0.5V

Storage Temperature (plastic) ........... -55°C to +150°C

Junction Temperature** ..................................... +150°C

Short Circuit Output Current.............................. 100mA

3.3VI/ODCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS

(0°C ≤ T_A≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

2.0

MAX

VDD + 0.3

0.8

UNITS

V

NOTES

1, 2

3

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

VIH

VIL

ILI

-0.3

-1.0

V

0V ≤ VIN ≤ VDD

Output(s) disabled,

1.0

µA

ILO

1.0

0V ≤ VIN ≤ VDD

Output High Voltage

Output Low Voltage

Supply Voltage

IOH = -4.0mA

VOH

VOL

2.4

–

V

1, 4

1

IOL = 8.0mA

0.4

3.6

VDD

3.135

Isolated Output Buffer Supply

VDDQ

1, 5

NOTE: 1. All voltages referenced to VSS (GND).

t

2. Overshoot:

VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA

t

Undershoot: V^IL≥ -0.7V for t ≤ KC/2 for I ≤ 20mA

Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = 10µA.

4. The load used for V^OH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC

values. AC I/O curves are available upon request.

5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFP CAPACITANCE

DESCRIPTION

CONDITIONS

T_A= 25°C; f = 1 MHz;

V^DD= 3.3V

SYMBOL

TYP

3

MAX

4

UNITS

pF

NOTES

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

CI

CO

CA

CCK

1

4

5

pF

3

3.5

pF

3

pF

FBGACAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL TYP

MAX

UNITS NOTES

Address/Control Input Capacitance

Output Capacitance (Q)

Clock Capacitance

CI

CO

2.5

4

3.5

5

pF

1, 2

T_A= 25°C; f = 1 MHz

CCK

2.5

3.5

NOTE: 1. This parameter is sampled.

2. Preliminary package data.

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MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

2.5VI/ODCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS

(0°C ≤ T_A≤ +70°C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Data bus (DQx)

Inputs

VIHQ

VIH

1.7

VDDQ + 0.3

VDD + 0.3

V

1, 2

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

VIL

ILI

-0.3

-1.0

0.7

1.0

V

1, 2

3

0V ≤ VIN ≤ VDD

µA

Output(s) disabled,

ILO

0V ≤ VIN ≤ VDDQ (DQx)

Output High Voltage

Output Low Voltage

IOH = -2.0mA

IOH = -1.0mA

VOH

1.7

2.0

–

V

1, 4

IOL = 2.0mA

IOL = 1.0mA

VOL

–

0.7

0.4

V

1, 4

Supply Voltage

VDD

3.135

2.375

3.6

2.9

V

1

Isolated Output Buffer Supply

VDDQ

NOTE: 1. All voltages referenced to VSS (GND).

t

2. Overshoot:

VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA

Power-up: V^IH≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms

3. MODE has an internal pull-up, and input leakage = 10µA.

4. The load used for V^OH, VOL testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC

values. AC I/O curves are available upon request.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFPTHERMALRESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ_JA

46

°C/W

1

Thermal Resistance

(Junction to Top of Case)

θ_JC

2.8

°C/W

1

FBGATHERMALRESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

(Airflow of 1m/s)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ_JA

40

°C/W

1, 2

Junction to Case (Top)

θ_JC

θ_JB

9

°C/W

1, 2

Junction to Pins

(Bottom)

17

NOTE: 1. This parameter is sampled.

2. Preliminary package data.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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PIPELINED, SCD SYNCBURST SRAM

IDD OPERATINGCONDITIONSANDMAXIMUMLIMITS

(Note 1) (0°C ≤ T_A≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)

M A X

DESCRIPTION

CONDITIONS

SYMBOL TYP -4.4 -5 -6 -7.5 -10 UNITS NOTES

Power Supply

Current:

Operating

Device selected; All inputs ≤ VIL

t

or ≥ VIH; Cycle time ≥ KC (MIN);

I

DD

225 575 525 475 375 300 mA

2, 3, 4

VDD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; V^DD= MAX;

ADSC#, ADSP#, GW#, BWx#, ADV# ≥

IDD

1

55 130 120 110 90 85

0.4 10 10 10 10 10

mA

V

IH; All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Clock Running

Device deselected; V^DD= MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDDQ - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

mA

3, 4

Device deselected; V^DD= MAX;

All inputs ≤ VIL or ≥ VIH

;

I

3

8

25 25 25 25 25

All inputs static; CLK frequency = 0

Device deselected; VDD = MAX;

ADSC#, ADSP#, GW#, BWx#, ADV# ≥

IH; All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;

I

4

55 130 120 110 90 85

V

t

Cycle time ≥ KC (MIN)

NOTE: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.

2. I^DDis specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greateroutputloading.

3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device

is active (not in power-down mode).

4. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS

(Note 1) (0°C ≤ T_A≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)

-4.4

-5

-6

-7.5

-10

DESCRIPTION

SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

Clock cycle time

Clockfrequency

ClockHIGHtime

t

KC

KF

4.4

5.0

6.0

7.5

10

ns

f

225

2.6

200

2.8

166

3.5

133

4.0

100 MHz

t

KH

1.7

2.0

2.3

2.5

3.0

ns

2

t

Clock LOW time

KL

OutputTimes

t

Clock to output valid

Clock to output invalid

Clock to output in Low-Z

ClocktooutputinHigh-Z

OE# to output valid

OE# to output in Low-Z

OE# to output in High-Z

SetupTimes

KQ

5.0

ns

t

KQX

KQLZ

KQHZ

OEQ

OELZ

OEHZ

1

0

1.0

0

1.5

0

1.5

0

1.5

3

t

3, 4, 5, 6

7

3, 4, 5, 6

2.6

2.8

3.5

4.2

5.0

t

0

t

2.6

2.8

3.5

4.2

4.5

t

Address

Address status (ADSC#, ADSP#)

Addressadvance(ADV#)

AS

1

1.3

1.5

2.0

ns

8, 9

t

ADSS

t

AAS

WS

t

Write signals

(BWa#-BWd#,BWE#,GW#)

t

Data-in

Chipenables(CE#, CE2#, CE2)

HoldTimes

Address

Address status (ADSC#, ADSP#)

Addressadvance(ADV#)

DS

1

1.3

1.5

2.0

ns

8, 9

t

CES

t

AH

0.3

0.5

ns

8, 9

t

ADSH

t

AAH

t

Write signals

WH

(BWa#-BWd#,BWE#,GW#)

t

Data-in

Chipenables(CE#, CE2#, CE2)

DH

0.3

0.5

ns

8, 9

t

CEH

NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and

Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.

2. Measured as HIGH above VIH and LOW below VIL.

3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.

4. This parameter is sampled.

5. Transition is measured 500mV from steady state voltage.

6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough

discussion on these parameters.

7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.

8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.

A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup

and hold times.

9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold

times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at

each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

19

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

3.3V I/O AC TEST CONDITIONS

2.5V I/O AC TEST CONDITIONS

Input pulse levels ................. VIH = (VDD/2.2) + 1.5V

Input pulse levels ............. VIH = (VDD/2.64) + 1.25V

....................V^IL= (VDD/2.2) - 1.5V

................V^IL= (VDD/2.64) - 1.25V

Input rise and fall times..................................... 1ns

Input timing reference levels ..................... VDD/2.2

Output reference levels ............................V^DDQ/2.2

Output load ............................. See Figures 1 and 2

Input rise and fall times..................................... 1ns

Input timing reference levels ................... VDD/2.64

Output reference levels ............................... V^DDQ/2

Output load ............................. See Figures 3 and 4

3.3V I/O Output Load Equivalents

2.5V I/O Output Load Equivalents

Q

Z_O= 50Ω

50Ω

Z_O= 50Ω

50Ω

V = 1.5V

V_T= 1.25V

T

Figure 1

Figure 3

+2.5V

225Ω

5pF

+3.3V

317

Q

5pF

351

225Ω

Figure 2

Figure 4

LOADDERATINGCURVES

Micron 256K x 18, 128K x 32, and 128K x 36 SyncBurst

SRAM timing is dependent upon the capacitive load-

ing on the outputs.

Consult the factory for copies of I/O current versus

voltage curves.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

SNOOZEMODE

SNOOZE MODE is a low-current, “power-down”

mode in which the device is deselected and current is

reduced to I^SB2Z. The duration of SNOOZE MODE is

dictated by the length of time ZZ is in a HIGH state.

After the device enters SNOOZE MODE, all inputs ex-

cept ZZ become gated inputs and are ignored.

ZZ is an asynchronous, active HIGH input that

causes the device to enter SNOOZE MODE. When ZZ

becomes a logic HIGH, I^SB2Z is guaranteed after the

t

setup time ZZ is met. Any READ or WRITE operation

pending when the device enters SNOOZE MODE is not

guaranteed to complete successfully. Therefore,

SNOOZE MODE must not be initiated until valid pend-

ing operations are completed.

SNOOZEMODEELECTRICALCHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL

ISB2Z

^tZZ

^tRZZ

^tZZI

^tRZZI

MIN

MAX

10

2(^tKC)

UNITS NOTES

Current during SNOOZE MODE

ZZ active to input ignored

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ZZ ≥ VIH

mA

ns

1

2(^tKC)

0

2(^tKC)

NOTE: 1. This parameter is sampled.

SNOOZEMODEWAVEFORM

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

I

ISB2Z

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

3

READTIMING

(READ timing parameters are contained on the following page.)

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC#

t

ADSH

ADSS

t

AH

AS

A1

A2

A3

Burst continued with

ADDRESS

t

WH

WS

new base address.

GW#, BWE#,

BWa#-BWd#

Deselect

cycle.

t

CEH

CES

CE#

(NOTE 2)

(NOTE 4)

t

AAH

AAS

ADV#

OE#

ADV#

suspends

burst.

t

OEQ

KQ

(NOTE 3)

High-Z

t

OEHZ

t

OELZ

t

KQHZ

KQX

t

KQLZ

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A1)

Q

t

KQ

Burst wraps around

to its initial state.

(NOTE 1)

Single READ

BURST READ

DON’T CARE

UNDEFINED

NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to

be driven until after the following clock rising edge.

4. Outputs are disabled within one clock cycle after deselect.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

READ TIMING PARAMETERS

-4.4

-5

-6

-7.5

-10

SYMBOL

MIN

MAX

MIN

MAX UNITS

SYMBOL

MIN MAX MIN MAX MIN MAX UNITS

t

KC

4.4

5.0

ns

KC

6.0

7.5

10

ns

MHz

ns

f

KF

225

200

2.8

MHz

ns

KF

166

3.5

133

4.0

100

5.0

t

KH

1.7

2.0

KH

2.3

2.5

3.0

t

KL

t

KQ

2.6

KQ

t

KQX

1

0

1.0

0

KQX

1.5

0

1.5

0

1.5

t

KQLZ

t

KQHZ

2.6

2.8

KQHZ

3.5

4.2

5.0

t

OEQ

t

OELZ

0

1

0

OELZ

0

t

OEHZ

2.6

2.8

OEHZ

3.5

4.2

4.5

t

AS

1.3

0.5

AS

1.5

0.5

1.5

0.5

2.0

0.5

t

ADSS

t

AAS

1

AAS

t

WS

1

WS

t

CES

1

CES

t

AH

0.3

AH

t

ADSH

t

AAH

t

WH

t

CEH

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

23

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

WRITETIMING

(WRITE timing parameters are contained on the following page.)

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC# extends burst.

t

ADSH

ADSS

t

ADSH

ADSS

ADSC#

t

AH

AS

A1

A2

A3

ADDRESS

Byte write signals are

ignored for first cycle when

ADSP# initiates burst.

t

WS

t

WH

BWE#,

BWa#-BWd#

t

WH (NOTE 5)

WS

GW#

t

CEH

CES

CE#

(NOTE 2)

t

AAS

t

AAH

ADV#

OE#

ADV# suspends burst.

(NOTE 4)

(NOTE 3)

t

DH

DS

D

Q

D(A2)

D(A2 + 1)

(NOTE 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

t

OEHZ

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE UNDEFINED

NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output

data contention for the time period prior to the byte write enable inputs being sampled.

4. ADV# must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW#

HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

WRITE TIMING PARAMETERS

-4.4

-5

-6

-7.5

-10

SYMBOL

MIN

MAX

MIN

MAX UNITS

SYMBOL

MIN MAX MIN MAX MIN MAX UNITS

t

KC

4.4

5.0

ns

KC

6.0

7.5

10

ns

MHz

ns

f

KF

225

200

2.8

MHz

ns

KF

166

3.5

133

4.2

100

4.5

t

KH

1.7

2.0

KH

2.3

2.5

3.0

t

KL

ns

t

OEHZ

2.6

OEHZ

ns

t

AS

1

1.3

0.5

AS

1.5

0.5

1.5

0.5

2.0

0.5

ns

t

ADSS

ns

t

AAS

1

AAS

ns

t

WS

1

WS

ns

t

DS

1

DS

ns

t

CES

1

CES

ns

t

AH

0.3

AH

ns

t

ADSH

ns

t

AAH

ns

t

WH

ns

t

DH

ns

t

CEH

ns

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

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4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

6

READ/WRITETIMING

(READ/WRITE timing parameters are contained on the following page.)

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC#

t

AH

AS

A1

A2

A3

A4

A5

A6

ADDRESS

t

WH

WS

BWE#,

BWa#-BWd#

(NOTE 4)

t

CEH

CES

CE#

(NOTE 2)

ADV#

OE#

t

DH

t

KQ

DS

t

OELZ

D

Q

High-Z

D(A3)

D(A5)

D(A6)

t

OEHZ

KQLZ

(NOTE 1)

Q(A4)

Q(A1)

Q(A2)

Q(A4+1)

Q(A4+2)

Q(A4+3)

Back-to-Back READs

(NOTE 5)

Single WRITE

BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.

4. GW# is HIGH.

5. Back-to-back READs may be controlled by either ADSP# or ADSC#.

6. Timing is shown assuming that the device was not enabled before entering into this sequence.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

26

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

READ/WRITE TIMING PARAMETERS

-4.4

-5

-6

-7.5

-10

SYMBOL

MIN

MAX

MIN

MAX UNITS

SYMBOL

MIN MAX MIN MAX MIN MAX UNITS

t

KC

4.4

5.0

ns

KC

6.0

7.5

10

ns

MHz

ns

f

KF

225

200

2.8

MHz

ns

KF

166

3.5

133

4.0

4.2

100

5.0

4.5

t

KH

1.7

2.0

KH

2.3

2.5

3.0

t

KL

t

KQ

2.6

KQ

t

KQLZ

0

KQLZ

0

1.5

0

t

OELZ

ns

t

OEHZ

t

AS

1

1.3

0.5

AS

1.5

0.5

1.5

0.5

2.0

0.5

t

ADSS

t

WS

1

WS

t

DS

1

DS

t

CES

1

CES

t

AH

0.3

AH

t

ADSH

t

WH

t

DH

t

CEH

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

27

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

100-PINPLASTICTQFP(JEDECLQFP)

+0.10

-0.20

22.10

20.10 0.10

0.65 TYP

0.32

+0.06

-0.10

0.625

SEE DETAIL A

14.00 0.10

16.00 0.20

PIN #1 ID

+0.03

-0.02

0.15

1.40 0.05

GAGE PLANE

0.60 0.15

1.60 MAX

+0.10

-0.05

0.10

1.00 TYP

0.25

DETAIL A

MAX

MIN

NOTE: 1. All dimensions in millimeters

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

28

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

165-PINFBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

13.00 0.10

SOLDER BALL MATERIAL:

EUTECTIC 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .33mm

MAX

MIN

NOTE: 1. All dimensions in millimeters

or typical where noted.

2. The 165-ball FBGA is not recommended for new designs in the 4Mb density.

DATASHEETDESIGNATIONS

No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are

subject to change, as further product development and data characterization sometimes occur.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail:prodmktg@micron.com,Internet:http://www.micronsemi.com,CustomerCommentLine:800-932-4992

Micron, the Micron logo, M logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

29

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

REVISIONHISTORY

Added “The 165-ball FBGA is not recommended for new designs in the 4Mb density” ........................... January 3/03

Removed "Preliminary Package Data" from front page .............................................................................. February 22/02

Removed -4 speed grade

Removed 119-pin PBGA package and references .......................................................................................... February 2/02

Removed note "Not Recommended for New Designs," Rev. 6/01 ...................................................................... June 7/01

Added Industrial Temperature note and reference, Rev. 3/01 ........................................................................ March 6/01

Added 119-pin PBGA package, Rev. 1/01, FINAL ........................................................................................... January 10/01

Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .............................................................................. August 22/00

Changed FBGA capacitance values, REV 8/00, FINAL ....................................................................................... August 7/00

C^I; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF

CO; TYP 4pF from 6pF; MAX. 5pF from 7pF

C^CK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF

Added FBGA Part Marking Guide, Rev. 7/00, Preliminary .................................................................................. June 13/00

Added FBGA Part Marking References

Removed 119-Pin PBGA package and references

Removed industrial temperature references

Added 165-pin FBGA package, Rev. 6/00, Preliminary ........................................................................................ May 23/00

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

30


型号：	MT58L128L32P1T-10
厂家：	Rochester Electronics
描述：	128KX32 CACHE SRAM, 5ns, PQFP100, PLASTIC, MS-026, TQFP-100 静态存储器内存集成电路
文件：	总31页 (文件大小：1131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT58L128L32P1T-10 [ROCHESTER]

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