MCF5307CFT66B_技术文档

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MCF5307

Product Brief

®

MCF5307 Integrated ColdFire Microprocessor

Overview

®

Introduction

The MCF5307 integrated microprocessor combines a ColdFire processor core

with the following components:

• 8K uniﬁed cache

• Multiply-Accumulate (MAC) unit and Divide unit

• DRAM controller

• DMA controller

• Timers

• M-Bus (I C)

2

1

• Parallel and serial interface

• System integration unit

Designed for embedded control applications, the ColdFire core delivers enhanced

performance (70 MIPS) while maintaining low system costs.

Performance boosts are supplied to the clock-doubled core through the on-chip, 8

Kbyte uniﬁed cache and 4K SRAM, which provide pipelined, single-cycle access

to critical code and data.

The integrated Multiply-Accumulate (MAC) module enhances the device’s

functionality through support of high-speed, complex arithmetic operations. The

MAC supports instruction issue rates of 1 multiply-accumulate per cycle for

16x16 operations, and also performs 32x32 operations, all producing a 32-bit

result.

The MCF5307 processor greatly reduces the time required for system design and

implementation by packaging common system functions on chip and providing

glueless interfaces to 8-, 16-, and 32-bit DRAM, EDO DRAM, SDRAM, SRAM,

ROM, FLASH, and I/O devices.

1 2

I C is a proprietary Philips bus.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

SEMICONDUCTOR PRODUCT INFORMATION

Overview, Continued

ColdFire Architecture

Provides New Price/

Performance Levels

The revolutionary ColdFire microprocessor architecture gives cost-sensitive,

high-volume markets new levels of price and performance. Based on the

concept of variable-length RISC technology, ColdFire combines the

architectural simplicity of conventional 32-bit RISC with a memory-saving,

variable-length instruction set. In deﬁning the ColdFire architecture for

embedded processing applications, Motorola incorporated RISC architecture

for peak performance and a simpliﬁed version of the variable-length

instruction set found in the M68000 Family for code density.

Clock-Doubled

Version 3 Core Boosts

Performance

The MCF5307 is the ﬁrst of the ColdFire Family to contain the Version 3,

clock-doubled ColdFire microprocessor core. Increasing the internal speed of

the core allows higher performance while providing the system designer with

an easy-to-use external system interface.

ColdFire VL RISC

Offers Many

Advantages

By using a variable-length instruction set architecture, embedded system

designers using ColdFire RISC processors will enjoy signiﬁcant advantages

over conventional ﬁxed-length RISC architectures. The denser binary code for

ColdFire processors consumes less valuable memory than any ﬁxed-length

instruction set RISC processor available. This improved code density means

more efﬁcient system memory use for a given application, and requires

slower, less costly memory to help achieve a target performance level.

The MCF5307

The integrated peripheral functions provide high performance and ﬂexibility.

The DRAM controller can interface with up to 256 Mbytes of DRAM and

supports bursting, page-mode, EDO and synchronous DRAMs.

Integrates a Rich Set

of Modules with the

ColdFire V3 Core

Serial communication channels are provided by two programmable full-

2

duplex UARTs and an M-Bus (I C interface-compatible) module. Four

channels of DMA allow for fast data transfer using a programmable burst

mode independent of processor execution. The two 16-bit general-purpose

multimode timers provide separate input and output signals. For system

protection, the processor includes a programmable 16-bit software watchdog

timer. In addition, common system functions such as chip-selects, interrupt

control, bus arbitration, and an IEEE 1149.1 JTAG module are included.

A sophisticated debug interface supports background-debug mode and real-

time trace, with on-chip breakpoint registers accessible from an emulator or

the processor itself. This interface is present in all ColdFire-based processors

and allows common emulator support across the entire ColdFire Family.

2

MCF5307 Product Brief

MOTOROLA

MCF5307 Features

ColdFire Processor

Core

• Variable-length RISC, clock-doubled Version 3 microprocessor core

• Independent 4-stage instruction and 2-stage operand pipelines

• 8-instruction FIFO buffer to provide decoupling between the pipelines

• Branch acceleration unit for increased performance

• 32-bit internal address bus with up to 4 Gbytes of linear address space

• 32-bit data bus

• 16 user-accessible, 32-bit-wide, general-purpose registers

• Supervisor / User modes for system protection

• Vector base register to relocate exception-vector table

• Optimized for high-level language constructs

• Hardware Integer Divide Unit

Multiply and

Accumulate Unit

• Provides high-speed, complex arithmetic processing for DSP

applications

• 1 clock issue rate with 3-stage execute pipeline

• Supports 16x16 and 32x32 multiplies, all with 32-bit accumulate

8 Kbyte Uniﬁed Cache

• Four-way set associative organization with writethrough and copyback

modes

• Operates at microprocessor core speed

• Provides single-cycle access to critical code and data

4 Kbyte SRAM

DMA Controller

• Programmable location within 4 Gbyte linear address space

• Provides pipeline single cycle access to critical code and data

• Information stored in SRAM not affected by RESET instruction

• Four fully programmable channels

• Supports dual-address and single-address transfers with 32-bit data

capability

• Two address pointers per channel that can increment or remain constant

• 16-bit transfer counter per channel

• Operand packing and unpacking supported

• Auto-alignment transfers supported for efﬁcient block movement

• Supports bursting and cycle steal

• Provides two clock-cycle internal access

DRAM Controller

• Supports up to 512 Mbytes of DRAM

• Programmable refresh timer provides CAS-before-RAS refresh

• Support for two separate memory banks

• Support for EDO DRAMs and synchronous DRAMs

• Support for external masters

MOTOROLA

MCF5307 Product Brief

3

MCF5307 Features, Continued

2 UARTs

• Full duplex operation

• Flexible baud-rate generator

• Modem control signals available (CTS, RTS)

• Processor-interrupt capability

Dual 16-Bit General-

Purpose Multimode

Timers

• 8-bit prescaler

• Timer input and output pins

• Processor-interrupt capability

• 22 ns resolution at 45 MHz

Motorola Bus

(M-Bus) Module

• Interchip bus interface for EEPROMs, LCD controllers, A/D converters,

keypads

• Fully compatible with industry-standard I C Bus

2

• Master or slave modes support multiple masters

• Automatic interrupt generation with programmable level

System Interface

• Glueless bus interface with chip selects and DRAM controller support for

interface to 8-, 16-, and 32-bit DRAM, SRAM, ROM, FLASH, and I/O

devices

• 8 chip-select signals; 2 that are fully programmable with base address

registers, 6 at a ﬁxed offset off the chip-select base address register

• Programmable wait states and port sizes

• User-deﬁned bus speed @ 1/2, 1/3, or 1/4 of processor clock

• Programmable interrupt controller

• Low interrupt latency

• 4 external interrupt request inputs

• Programmable autovector generator

• 16-Bit general-purpose I/O interface

• IEEE 1149.1 test (JTAG) module

System Debug Support

• Real-time trace for determining dynamic execution path

• Background debug mode (BDM) for debug features while halted

• Real-time debug support, including three user-visible hardware breakpoint

registers

4

MCF5307 Product Brief

MOTOROLA

MCF5307 Features, Continued

On-Chip PLL

• Accepts input frequencies ranging from 16.67 to 45 MHz

• Generates 2X core clock and a bus clock of either 1/2, 1/3, or 1/4 the core

clock based on user conﬁguration at reset

• Supports low-power mode

Product Offerings

• 75 MIPS at 45 MHz (90 MHz clock-doubled internally)

• Offered at 90 MHz core clock with external bus capability of 45, 30, and

22.5 MHz (operating temperature: 0° to +70° C)

• Offered at 66.7 MHz core clock with external bus capability of 33.3, 22.2,

and 16.7 MHz (operating temperature: 0° to +70° C and -40° to +85° C)

• Fully static 3.3-volt operation with 5V tolerant I/O pads

• 208 QFP package

MCF5307 Block Diagram

Overview of

MCF5307

Components

Figure 1 is a block diagram of the MCF5307 processor. The paragraphs that

follow provide an overview of the integrated processor components.

Figure 1: MCF5307

Block Diagram

CLOCK

INPUT

CLOCK MULTIPLIED PLL

DRAM

CONTROL

CONTROLLER

JTAG

INTERFACE

JTAG

CHIP

SELECTS

CHIP

SELECTS

INTERRUPT

SUPPORT

INTERRUPT

8 KBYTE

UNIFIED

CACHE

CONTROLLER

EXTERNAL

BUS

EXTERNAL

BUS INTERFACE

PARALLEL

INTERFACE

GENERAL

PURPOSE I/O

4K SRAM

SERIAL

INTERFACE

UARTs

DEBUG

MODULE

BDM

INTERFACE

TIMER

SUPPORT

TIMERS

COLDFIRE

CORE

DMA

INTERFACE

DMA MODULE

M-BUS

INTERFACE

2

I C MODULE

MAC MODULE

MOTOROLA

MCF5307 Product Brief

5

ColdFire Processor Core

Overview

The ColdFire processor Version 3 core consists of two independent,

decoupled pipelines to maximize performance while minimizing core size:

the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP).

Instruction Fetch

Pipeline

The four-stage instruction fetch pipeline is for prefetching instructions. The

IFP contains a branch acceleration unit that analyzes the prefetched

instruction stream and takes a predicted branch to allow this pipeline to begin

fetching the target path before the instruction is executed. This technique can

improve the execution time of these change-of-ﬂow instructions considerably.

In addition, illegal instructions are decoded and an illegal instruction

exception will be taken.

Operand Execution

Pipeline

The prefetched instruction stream is gated into the two-stage operand

execution pipeline, which decodes the instruction, fetches the required

operands and executes the required function. Because the IFP and OEP are

decoupled by an instruction buffer that serves as a FIFO queue, the IFP can

prefetch instructions in advance of their actual use by the OEP, thereby

minimizing time stalled waiting for instructions. The OEP is implemented in a

two-stage pipeline featuring a traditional RISC datapath with a two-read/one-

write port register ﬁle connected to these four execution units:

1. Arithmetic/logic unit

2. Barrel shifter

3. Integer divide

4. MAC

MAC Module

The MAC unit provides high-performance DSP capabilities for the

MCF5307. Integrated as an execution unit in the processor's operand

execution pipeline, the MAC unit implements a 3-stage arithmetic pipeline

with a sustained instruction issue rate of 1 multiply-accumulate per cycle for

16 x 16 operations (while also supporting 32 x 32 operations). The MAC

opcodes provide a full-featured set of extensions to the standard ColdFire

instruction set for signed and unsigned operands. In addition to executing the

MAC-speciﬁc instructions, this unit also performs all integer multiply

opcodes, providing higher performance for this class of operations.

6

MCF5307 Product Brief

MOTOROLA

8 Kbyte Uniﬁed Cache

The cache improves system performance by providing pipelined, single-cycle

access to the processor core on references that hit in this memory. This

decouples processor performance from system memory performance and

increases bus availability for alternate bus masters, whether internal (the 4-

channel DMA) or external.

The nonblocking design of the MCF5307 cache includes 16-byte line-ﬁll

buffers that allows processor-initiated requests that are mapped into this

memory to be serviced while cache line-ﬁll transfers are in progress. You can

conﬁgure various memory address regions to operate as copyback or write-

through cacheable regions, or as noncacheable spaces.

In addition to the 16 bytes of data, each cache line contains an address tag,

and control bits. Support for a bursting interface quickly performs line-sized

transfers in response to cache misses. A 4-entry, 32-bit-wide store buffer can

decouple processor writes from the slower system bus interface to improve

performance. The cache design, coupled with the processor microarchitecture,

allows the MCF5307 to achieve 70 MIPS performance using a 90/45 MHz

operating frequency.

Internal 4Kbyte SRAM

The 4 Kbyte on-chip SRAM is connected directly to the ColdFire core and

provides pipelined single-cycle access to the address space mapped into this

memory. Typically, this memory serves as the system stack. Additionally, you

can map heavily referenced code segments or data variables into the SRAM to

maximize performance. Users deﬁne the location of this memory within the 4

Gbyte linear address space of the processor.

DRAM Controller

The MCF5307 DRAM controller provides a glueless interface for as many as

2 banks of DRAM, each of which can be as large as 128 Kbytes up to 256

Mbytes. The controller supports 8-, 16-, or 32-bit memory widths. A unique

addressing scheme allows for increases in system memory size without

rerouting address lines and rewiring boards. The controller operates in normal

mode or in page mode, and supports extended-data-out (EDO) DRAMs and

synchronous DRAMs. At a 45 MHz external bus speed, the DRAM controller

supports DRAMs with access times as fast as 22 ns.

MOTOROLA

MCF5307 Product Brief

7

DMA Controller

UART Modules

MCF5307 provides four fully programmable DMA channels for quick data

transfer. Single- and dual-address mode is provided with the ability to

program bursting and cycle steal. Data transfers are 32 bits in length with

packing and unpacking supported along with an auto-alignment option for

efﬁcient block transfers.

Each UART on the MCF5307 contains an on-chip baud-rate generator, which

provides both standard and nonstandard baud rates. Data formats can be 5, 6,

7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16

increments. Four-byte receive buffers and two-byte transmit buffers minimize

CPU service calls. The UART modules also provide several error-detection

and maskable-interrupt capabilities. Modem support includes request-to-send

(RTS) and clear-to-send (CTS) lines.

The system clock provides the clocking function via a programmable

prescaler. Full duplex, auto-echo loopback, local loopback, and remote

loopback modes let you test UART connections. The programmable UARTs

can interrupt the CPU on various normal or error-condition events.

Timer Module

The timer module includes two general-purpose timers, each of which

contains a free-running 16-bit timer for use in any of three modes. One mode

captures the timer value with an external event. Another mode triggers an

external signal or interrupts the CPU when the timer reaches a set value, while

a third mode counts external events.

The timer unit has an 8-bit prescaler that allows programming of the clock

input frequency, which is derived from the system clock or an external clock

input pin (TIN). The programmable timer-output pin generates either an

active-low pulse or toggles the output.

8

MCF5307 Product Brief

MOTOROLA

Motorola Bus (M-Bus) Module

The M-Bus interface is a two-wire, bidirectional serial bus that exchanges

2

data between devices and is compliant with the I C Bus standard. The M-Bus

minimizes the interconnection between devices in the end system and is best

suited for applications that need occasional bursts of rapid communication

over short distances among several devices.

System Interface

Overview

The MCF5307 processor provides a glueless interface to 8-, 16-, and 32-bit

port size FLASH, SRAM, ROM, and peripheral devices with independent

programmable control of the assertion and negation of chip-selects and write-

enables. The MCF5307 also supports bursting ROMs. The MCF5307 has a

clock-multiplied core that operates at 2x, 3x, or 4x the external bus frequency.

You select the multiplier for the bus frequency at reset of the microprocessor.

External Bus Interface

The bus interface controller transfers information between the ColdFire core

or DMA and memory, peripherals, or other devices on the external bus. The

external bus interface provides 32 bits of address bus space, a 32-bit data bus,

and all associated control signals. This interface implements an extended

synchronous protocol that supports bursting operations.

Simple two-wire request/acknowledge bus arbitration between the MCF5307

processor and another bus master, such as an external DMA device, is glueless

with arbitration logic internal to the MCF5307 processor. Multiple-master

arbitration is also available with some external arbitration logic.

Chip-Selects

Eight chip-select outputs (2 that are programmable with base address

registers, 6 at ﬁxed offsets from the chip-select bus address register) provide

signals that enable external memory and peripheral circuits with automatic

wait-state insertion. These signals interface to 8-, 16-, or 32-bit ports. The

base address, access permissions, and internal bus transfer terminations are

programmable with conﬁguration registers.

16-Bit Parallel Port

Interface

A 16-bit general-purpose programmable parallel port serves as either an input

or an output on a bit-by-bit basis.

MOTOROLA

MCF5307 Product Brief

9

System Interface, Continued

Interrupt Controller

The interrupt controller provides user-programmable control of 10 internal

peripheral interrupts and implements 4 external ﬁxed interrupt-request pins.

You can program each internal interrupt to any one of 7 interrupt levels and 4

priority levels within each of these levels and can program the external

interrupt request pins to level 1, 3, 5, and 7 or levels 2, 4, 6, and 7.

Autovector capability is available for internal and external interrupts.

JTAG

To help with system diagnostics and manufacturing testing, the MCF5307

processor includes dedicated user-accessible test logic that complies with the

IEEE 1149.1a standard for boundary-scan testability, often referred to as Joint

Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a

standard.

System Debug Interface

The ColdFire processor core debug interface supports real-time trace and

debug, along with background debug mode (BDM). The BDM interface is

implemented using a serial communication channel with an emulator. The

BDM is compatible with the BDM interface provided on Motorola’s 683XX

Family of parts.

To support real-time trace, four output bits (PST) provide status information

on processor activity on a cycle-by-cycle basis. Additionally, a 4-bit output

data bus (DDATA) can be conﬁgured to display operand data and certain

change-of-ﬂow target addresses for determining the dynamic execution path

through the application.

Finally, the Debug module provides a number of on-chip breakpoint registers

that can be conﬁgured by an emulator, or by the processor itself to generate

special debug interrupts or processor halts. The breakpoint resources include

two 32-bit address registers, a 32-bit PC and 32-bit PC mask registers, and a

32-bit data register and 32-bit data mask register. These breakpoint registers

can be conﬁgured in single- or double-level triggers where you deﬁne the

trigger response.

10

MCF5307 Product Brief

MOTOROLA

PLL Module

Overview

The MCF5307 PLL module has three modes of operation:

1. Normal mode

2. Reduced power mode

3. Reset mode

Normal Mode Input

Frequency

In normal mode, an input frequency to the MCF5307 can range from 16.67

MHz to 45 MHz. This input frequency is programmed at reset and clock-

doubled to provide the processor clock and then is divided down to provide

the bus clock output. The bus clock is programmed to 1/2, 1/3, or 1/4 of the

core clock.

Reduced Power Mode

In reduced power mode, the PLL core clock is shut off by a combination of

executing the STOP instruction and programming a control bit in the System

Conﬁguration register. This low-power mode allows the core to be turned off

while retaining the core register contents.

Reset Mode

When the MCF5307 RESET pin is asserted, the PLL enters reset mode. At

reset, the PLL asserts RESETO to the rest of the processor and as an external

pin from the MCF5307. The system input frequency range, MCF5307 bus

clock frequency (along with other MCF5307 conﬁguration information) are

all sampled during reset mode.

MOTOROLA

MCF5307 Product Brief

11

Programming Model, Instruction Set, and Addressing Mode

Overview

The ColdFire programming model is separated into two privilege modes:

supervisor and user. The S-bit in the status register (SR) indicates the current

privilege mode. The processor identiﬁes a logical address by accessing either

the supervisor or user address space, which differentiates between supervisor

and user modes.

Supervisor Mode

Supervisor mode protects system resources from uncontrolled access by

users. In supervisor mode, you can access all registers and execute all

ColdFire instructions. Operating system functions (including I/O control) are

performed while in supervisor mode. During exception processing, the

processor enters supervisor mode regardless of the operating mode at the time

of the exception.

Typically, system programmers use the supervisor programming model to

implement operating system functions and provide I/O control. The

supervisor programming model provides access to the same registers as the

user model, plus seven additional registers. These added resources include the

upper byte of the Status Register (SR), the Vector Base Register (VBR), plus

ﬁve registers deﬁning the conﬁguration and attributes of the address space

connected to the MCF5307.

User Mode

While in user mode, access to only a subset of the supervisor registers is

allowed, and execution of privileged instructions is not permitted. Typically,

most application processing occurs while in user mode. Entry into user mode

is usually accomplished by executing a “return from exception” (RTE) or

MOVE, SR instruction.

User Programming

Model

The registers depicted in the programming model (see Figure 2) provide high-

speed storage for data and addresses for the ColdFire processor core. The user

programming model consists of sixteen general-purpose 32-bit registers {D0-

D7, A0-A7} plus two additional registers: the program counter (PC) and the

condition code register (CCR).

The program counter is a 32-bit register containing the address of the

instruction currently being executed by the MCF5307 processor. The 8-bit

CCR contains indicator ﬂags that reﬂect the result of a previous operation and

are used for conditional instruction execution.

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MCF5307 Product Brief

MOTOROLA

Programming Model, Instruction Set, and Addressing Mode,

Continued

Status Register (SR)

The upper byte of the Status Register provides interrupt information in

addition to a variety of mode indicators signaling the operating state of the

ColdFire processor.

Vector Base Register

(VBR)

The VBR deﬁnes the upper 12 bits of the base address of the exception vector

table used during exception processing. The low-order 20 bits are forced to

zero, placing the vector table on a 0-modulo-1Mbyte address boundaries,

which is set by the upper 12 bits of the address.

Cache Control

Register (CCR)

The Cache Control Register (CACR) deﬁnes the conﬁguration of the uniﬁed

cache and provides a set of default address attributes.

Access Control

Registers (ACRs)

There are two Access Control Registers (ACR0, ACR1), which each deﬁne a

set of address attributes for a speciﬁc memory space. For example, a memory

space can be deﬁned as copyback, writethrough, or noncacheable using the

ACR registers.

RAM Base Address

Register (RAMBAR)

The RAM Base Address Register (RAMBAR) provides the logical base

address for the processor's 4 Kbyte SRAM module as well as deﬁnition of

those access types that are allowed to access that SRAM.

Module Base Address

Register (MBAR)

The Module Base Address Register (MBAR) deﬁnes the logical base address

for the memory-mapped space containing the control registers for the on-chip

peripherals.

MOTOROLA

MCF5307 Product Brief

13

Programming Model, Instruction Set, and Addressing Mode,

Continued

Figure 2. ColdFire

Programming Model

31

0

D0

D1

D2

D3

D4

D5

D6

D7

DATA

REGISTERS

31

0

A0

A1

A2

A3

A4

A5

A6

A7

PC

CCR

ADDRESS

REGISTERS

STACK POINTER

PROGRAM COUNTER

CONDITION CODE REGISTER

USER PROGRAMMING MODEL

15

19

31

(CCR)

SR

STATUS REGISTER

MUST BE ZEROS

VBR

VECTOR BASE REGISTER

CACR

ACR0

ACR1

MBAR

CACHE CONTROL REGISTER

ACCESS CONTROL REGISTER 0

ACCESS CONTROL REGISTER 1

MODULE BASE ADDRESS REGISTER

RAMBAR

RAM BASE ADDRESS REGISTER

SUPERVISOR PROGRAMMING MODEL

14

MCF5307 Product Brief

MOTOROLA

Programming Model, Instruction Set, and Addressing Mode,

Continued

Data Format

Summary

Operands can be signed or unsigned and are contained in registers, memory,

or the instructions themselves. The operand speciﬁers and size for each

operation are either explicitly encoded in the instruction or implicitly deﬁned

by the instruction’s deﬁnition. Table 1 summarizes the MCF5307 data

formats.

Table 1: MCF5307

Data Formats

OPERAND DATA FORMAT

SIZE

1 Bit

Bit

Byte

8 Bits

16 Bits

32 Bits

Word

Longword

Notational

Conventions

The following tables list the commonly used ColdFire notational conventions.

REGISTER SPECIFICATION

An

Ay, Ax

Dn

Any Address Register n (example: A3 is address register 3)

Source and destination address registers, respectively.

Any Data Register n (example: D5 is data register 5)

Source and destination data registers, respectively.

Control Register (example: VBR, CACR)

Dy, Dx

Rc

Rn

Any Address or Data Register n

Ry, Rx

Rw

Any source and destination registers, respectively.

Destination Register w (used on certain MAC instructions only)

Index Register i (Can be an address or data register: A, Di)

Xi

REGISTER NAMES

CCR

MACSR

PC

Condition Code Register (lower byte of status register)

MAC Status Register

Program Counter

Racc

Rmask

SR

MAC Accumulator Register

MAC Mask Register

Status Register

DATA SIZE AND TYPE

<size>

Operand Data Size: Byte (B), Word (W), Longword (L).

Specifies a signed integer data type of 8-bit byte, 16-bit word, or 32-bit longword.

B, W, L

MOTOROLA

MCF5307 Product Brief

15

SUBFIELDS AND QUALIFIERS

#<data>

#<list>

#<vector>

()

Immediate data following the 16-bit instruction word of the instruction

List of registers for MOVEM instruction (example: D3-D0 = D3, D2, D1, D0)

Identifies a 4-bit vector number for TRAP instructions

Identifies an indirect operand address referencing memory

Identifies an absolute address referencing memory

Effective address

(xxx)

<ea>

<ea>y

<ea>x

<label>

Source effective address

Destination effective address

Assembly language program label

d

Signed displacement Value, n Bits Wide (example: d is a 16-bit displacement).

16

n

+

Postincrement indicator

Predecrement indicator

-

SF

Scale factor (x1, x2, or x4 for indexed addressing modes, <<1 or >>1 for MAC ops)

Addressing Capability Summary

The MCF5307 processor supports seven addressing modes (refer to Table 2a).

The register indirect addressing modes support postincrement, predecrement,

offset, and indexing, which are particularly useful for handling data structures

common to sophisticated embedded applications and high-level languages.

The program counter indirect mode also has indexing and offset capabilities.

This addressing mode is typically required to support position-independent

software. As part of the indexed addressing mode, ColdFire supports an

optional scale factor which can be applied to the index register to easily

access byte, word or longword entries within an array (x1, x2, x4).

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MCF5307 Product Brief

MOTOROLA

Addressing Capability Summary, Continued

Effective Addressing

Modes

An instruction’s effective addressing mode can specify the operand in one of

three ways:

1. It can specify the data value directly as an immediate operand

2. It can specify the register containing the operand

3. It can specify the addressing calculation needed to reference the memory

location containing the operand

Each addressing mode has a unique assembler syntax. In addition to the

generalized format where the addressing mode is speciﬁed directly in the

instruction, there are some opcodes where the effective address is implicitly

deﬁned by the operation itself. Table 2a summarizes the effective addressing

modes of ColdFire processors; Table 2b shows speciﬁc effective addressing

modes for the MOVE instruction; and Table 2c presents addressing variants

used by certain instructions.

Table 2a: ColdFire

Effective Addressing

Modes

ADDRESSING MODES

SYNTAX

Register Direct

Data

Dn

An

Address

Register Indirect

Address

Address with Postincrement

Address with Predecrement

Address with Displacement

(An)

(An)+

–(An)

(d16,An)

Address Register Indirect with Scaled Index

8-Bit Displacement

(d ,An,Xi*SF)

8

Program Counter Indirect

with Displacement

(d ,PC)

16

Program Counter Indirect with Scaled Index

8-Bit Displacement

(d ,PC,Xi*SF)

8

Absolute Data Addressing

Short

Long

(xxx).W

(xxx).L

Immediate

#<data>

Table 2b: Speciﬁc

Effective Addressing

Modes for MOVE

Instructions

SOURCE <EA>

DESTINATION <EA>

Dy

Ay

All

(Ay)

(Ay)+

MOTOROLA

MCF5307 Product Brief

17

Table 2b: Speciﬁc

SOURCE <EA>

DESTINATION <EA>

Effective Addressing

-(Ay)

All

Dx

Modes for MOVE

Instructions (Continued)

Ax

(d ,Ay)

16

(Ax)

(Ax)+

-(Ax)

(d ,PC)

16

(d ,Ax)

16

Dx

Ax

(d ,Ay,Xi*SF)

8

(Ax)

(Ax)+

-(Ax)

Dx

(d ,PC,Xi*SF)

8

Ax

(xxx).W

(xxx).L

(Ax)

(Ax)+

-(Ax)

Dx

Ax

#<data>

(Ax)

(Ax)+

-(Ax)

Table 2c: Addressing

Variants Used By

Certain Instructions

ADDRESSING VARIANT

ALLOWABLE MODES

Dn

(An)

(An)+

-(An)

<ea-1>

(d ,An)

16

(An)

<ea-2>

<ea-3>

(d ,An)

16

(An)

(d ,An)

16

(d ,An,Xi*SF)

8

(xxx).W

(xxx).L

(d ,PC)

16

(d ,PC,Xi*SF)

8

18

MCF5307 Product Brief

MOTOROLA

Instruction Set

Overview

The ColdFire instruction set supports high-level languages and is optimized

for those instructions most commonly generated by compilers in embedded

applications. Tables 3a and 3b provide an alphabetized listing of the ColdFire

instruction set opcode, supported operation sizes, and assembler syntax. For

two-operand instructions, the ﬁrst operand in the syntax is generally the

source operand, and the second operand is the destination.

Table 3a: Supervisor

Mode Instruction

Summary

SUPPORTED

OPERAND

SIZES

OPCODE

ADDRESSING MODES

CPUSHL

Unsized

.W

(An)

HALT*

MOVE from SR

SR,Dx

Dy,SR

#<data>,SR

MOVE to SR

.W

MOVEC

RTE

.L

Ry,Rc

Unsized

STOP

.W

.L

#<data>

<ea-2>

WDEBUG

*The HALT instruction can be configured to allow user mode execution by

setting the UHE bit in the debug module’s Configuration/Status Register

(CSR).

Table 3b: User Mode

Instruction Summary

SUPPORTED

OPERAND

SIZES

OPCODE

ADDRESSING MODES

<ea>y,Dx

ADD

.L

Dy,<ea>x

<ea>y,Ax

#<data>,Dx

#<data>,<ea>x

Dy,Dx

ADDA

ADDI

.L

ADDQ

ADDX

<ea>y,Dx

Dy,<ea>x

AND

ANDI

ASL

.L

#<data>,Dx

Dy,Dx

#<data>,Dx

Dy,Dx

#<data>,Dx

ASR

Bcc

.L

.B,.W

.B,.L

<label>

Dy,<ea>x

#<data>,<ea-1>x

BCHG

Dy,<ea>x

#<data>,<ea-1>x

BCLR

BRA

.B,.L

.B,.W

<label>

MOTOROLA

MCF5307 Product Brief

19

Table 3b: User Mode

Instruction Summary

(Continued)

SUPPORTED

OPERAND

SIZES

OPCODE

ADDRESSING MODES

Dy,<ea>x

#<data>,<ea-1>x

BSET

.B,.L

.B,.W

.B,.L

BSR

Dy,<ea>x

#<data>,<ea-1>x

BTST

CLR

.B,.W,.L

<ea>x

CMP

CMPA

CMPI

DIVS

DIVU

EOR

EORI

EXT

.L

<ea>y,Dx

<ea>y,Ax

#<data>,Dx

<ea>y, Dx

<ea-1>y, Dx

<ea>y, Dx

<ea-1>y, Dx

Dy,<ea>x

#<data>,Dx

Dx

.L

.W

.L

.W

.L

.W,.L

.L

EXTB

JMP

Dx

Unsized

.L

<ea-3>y

JSR

<ea-3>y

LEA

<ea>y,Ax

Ax,#<d16>

LINK

.W

Dy,Dx

#<data>,Dx

LSL

LSR

.L

Dy,Dx

#<data>,Dx

MAC

.W,.L

Ry, RxSF

MAC

.W,.L

Rx, RySF,<ea-1>y, Rw

see MOVE Table

MOVE

.B,.W,.L

Ry,MACSR

#<data>,MACSR

Ry,Racc

#<data>,Racc

Ry,Rmask

#,data>,Rmask

MACSR,CCR

MACSR,Rx

Racc,Rx

MOV

.L

Rmask,Rx

MOVE from CCR

MOVE to CCR

.W

CCR,Dx

Dy,CCR

#<data>,CCR

<ea-2>y,#<list>

#<list>,<ea-2>x

MOVEM

.L

MOVEQ

MSAC

MULS

MULU

.L

#<data>,Dx

Ry, RxSF

.W,.L

.W

Rx, RxSF,<ea-1>y, Rw

<ea>y,Dx

.L

<ea-1>y,Dx

<ea>,Dx

.W

.L

<ea-1>y,Dx

20

MCF5307 Product Brief

MOTOROLA

Table 3b: User Mode

Instruction Summary

(Continued)

SUPPORTED

OPERAND

OPCODE

ADDRESSING MODES

SIZES

NEG

.L

Dx

NEGX

NOP

NOT

.L

Unsized

.L

Dx

<ea>y,Dx

Dy,<ea>x

OR

.L

ORI

.L

#<data>,Dx

<ea-3>y

PEA

.L

PULSE

REMS

REMU

RTS

Unsized

.L

<ea-1>, Dx

.L

Unsized

.B

Scc

Dx

<ea>y,Dx

Dy,<ea>x

SUB

.L

SUBA

SUBI

.L

<ea>y,Ax

#<data>,Dx

#<data>,<ea>x

Dy,Dx

.L

SUBQ

SUBX

SWAP

TRAP

TRAPF

TST

.L

.W

Dx

Unsized

.W,.L

.B,.W,.L

Unsized

.B,.W,.L

#<vector>

#<data>

<ea>y

Ax

UNLK

WDDATA

<ea>y

MOTOROLA

MCF5307 Product Brief

21

General Device Information

Table 4: MCF5307

Package/Frequency

Availability

PACKAGE

OPERATING TEMP.

FREQUENCY

208 QFP

0 to 70 C,

-40 to +85 C

66.7 MHz core w/16.7, 22.2, &

33.3 MHz bus

capability

208 QFP

0 to 70 C

90 MHz core w/ 22.5, 30, &

45MHz bus capability

Documentation

Additional and detailed information is available from Motorola literature

distribution centers. To ﬁnd out more about Motorola’s ColdFire products and

development tool offerings, please visit our website at

http://www.mot.com/coldﬁre.

DOCUMENT NUMBER

DOCUMENT TITLE

MCF5307 Specification

MCF5307 Spec. Rev. 0.0(Available through secure website. Contact

your local salesperson for access)

MCF5307UM/AD

MCF5307 User’s Manual (Est. Stocking 1Q98)

5200PRM/AD Rev1

MCF5200 ColdFire Family Programmer's Reference Manual

22

MCF5307 Product Brief

MOTOROLA

MCF5307 Product Brief

23

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different

applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not

convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the

Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with

such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.

ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate,

Tai Po, N.T., Hong Kong.

SEMICONDUCTOR PRODUCT INFORMATION

MCF5307 Product Summary Page

*Digital DNA

MCF5307 : Integrated ColdFire Version 3 Microprocessor

SEARCH

The MCF5307 is a high performance (70 MIPS), low-cost,

highly integrated microprocessor, designed for embedded

control applications, which combines a Version 3 ColdFire®

processor core with a Multiply Accumulate (MAC) unit,

DRAM controller, DMA controller, timers, and parallel and

serial interfaces. The time required for system design and

implementation is greatly reduced by packaging common

system functions on chip and providing glueless interfaces to

8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices.

Support for EDO DRAM and Synchronous DRAM is also

present.

Page Contents

● Features

ADVANCED

Products

● Parametrics

Microcontrollers

/

Microprocessors

● Documentation

● Development

Tools/Boards

● Design Tools

32-Bit (68K,

ColdFire, C-Port,

MCore,

● Orderable Parts

Other Info

● Where to Buy

● Block Diagram

PowerPC, ARM)

ColdFire

● FAQs

MCF5XXX

MCF5307 Features

● 4 KByte SRAM

● Multiply-Accumulate (MAC) unit and Divide unit

● 8 KByte Unified Cache


型号：	MCF5307CFT66B
厂家：	Rochester Electronics
描述：	32-BIT, 66MHz, RISC PROCESSOR, PQFP208, 28 X 28 MM, PLASTIC, QFP-208 时钟外围集成电路
文件：	总31页 (文件大小：799K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCF5307CFT66B [ROCHESTER]

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