MAX794EPE+ [ROCHESTER]
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16, 0.300 INCH, LEA FREE, PLASTIC, DIP-16;
| 型号： | MAX794EPE+ |
| 厂家： | 
Rochester Electronics |
| 描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16, 0.300 INCH, LEA FREE, PLASTIC, DIP-16 光电二极管 |
| 文件： | 总21页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0366; Rev 4; 12/05
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________General Description
____________________________Features
MAX793/MAX794/MAX795
The MAX793/MAX794/MAX795 microprocessor (µP)
supervisory circuits monitor and control the activities of
+3.0V/+3.3V µPs by providing backup-battery switchover,
among other features such as low-line indication, µP
reset, write protection for CMOS RAM, and a watchdog
(see the Selector Guide below). The backup-battery volt-
♦ Precision Supply-Voltage Monitor:
Fixed Reset Trip Voltage (MAX793/MAX795)
Adjustable Reset Trip Voltage (MAX794)
♦ Guaranteed Reset Assertion to V
= 1V
CC
♦ Backup-Battery Power Switching—Battery
Voltage Can Exceed V
age can exceed V , permitting the use of 3.6V lithium
CC
CC
batteries in systems using 3.0V to 3.3V for V
.
CC
♦ On-Board Gating of Chip-Enable Signals—7ns
The MAX793/MAX795 offer a choice of reset threshold
voltage range (denoted by suffix letter): 3.00V to 3.15V
(T), 2.85V to 3.00V (S), and 2.55V to 2.70V (R). The
MAX794’s reset threshold is set externally with a resistor
divider. The MAX793/MAX794 are available in 16-pin
DIP and narrow SO packages, and the MAX795 comes
in 8-pin DIP and SO packages.
Max Propagation Delay
MAX793/MAX794 Only
♦ Battery Freshness Seal
♦ Battery OK Output (MAX793)
♦ Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning
♦ Independent Watchdog Timer (1.6s timeout)
♦ Manual Reset Input
_____________________Selector Guide
______________Ordering Information
FEATURE
Active-Low Reset
Active-High Reset
MAX793
MAX794 MAX795
PART*
TEMP RANGE
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
✔
✔
✔
MAX793_CPE
MAX793_CSE
MAX793_EPE
MAX793_ESE
0°C to +70°C
✔
✔
0°C to +70°C
Programmable Reset
Threshold
-40°C to +85°C
-40°C to +85°C
✔
✔
✔
Low-Line Early Warning
Output
Ordering Information continued on last page.
✔
✔
*The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
Backup-Battery
Switchover
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
External Switch Driver
Power-Fail Comparator
Battery OK Output
Watchdog Input
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
✔
✔
✔
✔
Battery Freshness Seal
Manual Reset Input
Chip-Enable Gating
Pins-Package
__________Typical Operating Circuit
(OPTIONAL)
Si9433DY
SILICONIX
✔
3.0V OR 3.3V
0.1 F
16-DIP/SO 16-DIP/SO 8-DIP/SO
0.1 F
PMOS
BATT ON OUT
________________________Applications
Battery-Powered Computers and Controllers
Embedded Controllers
V
CC
CMOS
RAM
BATT
CE OUT
0.1 F
3.6V
V
CC
MAX793
ADDRESS
DECODER
A0-A15
CE IN
WDO
MR
Intelligent Controllers
I/O
NMI
WDI
+5V SUPPLY
FAILURE
Critical µP Power Monitoring
LOWLINE
PFO
+5V
V
CC
P
Portable Equipment
PFI
RESET
RESET
BATT OK
GND
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
V
........................................................................-0.3V to 6.0V
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) .842mW
16-Pin Narrow SO (derate 9.52mW/°C above +70°C) ...696mW
Operating Temperature Ranges
MAX793_C_ _/MAX794C_ _/MAX795_C_ _......... 0°C to +70°C
MAX793_E_ _/MAX794E_ _/MAX795_E_ _........-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
.....................................................................-0.3V to 6.0V
BATT
All Other Inputs ..................-0.3V to the higher of V
Continuous Input Current
or V
CC
BATT
V
V
.................................................................................200mA
CC
................................................................................50mA
BATT
GND ..................................................................................20mA
Output Current
V
................................................................................200mA
OUT
All Other Outputs ..............................................................20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
CC
to T
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.0
TYP
MAX
5.5
5.5
60
UNITS
MAX79_C
MAX79_E
MAX793/MAX794,
MR = V
Operating Voltage Range,
V
V
, V
(Note 1)
CC BATT
1.1
V
CC
V
CC
V
CC
V
CC
< 3.6V
< 5.5V
< 3.6V
< 5.5V
46
62
35
49
CC
80
V
Supply Current
CC
I
I
µA
SUPPLY
SUPPLY
(excluding I
, I
)
OUT CE OUT
50
MAX795
70
V
Supply Current in
CC
MAX793/MAX794
MAX795
32
24
45
35
V
V
= 2.1V,
= 2.3V
CC
BATT
Battery-Backup Mode
(excluding I
µA
)
OUT
BATT Supply Current
(excluding I ) (Note 2)
1
1
µA
µA
µA
OUT
BATT Leakage Current,
Freshness Seal Enabled
V
CC
= 0V, V
= 0V
OUT
Battery Leakage Current
(Note 3)
0.5
I
I
I
= 75mA
V
V
V
V
- 0.3
V
- 0.125
OUT
OUT
OUT
CC
CC
CC
OUT Output Voltage in
Normal Mode
V
V
= 30mA (Note 4)
= 250µA (Note 4)
- 0.12
- 0.001
V
- 0.050
V
OUT
OUT
CC
V
- 0.5mV
CC
CC
I
I
= 250µA
= 1mA
- 0.1
V
BATT
- 0.034
- 0.14
OUT
BATT
OUT Output Voltage in
Battery-Backup Mode
V
= 2.3V
V
BATT
V
OUT
BATT
V
-
CC
V
SW
> V
> 1.75V (Note 5)
CC
20
65
mV
V
BATT
MAX793T/MAX795T
MAX793S/MAX795S
2.69
2.55
2.82
2.68
2.95
2.80
Battery Switch Threshold
(V
falling)
CC
V
> V
CC
BATT
V
V
SW
(Note 6)
MAX793R/MAX795R/
MAX794
2.30
2.41
2.52
This value is identical to the reset threshold,
V
rising for V
> V
BATT RST
Battery Switch Threshold
(V rising) (Note 7)
V
-
CC
CC
V
CC
BATT
V
BATT
< V
25
65
mV
RST
2
_______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
CC
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MAX793T/MAX795T
MIN
3.00
2.85
2.55
3.00
2.85
TYP
MAX
3.15
3.00
2.70
3.17
3.02
UNITS
3.075
2.925
2.625
3.085
2.935
V
V
Falling
MAX793S/MAX795S
MAX793R/MAX795R
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
CC
CC
Reset Threshold (Note 8)
V
V
RST
Rising
2.55
1.212
1.212
2.635
1.240
1.250
2.72
1.262
1.282
V
V
Falling
Rising
RESET IN Threshold
(MAX794 only)
CC
V
V
RST IN
CC
RESET IN Leakage Current
(MAX794 only)
-25
2
25
nA
ms
Reset Timeout Period
t
RP
V
CC
< 3.6V
140
200
280
LOWLINE-to-Reset
MAX793
30
5
45
60
25
V
LR
mV
Threshold, (V
-
LOWLINE
V
), V
RST
Falling
CC
MAX794
MAX793
MAX794
15
10
10
mV
mV
Low-Line Comparator
Hysteresis
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
MAX794
3.23
3.08
2.78
LOWLINE Threshold,
V
V
V
LL
V
Rising
CC
1.317
1.262
1.287
25
V
PFI
V
PFI
falling
rising
1.212
1.212
-25
1.240
1.250
2
PFI Input Threshold
PFI Input Current
V
TH
nA
PFI Hysteresis, PFI Rising
10
20
mV
BATT OK Threshold
(MAX793)
V
2.00
2.25
2.50
V
BOK
INPUT AND OUTPUT LEVELS
RESET Output Voltage High
V
I
I
= 300µA, V
= 300µA, V
= 65µA, V
= V
= V
min
0.8V
0.8V
0.8V
0.86V
0.86V
V
V
OH
SOURCE
CC
CC
RST
RST
CC
CC
CC
BATT OK, BATT ON, WDO,
LOWLINE Output Voltage
High
V
OH
max
SOURCE
CC
V
V
I
I
= V
max
V
V
PFO Output Voltage High
OH
SOURCE
CC
RST
CC
BATT ON Output
Voltage High
= 100µA, V
= 2.3V, V
= 3V 0.8V
OH
SOURCE
CC
BATT BATT
RESET Output Leakage
Current (Note 9)
I
V
V
= V max
RST
-1
-1
µA
µA
LEAK
CC
PFO Output Short to GND
Current
I
= 3.3V, V = 0V
PFO
180
500
SC
CC
PFO, RESET, RESET, WDO,
LOWLINE Output Voltage
Low
I
= 1.2mA; RESET, LOWLINE tested
SINK
V
with V
WDO tested with V
= V
min; RESET, BATTOK,
0.08
0.2V
CC
V
OL
CC
RST
= V
max
RST
CC
_______________________________________________________________________________________
3
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
CC
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.13
0.17
MAX
0.3
0.3
UNITS
MAX79_C, V
MAX79_E, V
= V = 1.0V, I
= 40µA
= 200µA
BATT
BATT
CC
SINK
RESET Output Voltage Low
V
V
V
OL
OL
= V = 1.2V, I
CC
SINK
BATT ON Output
Voltage Low
I
= 3.2mA, V
= V
max
0.2V
V
V
SINK
CC
RST
CC
V
0.7V
IH
CC
All Inputs Including PFO
(Note 10)
V
max < V
< 5.5V
CC
RST
V
0.3V
CC
IL
MANUAL RESET INPUT
MR Pulse Width
t
t
MAX793/MAX794 only
MAX793/MAX794 only
100
25
ns
ns
µA
MR
75
70
250
250
MR-to-Reset Delay
MD
MR Pullup Current
MAX793/MAX794 only, MR = 0V
CHIP-ENABLE GATING
CE IN Leakage Current
I
Disable mode
10
46
nA
LEAK
CE IN-to-CE OUT
Resistance
Enable mode, V
= V
max
RST
CC
CE IN-to-CE OUT
Propagation Delay
V
= V
= V
max, Figure 9
2
7
ns
V
CC
RST
RST
V
V
max, I
= -1mA,
CC
OUT
V
0.8V
CC
OH
= V
CE IN
CC
CE OUT Drive from CE IN
Reset to CE OUT High Delay
V
V
= V
max, I
= 1.6mA,
CC
RST
OUT
V
0.2V
CC
OL
= 0V
CE IN
10
µs
V
CE OUT Output Voltage
High (reset active)
V
I
= 500µA, V
< 2.3V
0.8V
BATT
OH
OH
CC
WATCHDOG (MAX793/MAX794 only)
WDI Input Current
0V < V
< 5.5V
-1
0.01
1.60
1
µA
sec
ns
CC
Watchdog Timeout Period
WDI Pulse Width
t
1.00
1.00
2.25
WD
Note 1: V
supply current, logic input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
CC
PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at V
= 3.6V and V
=
BATT
CC
5.5V. The state of RESET is tested at V
= V
min.
CC
CC
Note 2: Tested at V
= 3.6V, V
= 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around V
CC CC
BATT
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at V
= 5.5V, V
= 1.8V and V
= 1.5V,
CC
CC
BATT
V
= 1.0V.
BATT
Note 4: Guaranteed by design.
Note 5: When V > V > V
, OUT remains connected to V
until V
drops below V
. The V -to-V
comparator
BATT
SW
CC
BATT
CC
CC
BATT
CC
has a small 15mV typical hysteresis to prevent oscillation. For V
< 1.75V (typical), OUT switches to BATT regardless of
CC
V
.
BATT
Note 6: When V
> V
> V , OUT remains connected to V
until V
drops below the battery switch threshold (V ).
BATT
CC
SW
CC
CC SW
Note 7: OUT switches from BATT to V
when V
rises above the reset threshold, if V
> V
. In this case, switchover back
RST
CC
CC
BATT
to V
V
occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If
CC
BATT
< V
, OUT switches from BATT to V
RST
when V
exceeds V
.
CC
CC
BATT
Note 8: The reset threshold tolerance is wider for V
rising than for V
falling to accommodate the 10mV typical hysteresis,
CC
CC
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
4
_______________________________________________________________________________________
3.0V/3.3V/Adjustable Microprocessor
Supervisory Circuits
__________________________________________Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
V
SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
V
-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
CC
CC
3.0
2.8
160
140
120
100
80
70
60
50
MAX793/4, V = 5V
CC
I
= 30mA
OUT
V
= 3.0V
2.6
2.4
2.2
2.0
BATT
MAX795, V = 5V
CC
40
30
20
V
= 3.6V
V
= 3.0V
MAX793/4, V = 3.3V
BATT
CC
CC
V
= 3.3V
CC
MAX795, V = 3.3V
CC
1.8
1.6
1.4
V
= 5V
CC
60
10
0
I
V
= 250 A
= 0V
OUT
CC
1.2
1.0
V
= V = V
CC
V
= 5V
BATT
OUT
BATT
40
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
RESET COMPARATOR PROPAGATION DELAY
RESET TIMEOUT PERIOD
vs. TEMPERATURE
vs. TEMPERATURE (V FALLING)
CC
0.10
0.08
0.06
0.04
0.02
30
25
20
15
10
5
250
200
150
100
50
V
V
= 0V
CC
= 3.6V
BATT
V
RISING FROM
CC
OV TO V MAX
RST
0
0
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
MAX793
MAX793/MAX794
LOWLINE-TO-RESET THRESHOLD
vs. TEMPERATURE
LOWLINE COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE
MAX793/MAX794
PFI THRESHOLD vs. TEMPERATURE
100
90
10
1.250
1.245
V
FALLING
CC
40mV OVERDRIVE
80
70
60
50
8
6
4
2
V
RISING
CC
1.240
1.235
40
30
20
V
FALLING
CC
10
0
0
1.230
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
_______________________________________________________________________________________
5
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MAX794
RESET IN THRESHOLD AND LOWLINE-TO-RESET IN
THRESHOLD vs. TEMPERATURE
CE IN-TO-CE OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793
BATT OK THRESHOLD vs. TEMPERATURE
1.242
1.241
1.240
1.239
1.238
1.237
1.236
30
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
60
50
40
30
20
10
0
V
RESET IN
V
- V
RST
LOWLINE
V
FALLING
V
FALLING
V
= V MAX
CC RST
BATT
CC
0
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
MAX793/MAX794
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAX793/MAX794
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
RESET THRESHOLD
vs. TEMPERATURE (NORMALIZED)
1.002
1.001
1.70
1.65
20
V
V
V
= 5.5V
= 0V
BATT
CC
OUT
= 0V
15
1.000
0.999
0.998
0.997
0.996
1.60
1.55
10
5
V
FALLING
CC
1.50
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
MAX793/MAX794
PFI TO PFO PROPAGATION DELAY
vs. TEMPERATURE
10
8
6
4
2
V
FALLING
PFI
20mV OVERDRIVE
0
-40 -20
0
20
40
60
80 100
TEMPERATURE ( C)
6
_______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
MAX793/
MAX794
MAX795
Supply Output for CMOS RAM. When V
rises above the reset threshold or above
CC
1
2
1
2
OUT
V
V
, OUT is connected to V
through an internal P-channel MOSFET switch. When
, BATT connects to OUT.
BATT
CC
CC
falls below V
and V
SW
BATT
V
CC
Main Supply Input
BATT OK
(MAX793)
Battery Status Output. High in normal operating mode when V
exceeds V
, other-
BATT
BOK
wise low. V
is checked continuously. Disabled and logic low while V is below V
.
BATT
CC
SW
3
4
—
—
RESET IN
(MAX794)
Reset Input. Connect to an external resistor divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V to 5.5V range.
SW
Power-Fail Comparator Input. When PFI is less than V
or when V
falls below V
,
SW
PFT
CC
PFI
PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).
Connect to V if unused.
CC
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V . Connect the base/gate of PNP/PMOS transistor to
5
6
7
3
4
BATT ON
GND
CC
BATT ON for I
requirements exceeding 75mA.
OUT
Ground
Power-Fail Comparator Output. When PFI is less than V
or when V
falls below
PFT
CC
—
PFO
V
, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
SW
tery freshness seal (see Battery Freshness Seal, and Power-Fail Comparator sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pullup current. It can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
8
9
—
—
—
MR
WDO
WDI
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V
< V
< V
, and low when V
RST
is below V
.
SW
CC
CC
SW
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
10
11
12
5
6
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused.
CE IN
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT remains low for 10µs or until CE IN goes
high, whichever occurs first. CE OUT is pulled up to OUT.
CE OUT
13
14
—
—
RESET
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
Early Power-Fail Warning Output. Low when V
falls to V . This output can be used to
LR
CC
LOWLINE
generate an NMI to provide early warning of imminent power failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V
for 200ms after either V
(WDO connected to MR), or MR goes low to high.
is below the reset threshold or when MR is a logic low. It remains low
CC
15
16
7
RESET
rises above the reset threshold, the watchdog triggers a reset
CC
Backup-Battery Input. When V falls below V
and V , OUT switches from V to
BATT CC
CC
SW
BATT. When V
rises above the reset threshold or above V , OUT reconnects to
BATT
CC
8
BATT
V
. V
can exceed V . Connect V , OUT, and BATT together if no battery is
CC BATT CC CC
used.
_______________________________________________________________________________________
7
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
out period (t ), the state of MR is ignored if PFO is exter-
RP
_______________Detailed Description
nally forced low to facilitate enabling the battery fresh-
ness seal. MR has an internal 70µA pullup current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec-
tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.
General Timing Characteristics
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the Selector Guide on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical V
rise and fall times.
CC
Manual Reset Input (MAX793/MAX794)
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
Reset Outputs
A microprocessor’s (µP’s) reset input starts the µP in a
known state. These MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code exe-
cution errors during power-up, power-down, and
remains asserted while MR is low, and for t (200ms)
RP
after it returns high. During the first half of the reset time-
V
LL
V
RST
V
SW
V
CC
5 s
V
(MAX793/MAX794)
LOWLINE
t
t
RP
V
(PULLED UP TO V
)
RESET
RESET
CC
RP
V
(MAX793/MAX794)
V
BATT
V
t
/
CE OUT
RP 2
V
WDO
25 s
25 s
(MAX793/MAX794)
V
BOK
(MAX793)
PFO
t /
RP 2
(MAX793/MAX794)
25 s
(PFO FOLLOWS PFI)
BATT ON
25 s
SHOWN FOR V = 0V to 3.3V, V
= 3.6V, CE IN = GND.
CC
BATT
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
MAX794: V
= V (V
/ V
)
RESET IN
CC RST IN RST
Figure 1. Timing Diagram, V
Rising
CC
8
_______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
brownout conditions. RESET is guaranteed to be a
If a brownout condition occurs (V
dips below the
CC
logic low for 0V < V
< V
, provided V
is
=
reset threshold), RESET goes low. Each time RESET is
CC
RST
BATT
BATT
greater than 1V. Without a backup battery (V
asserted, it stays low for the reset timeout period. Any
V
= V
), RESET is guaranteed valid for V
1V.
time V
goes below the reset threshold, the internal
CC
CC
Once V
OUT
CC
exceeds the reset threshold, an internal
timer restarts.
CC
timer keeps RESET low for the reset timeout period
The watchdog output (WDO) can also be used to initi-
ate a reset. See the Watchdog Output section.
(t ); after this interval, RESET becomes high imped-
RP
ance (Figure 2). RESET is an open-drain output, and
The RESET output is the inverse of the RESET output,
and it can both source and sink current.
requires a pullup resistor to V
(Figure 3). Use a
CC
4.7k to 1M pullup resistor that provides sufficient
current to assure the proper logic levels to the µP.
V
LL
V
RST
V
CC
V
SW
V
LOWLINE
4 s
(MAX793/MAX794)
V
RESET
20 s
20 s
(RESET PULLED UP TO V
)
CC
V
RESET
(MAX793/MAX794)
25 s
V
CE OUT
V
BATT
10 s
V
WDO
(MAX793/MAX794)
25 s
25 s
V
BOK
(MAX793)
V
PFO
(MAX793/MAX794)
25 s
25 s
V
BATT
V
BATT ON
SHOWN FOR V = 3.3V to 0V, V
= 3.6V, CE IN = GND, PFI = V .
CC
CC
BATT
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE
MAX794: V
= V (V
/ V
)
RESET IN
CC RST IN RST
Figure 2. Timing Diagram, V
Falling
CC
_______________________________________________________________________________________
9
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
(OPTIONAL)
Si9433DY
SILICONIX
V
RST
V
RST
3.3V
D
S
0.1 F
0.1 F
V
CC
PMOS
R1
R2
V
BATT ON OUT
CC
CMOS
RAM
RESET IN
CE OUT
t
RP
V
CC
RESET
PFO
MAX794
ADDRESS
DECODER
CE IN
A0-A15
I/O
BATT
0.1 F
3.6V
PFO STATE LATCHED,
WDI
FRESHNESS SEAL ENABLED.
(EXTERNALLY HELD AT 0V)
WDO
MR
LOWLINE
NMI
V
CC
RESET PULLED UP TO V
CC
+5V SUPPLY
FAILURE
4.7k
PFO
+5V
Figure 4. Battery Freshness Seal Enable Timing
RESET
RESET
Using the standard application circuit (Figure 3), the
reset threshold can be programmed anywhere in the
PFI
R1
R2
GND
+ 1
V
= V
RST IN
RST
(
)
range of V
(the battery switch threshold) to 5.5V.
SW
Reset is asserted when V
falls below V
.
SW
CC
Battery Freshness Seal
Figure 3. MAX794 Standard Application Circuit
The MAX793/MAX794’s battery freshness seal discon-
nects the backup battery from internal circuitry until it is
needed. This allows an OEM to ensure that the backup
battery connected to BATT is fresh when the final prod-
uct is put to use. To enable the freshness seal, connect
Reset Threshold
The MAX793T/MAX795T are intended for 3.3V systems
with a 5ꢀ power-supply tolerance and a 10ꢀ systems
tolerance. Except when MR is asserted, reset does not
assert as long as the power supply remains above
3.15V (3.3V - 5ꢀ). Reset is guaranteed to assert before
the power supply falls below 3.0V (3.3V - 10ꢀ).
a battery to BATT, ground PFO, bring V
above the
CC
reset threshold, and hold it there until reset is deassert-
ed following the reset timeout period, then bring V
CC
back down again (Figure 4). Once the battery fresh-
ness seal is enabled (disconnecting the backup battery
from the internal circuitry and anything connected to
The MAX793S/MAX795S are designed for 3.3V 10ꢀ
power supplies. Except when MR is asserted, they are
guaranteed not to assert reset as long as the supply
remains above 3.0V (3.0V is just above 3.3V - 10ꢀ).
Reset is guaranteed to assert before the power supply
falls below 2.85V (3.3V - 14ꢀ).
OUT), it remains enabled until V
RST
fere with battery freshness seal operation.
is brought above
CC
V
. Note that connecting PFO to MR does not inter-
BATT OK Output (MAX793)
The MAX793R/MAX795R are optimized to monitor 3.0V
BATT OK indicates the status of the backup battery.
When reset is not asserted, the MAX793 checks the
10ꢀ power supplies. Reset does not occur until V
CC
falls below 2.7V (3.0V - 10ꢀ), but is guaranteed to
occur before the supply falls below 2.55V (3.0V - 15ꢀ).
battery voltage continuously. If V
is below V
BOK
BATT
(2.0V min), BATT OK goes low; otherwise, it remains
pulled up to V . BATT OK also goes low when V
Program the MAX794’s reset threshold with an external
voltage divider to RESET IN. The reset-threshold toler-
ance is a combination of the RESET IN tolerance and
the tolerance of the resistors used to make the external
voltage divider. Calculate the reset threshold as follows:
CC
CC
goes below V
.
SW
Watchdog Input (MAX793/MAX794)
In the MAX793/MAX794, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within 1.6s, WDO goes low. The internal
1.6s timer is cleared and WDO returns high either when
V
RST
= V
(R1 / R2 + 1)
RST IN
10 ______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
V
RST
V
CC
V
CC
4.7k
MAX793/MAX794
t
RP
WDO
TO
P
RESET
RESET
WDO
MR
V
CC
t
WD
WDI
10 s
WDO
RESET
WDI
t
t
t
RP
RP
WP
WDO CONNECTED TO P INTERRUPT
RESET PULLED UP TO V
CC
Figure 5. Watchdog Timing Relationship
a reset occurs or when a transition (low-to-high or high-
to-low) takes place at WDI. As long as reset is assert-
ed, the timer remains cleared and does not count. As
soon as reset is released or WDI changes state, the
timer starts counting (Figure 5). WDI can detect pulses
as short as 100ns. Unlike the 5V MAX690 family, the
watchdog function cannot be disabled.
Figure 6. Generating a Reset on Each Watchdog Fault
Chip-Enable Signal Gating
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.
Watchdog Output (MAX793/MAX794)
In the MAX793/MAX794, WDO remains high (WDO is
pulled up to V ) if there is a transition or pulse at WDI
CC
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if V
is above V
SW
.
CC
is below V
SW
WDO is a logic low when V
.
CC
If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
circuitry to capture a watchdog fault indication. A con-
tinuous high or low on WDI causes 200ms reset pulses
to be issued every 1.6s.
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V
passes the
CC
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate disables at the moment CE IN
goes high, or 10µs after reset asserts, whichever
occurs first (Figure 8). This permits the current write
cycle to complete during power-down.
______________________________________________________________________________________ 11
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
The propagation delay through the CE transmission
gate depends on V , the source impedance of the
CC
drive connected to CE IN, and the loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50ꢀ point on CE IN to the 50ꢀ
point on CE OUT using a 50 driver and 50pF of load
capacitance (Figure 9). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low-output-impedance driver.
MAX793
MAX794
MAX795
OUT
P
CHIP-ENABLE
OUTPUT
CONTROL
RESET
GENERATOR
P
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a 46 resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pullup con-
nects CE OUT to OUT (Figure 8). This pullup turns off
when the transmission gate is enabled.
CE IN
CE OUT
N
Early Power-Fail Warning
(MAX793/MAX794)
Figure 7. Chip-Enable Transmission Gate
Critical systems often require an early warning indicat-
ing that power is failing. This warning provides time for
the µP to store vital data and take care of any additional
“housekeeping” functions, before the power supply
gets too far out of tolerance for the µP to operate reli-
ably. The MAX793/MAX794 offer two methods of
achieving this early warning. If access to the unregulat-
ed supply is feasible, the power-fail comparator input
(PFI) can be connected to the unregulated supply
The CE transmission gate remains disabled and CE IN
remains high impedance (regardless of CE IN activity)
for the first half of the reset timeout period (t / 2), any
RP
time a reset is generated. While disabled, CE IN is high
impedance. When the CE transmission gate is enabled,
the impedance of CE IN appears as a 46 resistor in
series with the load at CE OUT.
V
RST
V
RST
V
RST
V
RST
V
CC
V
SW
V
SW
CE OUT
V
BATT
V
BATT
10 s
V
CC
t
RP
/2
t
RP
RESET
(PULLED TO V
)
CC
CE IN
V
BATT
= 3.6V
RESET PULLED UP TO V
CC
Figure 8. Chip-Enable Timing
12 ______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
pulled to V . Use LOWLINE to provide an NMI to the
CC
V
CC
CC
µP when power begins to fall.
V
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered and before reset asserts. If the system
BATT
3.6V
MAX793
MAX794
MAX795
must also contend with a more rapid V
fall time, such
CC
25 EQUIVALENT
SOURCE IMPEDANCE
as when the main battery is disconnected or a high-
side switch is opened during normal operation, use
50 CABLE
capacitance on the V
line to provide time to execute
CC
CE OUT
CE IN
the shutdown routine (Figure 11).
50
50pF
C *
First, calculate the worst-case time required for the sys-
tem to perform its shutdown routine. Then, with the worst-
case shutdown time, the worst-case load current, and the
50
L
GND
minimum low-line to reset threshold (V min), calculate
LR
the amount of capacitance required to allow the shut-
down routine to complete before reset is asserted:
*C INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
L
C
> I
x t
/ V
SHDN LR
HOLD
LOAD
Figure 9. CE Propagation Delay Test Circuit
where I
is the current being drained from the
LOAD
capacitor, V is the low-line to reset threshold differ-
through a voltage divider, with the power-fail compara-
tor output (PFO) providing the NMI to the µP (Figure
10). If there is no easy access to the unregulated sup-
ply, the LOWLINE output can be used to generate an
NMI to the µP (see LOWLINE Output section).
LR
ence (V - V
), and t
is the time required for
SHDN
LL
RST
the system to complete an orderly shutdown routine.
Power-Fail Comparator (MAX793/MAX794)
The MAX793/MAX794’s PFI input is compared to an
internal reference. If PFI is less than the power-fail
LOWLINE Output (MAX793/MAX794)
threshold (V
), PFO goes low. The power-fail com-
The low-line comparator monitors V
with a threshold
PFT
CC
parator is intended for use as an undervoltage detector
to signal a failing power supply (Figure 12). However,
the comparator does not need to be dedicated to this
function because it is completely separate from the rest
of the circuitry.
voltage typically 45mV above the reset threshold (10mV
of hysteresis) for the MAX793, and 15mV above RESET
IN (4mV of hysteresis) for the MAX794. For normal
operation (V
above the reset threshold), LOWLINE is
CC
UNREGULATED
SUPPLY
3.0V OR 3.3V
REGULATOR
3.0V OR 3.3V
REGULATOR
TO P NMI
LOWLINE
V
CC
C
HOLD
V
CC
MAX793
MAX794
MAX793
MAX794
R1
TO P NMI
PFO
PFI
C
> I
x t
HOLD LOAD SHDN
V
LR
GND
R2
GND
Figure 10. Using the Power-Fail Comparator to Generate
Power-Fail Warning
Figure 11. Using LOWLINE to Provide Power-Fail Warning
to the µP
______________________________________________________________________________________ 13
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
V
IN
3.0V OR 3.3V
3.0V OR 3.3V
V
V
CC
CC
R1
R2
R1
R2
MAX793
MAX794
MAX793
MAX794
PFI
PFO
PFI
PFO
MR
GND
GND
V
IN
V
V
CC
CC
PFO
PFO
V
V
IN
IN
V
V
V
V
H
L
TRIP
0V
TRIP
1
1
V
CC
R1
R1 + R2
R2
+
–
V
= R2 (V + V
PFT
)
TRIP
PFH
1
V
V
= V
PFT
(
)
CC
TRIP
(
)
R1 R2
WHERE V
V
= 1.237V
= 10mV
PFT
PFH
1
V
R1 + R2
R2
+
–
V = R2 (V
)
PFT
L
= (V + V
PFT
)
PFH
(
)
H
(
)
R1 R2
R1
NOTE: V
TRIP,
V ARE NEGATIVE
L
(a)
(b)
Figure 12. Using the Power-Fail Comparator to Monitor an Additional Power Supply: (a) V Is Negative, (b) V Is Positive
IN
IN
V
is greater than V , or when V
falls below
CC
The power-fail comparator turns off and PFO goes low
when V falls below V on power-down. During the
BATT
CC
1.75V (typ) regardless of the BATT voltage.
CC
SW
first half of the reset timeout period (t ), PFO is forced
RP
Switchover at V ensures that battery-backup mode is
entered before V
SW
OUT
high, irrespective of V . At the beginning of the sec-
PFI
gets too close to the 2.0V mini-
ond half of t , the power-fail comparator is enabled
RP
mum required to reliably retain data in most CMOS
RAM, (switchover at higher V voltages would
and PFO follows PFI. If the comparator is unused, con-
nect PFI to VCC and leave PFO unconnected. PFO can
be connected to MR so that a low voltage on PFI gener-
ates a reset (Figure 12b). In this configuration, when
CC
decrease backup-battery life). When V
recovers,
CC
switchover is deferred either until V
crosses V
if
BATT
CC
CC
V
is below V
, or when V
RST
rises above the
. This
BATT
the monitored voltage causes PFI to fall below V
,
PFT
reset threshold (V
) if V
is above V
RST
BATT
RST
CC
PFO pulls MR low, causing a reset to be asserted.
Reset remains asserted as long as PFO holds MR low,
and for 200ms after PFO pulls MR high when the moni-
tored supply is above the programmed threshold.
power-up switchover technique prevents V
from
charging the backup battery through OUT when using
an external transistor driven by BATT ON. OUT con-
nects to V
when V
through a 4 (max) PMOS power switch
CC
crosses the reset threshold (Figure 13).
CC
Backup-Battery Switchover
In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a
backup battery installed at BATT, the devices automati-
BATT ON (MAX793/MAX794)
BATT ON is high when OUT is connected to BATT.
Although BATT ON can be used as a logic output to
indicate the battery switchover status, it is most often
used as a gate or base drive for an external pass tran-
sistor for high-current applications (see Driving an
External Switch with BATT ON in the Applications
cally switch RAM to backup power when V
falls. In
CC
order to allow the backup battery (e.g., a 3.6V lithium
cell) to have a higher voltage than V , this family of µP
CC
supervisors (designed for 3.3V and 3V systems) does
not always connect BATT to OUT when V
is
BATT
Information section). When V
exceeds V
on
RST
CC
greater than V . BATT connects to OUT (through a
CC
power-up, BATT ON sinks 3.2mA at 0.4V. In battery-
140 switch) either when V
falls below V
and
SW
CC
backup mode, this terminal sources 100µA from BATT.
14 ______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
to V , the collector to OUT, and the base to BATT ON
CC
(Figure 14a). No current-limiting resistor is required, but
a resistor connecting the base of the PNP to BATT ON
3.3V
V
RST
can be used to limit the current drawn from V , pro-
CC
V
CC
longing battery life in portable equipment.
V
SW
If you are using a PMOS transistor, however, it must be
connected backwards from the traditional method.
Connect the gate to BATT ON, the drain to V , and
CC
the source to OUT (Figure 14b). This method orients
3.6V
3.6V
the body diode from V
to OUT and prevents the
3.3V
CC
backup battery from discharging through the FET when
its gate is high. Two PMOS transistors in the Siliconix
V
OUT
LITTLE FOOT™ series are specified with V
down to
GS
V
= 3.6V
BATT
-2.7V. The Si9433DY has a maximum 100m drain-
source on-resistance with 2.7V of gate drive and a 2A
drain-source current. The Si9434DY specifies a 60m
drain-source on-resistance with 2.7V of gate drive and
a 5.1A drain-source current.
Figure 13. Battery Switchover Timing
Table 1. Input and Output Status in
Battery-Backup Mode
Using a SuperCap™ as a Backup
Power Source
PIN NAME
STATUS
Connected to BATT through an internal
140 switch
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their size.
Figure 15 shows two ways to use a SuperCap as a
backup power source. The SuperCap can be connect-
ed through a diode to the 3V input (Figure 15a); or, if a
5V supply is also available, the SuperCap can be
charged up to the 5V supply (Figure 15b), allowing a
OUT
V
Disconnected from OUT
Pulled up to BATT
Logic low
CC
BATT ON
BATT OK
PFI
Disabled
Logic low
PFO
longer backup period. Since V
can exceed V
CC
BATT
Disabled, but still pulled up to V
CC
while V
is above the reset threshold, there are no
MR
CC
special precautions when using these µP supervisors
with a SuperCap.
Logic low
Disabled
Logic low
WDO
WDI
RESET
RESET
BATT
Operation without a
Backup Power Source
These µP supervisors were designed for battery-
backed applications. If a backup battery is not used,
Pulled up to V
CC
Connected to OUT
Logic low
LOWLINE
CE IN
CE OUT
connect BATT, OUT, and V
together, or use a differ-
CC
High impedance
Pulled to BATT
ent µP supervisor. See the µP Supervisory Circuits table
at the end of this data sheet.
__________Applications Information
Replacing the Backup Battery
The backup power source can be removed while V
CC
These µP supervisory circuits are not short-circuit pro-
remains valid, without danger of triggering a reset
pulse, provided that BATT is decoupled with a 0.1µF
tected. Shorting V
to ground, excluding power-up
OUT
transients such as charging a decoupling capacitor,
capacitor to ground. As long as V
stays above the
CC
destroys the device. Decouple both V and BATT
pins to ground by placing 0.1µF ceramic capacitors as
CC
reset threshold, battery-backup mode cannot be
entered.
close to the device as possible.
Driving an External Switch with BATT ON
BATT ON can be directly connected to the base of a
PNP transistor or the gate of a PMOS transistor. The
PNP connection is straightforward: connect the emitter
™ LITTLE FOOT is a trademark of Siliconix Inc.
SuperCap is a trademark of Baknor Industries.
______________________________________________________________________________________ 15
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
PMOS FET
BODY DIODE
TO CMOS RAM
3.0V OR 3.3V
S
D
G
V
BATT ON OUT
V
BATT ON OUT
CC
CC
MAX793
MAX794
MAX795
MAX793
MAX794
MAX795
GND
GND
(a)
(b)
Figure 14. Driving an External Transistor with BATT ON
3.0V OR 3.3V
+5V
3.0V OR
3.3V
V
MAX793
MAX794
OUT
TO STATIC
RAM
V
MAX793
MAX794
OUT
TO STATIC
RAM
CC
CC
V
V
CC
CC
1N4148
1N4148
0.47F
BATT
RESET
TO P
BATT
RESET
TO
P
0.47F
GND
GND
(a)
Figure 15. Using a SuperCap™ as a Backup Source
(b)
both above (V ) and below (V ) the original trip point
H
L
(V
).
TRIP
Adding Hysteresis to the Power-Fail
Comparator (MAX793/MAX794)
The power-fail comparator has a typical input hystere-
sis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section Monitoring
an Additional Power Supply).
Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (V )
L
),
to coincide with the trip point without hysteresis (V
TRIP
so the entire hysteresis window occurs above V
.
TRIP
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a thresh-
old. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82k so it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees V
when
PFT
V
IN
falls to its trip point (V
). R3 adds the additional
TRIP
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends
16 ______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
V
V
IN
IN
R1
R2
V
V
CC
R1
R2
CC
PFI
MAX793
MAX794
MAX793
MAX794
PFI
R3
R3
C1*
C1*
PFO
PFO
GND
GND
*OPTIONAL
*OPTIONAL
TO
P
TO
P
PFO
PFO
0V
V
0V
V
IN
IN
V
V
H
V
V
TRIP
L
H
0V
0V
V
TRIP
R1 + R2
V
= V
(
)
)
R1 + R2
R2
TRIP
PFT
R2
V
= V
PFT
(
)
TRIP
WHERE V
V
= 1.237V
= 10mV
PFT
PFH
V
1
1
1
D
+
+
–
V
= R1 (V + V
PFT
1
1
1
(
)
H
PFH
V
= (V + V ) (R1)
H
PFT
PFH
R3
R1 R2 R3
+
+
(
)
R1 R2 R3
WHERE V
= 1.237V
= 10mV
PFT
PFH
1
1
1
V
CC
+
+
–
V = R1 V
(
)
L
PFT
V
R1 R2 R3
R3
V
= DIODE FORWARD VOLTAGE DROP
D
(a)
(b)
V
= V
L
TRIP
Figure 16. Adding Hysteresis to the Power-Fail Comparator: (a) Symmetrical Hysteresis, (b) Hysteresis Only on Rising V
IN
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
V
negative supplies using a resistor voltage divider to
PFI. PFO can be used to generate an interrupt to the µP
or to cause reset to assert (Figure 12).
CC
V
V
CC
CC
Interfacing to µPs with
Bidirectional Reset Pins
RESET
N
Since the RESET output is open drain, the MAX793/
MAX794/MAX795 interface easily with µPs that have
bidirectional reset pins, such as the Motorola 68HC11.
Connecting the RESET output of the µP supervisor
directly to the RESET input of the microcontroller with a
single pullup resistor allows either device to assert
reset (Figure 17).
RESET
RESET
GENERATOR
P
MAX793
MAX794
MAX795
Negative-Going V
Transients
CC
These supervisors are relatively immune to short-dura-
tion negative-going V transients (glitches) while issu-
CC
ing resets to the µP during power-up, power-down, and
GND
GND
brownout conditions. Therefore, resetting the µP when
V
experiences only small glitches is usually not rec-
CC
ommended.
Figure 17. Interfacing to µPs with Bidirectional Reset I/O
______________________________________________________________________________________ 17
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Figure 18 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
Watchdog Software Considerations
There is a way to help the watchdog timer monitor soft-
ware execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than pulsing the watchdog input
high-low-high or low-high-low. This technique avoids a
stuck loop, in which the watchdog timer would continue
to be reset within the loop, keeping the watchdog from
timing out. Figure 19 shows an example of a flow dia-
gram where the I/O driving the watchdog input is set
high at the beginning of the program, set low at the
beginning of every subroutine or loop, then set high
again when the program returns to the beginning. If the
program should hang in any subroutine, the problem
would quickly be corrected, since the I/O is continually
set low and the watchdog timer is allowed to time out,
causing a reset or interrupt to be issued.
going V
pulses, starting at 3.3V and ending below
CC
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
pulse width a negative-going V
transient can typically
CC
have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V
transient that
CC
goes 40mV below the reset threshold and lasts for 10µs
or less does not cause a reset pulse to be issued.
A 0.1µF bypass capacitor mounted close to the V
pin provides additional transient immunity.
CC
100
90
80
70
60
50
40
30
START
SET WDI
HIGH
PROGRAM
CODE
20
10
0
Subroutine or
Program Loop
10 20 30 40 50 60 70 80 90 100
RESET COMPARATOR OVERDRIVE, V
- V (mV)
CC
RST
SET WDI LOW
Figure 18. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
RETURN
Figure 19. Watchdog Flow Diagram
18 ______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_Ordering Information (continued)
_________________Pin Configurations
PART*
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
8 Plastic DIP
8 SO
MAX794CPE
MAX794CSE
MAX794EPE
MAX794ESE
MAX795_CPA
MAX795_CSA
MAX795_EPA
MAX795_ESA
TOP VIEW
OUT
BATT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RESET
LOWLINE
RESET
CE OUT
CE IN
CC
(RESET IN) BATT OK
PFI
BATT ON
GND
MAX793
MAX794
8 Plastic DIP
8 SO
*The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold volt-
age range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
PFO
WDI
MR
WDO
DIP / Narrow SO
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
BATT
RESET
CE OUT
CE IN
OUT
1
8
7
6
5
V
2
3
4
CC
MAX795
BATT ON
GND
DIP/SO
( ) ARE FOR MAX794
___________________Chip Information
TRANSISTOR COUNT: 1271
______________________________________________________________________________________ 19
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX794ESE-T
Power Supply Management Circuit, Adjustable, 2 Channel, CMOS, PDSO16, 0.150 INCH, MS-012AC, SOIC-16
MAXIM
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