MAX5864ETM [ROCHESTER]
TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48;
| 型号： | MAX5864ETM |
| 厂家： | 
Rochester Electronics |
| 描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48 蜂窝 电信 电信集成电路 |
| 文件： | 总27页 (文件大小：2762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2915; Rev 1; 10/03
Ultra-Low-Power, High-Dynamic-
Performance, 22Msps Analog Front End
General Description
Features
o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
o Ultra-Low Power
The MAX5864 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5864 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
42mW at f
34mW at f
= 22MHz (Transceiver Mode)
= 15.36MHz (Transceiver Mode)
CLK
CLK
Low-Current Idle and Shutdown Modes
o Excellent Dynamic Performance
accept 1V
full-scale signals. Typical I-Q channel
P-P
48.5dB SINAD at f = 5.5MHz (ADC)
IN
phase matching is 0.1° and amplitude matching is
71.7dB SFDR at f
= 2.2MHz (DAC)
OUT
0.03dB. The ADCs feature 48.5dB SINAD and 69dBc
spurious-free dynamic range (SFDR) at f = 5.5MHz and
IN
o Excellent Gain/Phase Match
f
= 22Msps. The DACs’ analog I-Q outputs are fully
CLK
0.1° Phase, 0.03dB Gain at f = 5.5MHz (ADC)
IN
differential with 400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase match is
0.15° and amplitude match is 0.05dB. The DACs also
feature dual 10-bit resolution with 71.7dBc SFDR, and
o Internal/External Reference Option
o +1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
57dB SNR at f
= 2.2MHz and f
= 22MHz.
OUT
CLK
o Multiplexed Parallel Digital Input/Output for
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
ADCs/DACs
o Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
o Evaluation Kit Available (Order MAX5865EVKIT)
tion. The typical operating power is 42mW at f
=
CLK
22Msps with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5864 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5864 operates on a +2.7V to +3.3V ana-
log power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
5.6mA in idle mode and 1µA in shutdown mode. The
MAX5864 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Functional Diagram
IA+
ADC
IA-
ADC
OUTPUT
MUX
DA0–DA7
CLK
QA+
QA-
ADC
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
ID+
ID-
DAC
DAC
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
DAC
INPUT
MUX
DD0–DD9
QD+
QD-
Ordering Information
REFP
COM
REFN
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
SERIAL
INTERFACE
AND SYSTEM
CONTROL
48 Thin QFN-EP*
(7mm x 7mm)
DIN
SCLK
CS
MAX5864ETM
MAX5864E/D
REF AND
BIAS
REFIN
Dice**
*EP = Exposed paddle.
**Contact factory for dice specifications.
MAX5864
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ABSOLUTE MAXIMUM RATINGS
V
to GND, OV
to OGND................................-0.3V to +3.3V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
GND to OGND.......................................................-0.3V to +0.3V
IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN,
REFIN, COM to GND..............................-0.3V to (V
DD0–DD9, SCLK, DIN, CS, CLK,
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) ..........2.1W
Thermal Resistance θ .................................................+38°C/W
JA
+ 0.3V)
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DA0–DA7 to OGND .............................-0.3V to (OV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
2.7
1.8
3.0
3.3
V
V
DD
OV
V
DD
DD
ADC operating mode, f = 5.5MHz, f
=
IN
CLK
14
16.5
22MHz, DAC operating mode, f
= 2.2MHz
OUT
ADC operating mode, f = 5.5MHz, f
IN
=
CLK
=
15.36MHz, DAC operating mode, f
11.4
OUT
2.2MHz
ADC operating mode (Rx), f = 5.5MHz,
IN
f
= 15.36MHz, DAC off, DAC digital
8.25
8
CLK
mA
inputs at zero or DV
DD
V
Supply Current
DD
DAC operating mode (Tx), f
f
= 2.2MHz,
OUT
= 15.36MHz, ADC off
CLK
Standby mode, DAC digital inputs and CLK
at zero or OV
2.0
6.7
DD
Idle mode, DAC digital inputs at zero or
OV , f = 22MHz
DD CLK
Shutdown mode, digital inputs and CLK at
zero or OV , CS = OV
1
2.3
20.6
1
µA
DD
DD
ADC operating mode, f = 5.5MHz, f
=
IN
CLK
mA
22MHz, DAC operating mode, f
= 2.2MHz
OUT
Idle mode, DAC digital inputs at zero or
OV = 22MHz
OV
Supply Current
DD
f
DD, CLK
µA
Shutdown mode, DAC digital inputs and
CLK at zero or OV , CS = OV
DD
DD
2
_______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
ADC DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.15
0.15
0.24
0.77
0.03
3
DNL
No missing codes over temperature
Residual DC offset error
LSB
5
5
%FS
%FS
dB
Gain Error
Includes reference error
DC Gain Matching
Offset Matching
0.25
LSB
Gain Temperature Coefficient
59
ppm/°C
Offset error (V
5%)
0.2
DD
Power-Supply Rejection
PSRR
LSB
Gain error (V
5%)
0.07
DD
ADC ANALOG INPUT
Input Differential Range
V
Differential or single-ended inputs
Switched capacitor load
0.512
V
V
ID
Input Common-Mode Voltage
Range
V
/ 2
DD
R
C
245
5
kΩ
IN
Input Impedance
pF
IN
ADC CONVERSION RATE
Maximum Clock Frequency
f
(Note 2)
22
MHz
CLK
Channel I
Channel Q
5
Clock
cycles
Data Latency
5.5
ADC DYNAMIC CHARACTERISTICS (Note 3)
f
f
f
f
f
f
f
f
= 5.5MHz
= 11MHz
= 5.5MHz
= 11MHz
= 5.5MHz
= 11MHz
= 5.5MHz
= 11MHz
47
46.5
58
48.6
48.6
48.5
48.5
69
IN
IN
IN
IN
IN
IN
IN
IN
Signal-to-Noise Ratio
SNR
SINAD
SFDR
dB
dB
Signal-to-Noise and Distortion
Ratio
Spurious-Free Dynamic Range
dBc
71.5
-70.3
-75.5
-64
Third-Harmonic Distortion
Intermodulation Distortion
HD3
IMD
IM3
dBc
dBc
dBc
f = 2MHz, -7dBFS; f = 2.01MHz, -7dBFS
1
2
Third-Order Intermodulation
Distortion
f = 2MHz, -7dBFS; f = 2.01MHz, -7dBFS
1
-67
2
f
f
= 5.5MHz
= 11MHz
-68.2
-68
-57
IN
IN
Total Harmonic Distortion
THD
dBc
_______________________________________________________________________________________
3
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
Small-Signal Bandwidth
Large-Signal Bandwidth
Aperture Delay
SYMBOL
SSBW
CONDITIONS
MIN
TYP
440
440
3.3
2.7
2
MAX
UNITS
MHz
MHz
ns
A
A
= -20dBFS
= -0.5dBFS
IN
IN
FBW
Aperture Jitter
ps
RMS
Overdrive Recovery Time
1.5 × full-scale input
ns
ADC INTERCHANNEL CHARACTERISTICS
f
= 5.5MHz at -0.5dBFS, f
= 0.3MHz at
INX
INY
Crosstalk Rejection
-75
dB
-0.5dBFS (Note 5)
Amplitude Matching
Phase Matching
f
f
= 5.5MHz at -0.5dBFS (Note 6)
= 5.5MHz at -0.5dBFS (Note 6)
0.03
0.1
dB
IN
IN
Degrees
DAC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Zero-Scale Error
INL
DNL
1
0.5
3
Guaranteed monotonic
Residual DC offset
Full-Scale Error
Include Reference Error
-35
+35
22
DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
Noise over Nyquist
(Note 2)
Msps
N
N
f
= 2.2MHz, f
= 22MHz
-128.4
-131.5
dBc/Hz
D
OUT
CLK
CLK
Output-of-Band Noise Power
Density
f
= 1.2MHz, f
= 15.36MHz, offset =
OUT
dBc/Hz
O
10MHz
WCDMA at offset = 5MHz, f
15.36Msps
=
CLK
Adjacent Channel Power Ratio
Glitch Impulse
ACPR
57
dB
pVs
dBc
10
f
f
= 22MHz
f
f
= 2.2MHz
= 200kHz
60
71.7
72.5
CLK
CLK
OUT
OUT
Spurious-Free Dynamic Range
SFDR
THD
SNR
= 15.36MHz
Total Harmonic Distortion
(to Nyquist)
f
f
= 22MHz, f
= 2.2MHz
= 2.2MHz
-70
57
-59
dB
dB
CLK
CLK
OUT
OUT
Signal-to-Noise Ratio
(to Nyquist)
= 22MHz, f
DAC INTERCHANNEL CHARACTERISTICS
DAC-to-DAC Output Isolation
f
f
= 2.2MHz, f
= 2.0MHz
OUTX, Y
80
dB
dB
OUTX, Y
Gain Mismatch Between DAC
Outputs
= 2.2MHz, f
= 22MHz
= 22MHz
0.05
OUT
OUT
CLK
Phase Mismatch Between DAC
Outputs
f
= 2.2MHz, f
0.15
Degrees
CLK
4
_______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
DAC ANALOG OUTPUT
Full-Scale Output Voltage
Output Common-Mode Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
400
mV
V
FS
1.29
1. 5
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC f = f
= 5.5MHz, DAC f
=
INI
INQ
OUTI
ADC-DAC Isolation
75
dB
f
= 2.2MHz, f
= 22MHz
OUTQ
CLK
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
t
Figure 3 (Note 4)
Figure 3 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
7.4
6.9
9
9
ns
ns
ns
ns
DOI
CLK Fall to Q-ADC Channel-Q
Output Data Valid
t
DOQ
I-DAC Data to CLK Fall Setup
Time
t
10
10
DSI
Q-DAC Data to CLK Rise Setup
Time
t
DSQ
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold Time
Clock Duty Cycle
t
Figure 4 (Note 4)
Figure 4 (Note 4)
0
0
ns
ns
%
DHI
t
DHQ
50
15
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
%
20% to 80%
2.6
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
t
Figure 5 (Note 4)
10
ns
CSS
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Period
t
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
10
0
ns
ns
ns
ns
ns
ns
ns
DS
DH
CH
t
t
25
25
50
0
t
t
t
CL
CP
CS
SCLK to CS Setup Time
CS High Pulse Width
t
80
CSW
MODE RECOVERY TIMING CHARACTERISTICS
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
20
40
Shutdown Wake-Up Time
t
µs
WAKE,SD
From shutdown to Tx mode, Figure 6, DAC
settles to within 1 LSB error
_______________________________________________________________________________________
5
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
From idle to Rx mode with CLK present
during idle, Figure 6, ADC settles to within
1dB SINAD
10
Idle Wake-Up Time (with CLK)
t
µs
WAKE,ST
From idle to Tx mode with CLK present
during idle, Figure 6, DAC settles to 10 LSB
error
10
From standby to Rx mode, Figure 6, ADC
settles to within 1dB SINAD
10
40
Standby Wake-Up Time
t
µs
WAKE,St1
From standby to Tx mode, Figure 6, DAC
settles to 10 LSB error
Enable Time from Xcvr or Tx to Rx
Enable Time from Xcvr or Rx to Tx
t
ADC settles to within 1dB SINAD
DAC settles to 1 LSB error
10
10
µs
µs
ENABLE, Rx
t
ENABLE, Tx
INTERNAL REFERENCE (REFIN = V . V
, V
, and V
are generated internally)
DD REFP REFN
COM
COM
Positive Reference
Negative Reference
V
V
- V
0.256
V
V
REFP
REFN
- V
-0.256
COM
V
/ 2
V
/ 2
DD
DD
Common-Mode Output Voltage
V
V
/ 2
DD
V
V
COM
- 0.15
+ 0.15
Differential Reference Output
V
V
- V
REFN
+0.49 +0.512 +0.534
REF
REFP
Differential Reference
Temperature Coefficient
REFTC
30
ppm/°C
Maximum REFP/REFN/COM
Source Current
I
2
2
mA
mA
SOURCE
Maximum REFP/REFN/COM
Sink Current
I
SINK
BUFFERED EXTERNAL REFERENCE (REFIN = 1.024V. V
, V
, and V
are generated internally)
COM
REFP REFN
Reference Input
V
1.024
0.512
V
V
V
REFIN
Differential Reference Output
Common-Mode Output Voltage
V
V
- V
REFP REFN
DIFF
V
V
/ 2
COM
DD
Maximum REFP/REFN/COM
Source Current
I
2
mA
mA
SOURCE
Maximum REFP/REFN/COM
Sink Current
I
2
SINK
REFIN Input Resistance
REFIN Input Current
>500
-0.7
kΩ
µA
DIGITAL INPUTS (CLK, SCLK, DIN, CS, DD0–DD9)
0.7 x
OV
Input High Threshold DD0–DD9, CLK, SCLK, DIN, CS
V
V
INH
DD
6
_______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz, ADC input amplitude = -0.5dBFS,
DD
DD
L
CLK
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
= C
= 0.33µF, Xcvr mode, unless
REFP
REFN
COM
otherwise noted. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 x
Input Low Threshold
V
DD0–DD9, CLK, SCLK, DIN, CS
V
INL
OV
DD
DD0–DD9, CLK, SCLK, DIN, CS = OGND or
OV
Input Leakage
DI
5
µA
pF
IN
DD
Input Capacitance
DC
5
IN
DIGITAL OUTPUTS (DA0–DA7)
0.2 x
OV
Output Voltage Low
Output Voltage High
V
I
I
= 200µA
SINK
V
V
OL
DD
0.8 x
OV
V
= 200µA
SOURCE
OH
DD
Tri-State Leakage Current
I
5
µA
pF
LEAK
Tri-State Output Capacitance
C
5
OUT
Note 1: Specifications from T = +25°C to +85°C are guaranteed by product tests. Specifications from T = +25°C to -40°C are
A
A
guaranteed by design and characterization.
Note 2: The minimum clock frequency for the MAX5864 is 7.5MHz.
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4: Guaranteed by design and characterization.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(V
= DV
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz 50% duty cycle, ADC
DD
DD
DD
L
CLK
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
=
REFP
REFN
C
COM
= 0.33µF, Xcvr mode, T = +25°C, unless otherwise noted.)
A
ADC CHANNEL-IA FFT PLOT
ADC CHANNEL-QA FFT PLOT
ADC CHANNEL-IA TWO-TONE FFT PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
f
f
f
= 22MHz
f
f
f
= 22MHz
f
1
= 22MHz
CLK
IA
QA
CLK
IA
QA
CLK
f = 1.8MHz
QA
IA
QA
7
= 5.50885MHz
= 5.50885MHz
-20
= 7.9787MHz
= 7.9787MHz
f = 2.2MHz
2
F
F
2
1
A
= A = -0.5dBFS
A
= A = -0.5dBFS
A
-7dBFS PER TONE
IA
QA
IA
QA
-30
IA =
8192-POINT
DATA RECORD
8192-POINT
DATA RECORD
8192-POINT
-40
DATA RECORD
-50
-60
HD2
HD3
HD3
HD2
IA
-70
-80
-90
-100
-110
-120
0
1
2
3
4
5
6
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9 10 11
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
7
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Typical Operating Characteristics (continued)
(V
= DV
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz 50% duty cycle, ADC
DD
DD
DD
L
CLK
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, Xcvr mode, T = +25°C, unless otherwise noted.)
A
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCY
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
ADC CHANNEL-QA TWO-TONE FFT PLOT
50
49
48
47
46
45
44
43
42
0
50
49
48
47
46
45
44
43
42
f
1
= 22MHz
CLK
f = 1.8MHz
IA
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
IA
f = 2.2MHz
2
F
F
2
1
A
-7dBFS PER TONE
IA =
8192-POINT
QA
DATA RECORD
QA
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9 10 11
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
80
75
70
65
60
55
50
80
75
70
65
60
55
50
45
40
-50
-55
-60
-65
-70
-75
-80
SINGLE ENDED
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC SIGNAL-TO-NOISE-RATIO AND
DISTORTION vs. ANALOG INPUT POWER
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
ADC SIGNAL-TO-NOISE-RATIO
vs. ANALOG INPUT POWER
60
50
40
30
20
10
0
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
60
50
40
30
20
10
0
f
= 5.50885
f = 5.50885
IN
f
= 5.50885
IN
IN
QA
QA
IA
IA
-24
-20
-16
-12
-8
-4
0
-24
-20
-16
-12
-8
-4
0
-24
-20
-16
-12
-8
-4
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
8
_______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Typical Operating Characteristics (continued)
(V
= DV
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz 50% duty cycle, ADC
DD
DD
DD
L
CLK
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, Xcvr mode, T = +25°C, unless otherwise noted.)
A
ADC SPURIOUS -FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
ADC SIGNAL-TO-NOISE RATIO
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE
vs. SAMPLING RATE
80
50
49
48
47
46
45
50
49
48
47
46
45
f
= 5.50885
IN
75
70
65
60
55
50
45
40
35
30
QA
IA
QA
IA
f
= 5.50885
19
f
IN
= 5.50885
19
IN
-24
-20
-16
-12
-8
-4
0
7
10
13
16
22
7
10
13
16
22
ANALOG INPUT POWER (dBFS)
SAMPLING RATE (MHz)
SAMPLING RATE (MHz)
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
80
75
70
65
65
55
50
50
49
48
47
46
45
-50
-55
-60
-65
-70
-75
-80
f = 5.50885
IN
f
= 5.50885
IA
f
= 5.50885
IN
IN
QA
7
10
13
16
19
22
35
40
45
50
55
60
65
7
10
13
16
19
22
SAMPLING RATE (MHz)
CLOCK DUTY CYCLE (%)
SAMPLING RATE (MHz)
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
50
49
48
47
46
45
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
80
75
70
65
60
55
50
f
= 5.50885
IN
IA
QA
f
= 5.050885
60
f
= 5.050885
60 65
IN
IN
35
40
45
50
55
60
65
35
40
45
50
55
65
35
40
45
50
55
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
_______________________________________________________________________________________
9
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Typical Operating Characteristics (continued)
(V
= DV
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz 50% duty cycle, ADC
DD
DD
DD
L
CLK
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, Xcvr mode, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SAMPLING RATE
ADC OFFSET ERROR vs. TEMPERATURE
ADC GAIN ERROR vs. TEMPERATURE
12
10
8
0
2.0
1.5
1.0
0.5
0
Rx MODE ONLY
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
QA
I
VDD
6
IA
4
I
OVDD
2
-0.5
-1.0
0
7
10
13
16
19
22
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SAMPLING RATE (MHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT POWER
DAC SPRURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
DAC SPRURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
90
85
80
75
70
65
60
80
70
60
50
40
30
20
90
85
80
75
70
65
60
f
= 2MHz
OUT
f
= f /10
OUT CLK
0
2
4
6
8
10
-30
-25
-20
-15
-10
-5
0
7
10
13
16
19
22
FREQUENCY (MHz)
OUTPUT POWER (dBFS)
SAMPLING RATE (MHz)
DAC CHANNEL-ID TWO TONE
SPECTRAL PLOT
DAC CHANNEL-ID SPECTRAL PLOT
DAC CHANNEL-QD SPECTRAL PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f = 2.0MHz, f = 2.2MHz, -7dBFS
1
2
f
ID
= 2.2MHz
f
= 2.2MHz
QD
f
1
f
2
1
3
5
7
9
11
1
3
5
7
9
11
1
3
5
7
9
11
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
10 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Typical Operating Characteristics (continued)
(V
= DV
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 22MHz 50% duty cycle, ADC
DD
DD
DD
L
CLK
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, Xcvr mode, T = +25°C, unless otherwise noted.)
A
DAC CHANNEL-QD TWO-TONE
SUPPLY CURRENT vs. SAMPLING RATE
SPECTRAL PLOT
DAC ACPR SPECTRAL PLOT
0
16
14
12
10
8
-20
-30
-40
-50
-60
-70
-80
-90
f = 2.0MHz, f = 2.2MHz, -7dBFS
1
2
Xcrv MODE
f
= 15.36Msps
CLK
WCDMA
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
I
VDD
f
1
f
2
6
4
-100
-110
-120
I
OVDD
2
0
1
3
5
7
9
11
7
10
13
16
19
22
CENTER = 4MHz, SPAN = 7MHz
FREQUENCY (MHz)
SAMPLING RATE (MHz)
ADC DIFFERENTIAL NONLINEARITY
ADC INTEGRAL NONLINEARITY
DAC INTEGRAL NONLINEARITY
0.5
0.4
0.5
0.4
1.0
0.8
0.3
0.3
0.6
0.2
0.2
0.4
0.1
0.1
0.2
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
-1.0
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
REFERENCE OUTPUT VOLTAGE
vs.TEMPERATURE
DAC DIFFERENTIAL NONLINEARITY
0.5
0.4
0.520
0.515
0.510
0.505
0.500
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Pin Description
PIN
NAME
FUNCTION
1
REFP
Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
Analog Supply Voltage. Bypass V
0.1µF capacitor.
to GND with a combination of a 2.2µF capacitor in parallel with a
DD
2, 8, 43
V
DD
3
4
IA+
IA-
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42
GND
Analog Ground. Connect all pins to GND ground plane.
6
CLK
QA-
Conversion Clock Input. Clock signal for both ADCs and DACs.
9
10
Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
QA+
11, 33, 39
V
Analog Supply Voltage. Connect to V
power plane as close to the device as possible.
DD
DD
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
13–16, 19–22
DA0–DA7
17
18
OGND
Output Driver Ground
Output Driver Power Supply. Supply range from +1.8V to V to accommodate most logic levels.
DD
OV
DD
Bypass OV
to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
DD
23–32
34
DD0–DD9 DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
DIN
SCLK
CS
3-Wire Serial Interface Data Input. Data is latched on the rising edge of the SCLK.
3-Wire Serial Interface Clock Input
35
36
3-Wire Serial Interface Chip Select Input. Apply logic low enables the serial interface.
No Connection
38
N.C.
40, 41
44, 45
46
QD+, QD- DAC Channel-QD Differential Voltage Output
ID-, ID+
REFIN
COM
DAC Channel-ID Differential Voltage Output
Reference Input. Connect to V for internal reference.
DD
47
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
Negative Reference I/O. Conversion range is (V
capacitor.
- V
). Bypass REFN to GND with a 0.33µF
REFP
REFN
48
REFN
EP
—
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
12 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
The MAX5864 can operate in FDD or TDD applications
Detailed Description
by configuring the device for transmit, receive, or trans-
The MAX5864 integrates dual 8-bit receive ADCs and
ceiver modes through a 3-wire serial interface. In TDD
mode, the digital bus for receive ADC and transmit
DAC can be shared to reduce the digital I/O to a single
10-bit parallel multiplexed bus. In FDD mode, the
MAX5864 digital I/O can be configured for an 18-bit,
parallel multiplexed bus to match the dual 8-bit ADC
and dual 10-bit DAC.
dual 10-bit transmit DACs while providing ultra-low
power and highest dynamic performance at a conver-
sion rate of 22Msps. The ADCs’ analog input amplifiers
are fully differential and accept 1V
full-scale signals.
P-P
The DACs’ analog outputs are fully differential with
400mV full-scale output range at 1.4V common mode.
The MAX5864 includes a 3-wire serial interface to con-
trol operating modes and power management. The ser-
ial interface is SPI™ and MICROWIRE™ compatible.
The MAX5864 serial interface selects shutdown, idle,
standby, transmit, receive, and transceiver modes.
The MAX5864 features an internal precision 1.024V
bandgap reference is stable over the entire power-supply
and temperature ranges.
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
IA+
IA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
S4b
QA+
QA-
OUT
OUT
C2a
C2b
S4c
S1
MAX5864
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 1. MAX5864 ADC Internal T/H Circuits
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________ 13
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
The amplifiers charge capacitors C1a and C1b to the
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential,
pipelined architecture that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for channel IA and 5.5 clock
cycles for channel QA. The ADC’s full-scale analog
same values originally held on C2a and C2b. These val-
ues are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the ADC to
track and sample/hold analog inputs of high frequen-
cies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and
QA-) can be driven either differentially or single ended.
Match the impedance of IA+ and IA-, as well as QA+
and QA-, and set the common-mode voltage to mid-
input range is
V
with a common-mode input range
is the difference between V
REF
supply (V /2) for optimum performance.
DD
of V /2 0.2V. V
DD
REF
REFP
and V
. See the Reference Configurations section
REFN
ADC Digital Output Data (DA0–DA7)
for details.
DA0–DA7 are the ADCs’ digital logic outputs. The logic
level is set by OV
from 1.8V to V . The digital out-
DD
Input Track-and-Hold (T/H) Circuits
DD
put coding is offset binary (Table 1, Figure 2). The
capacitive load on digital outputs DA0–DA7 should be
kept as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX5864 and degrading its dynamic performance.
Buffers on the digital outputs isolate them from heavy
capacitive loads. Adding 100Ω resistors in series with
the digital outputs close to the MAX5864 helps improve
ADC performance. Refer to the MAX5865 EV kit
schematic for an example of the digital outputs driving
a digital buffer through 100Ω series resistors.
Figure 1 displays a simplified functional diagram of the
ADC’s input T/H circuitry. In track mode, switches S1,
S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully
differential circuits sample the input signals onto the
two capacitors (C2a and C2b) through switches S4a
and S4b. S2a and S2b set the common mode for the
amplifier input, and open simultaneously with S1, sam-
pling the input waveform. Switches S4a, S4b, S5a, and
S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differ-
ential voltages are held on capacitors C2a and C2b.
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL
INPUT VOLTAGE
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
OUTPUT DECIMAL
CODE
(DA7–DA0)
127
128
127
V
×
REF
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
255
254
129
128
127
1
(+full scale - 1LSB)
126
128
126
V
×
×
REF
(+full scale - 2LSB)
1
128
V
+1
REF
0
128
0
V
×
×
REF
(bipolar zero)
1
128
−V
REF
-1
127
128
-127
−V
REF
×
×
(-full scale + 1LSB)
128
128
-128
(-full scale)
−V
REF
0
14 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sam-
pled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 22MHz. The DAC’s digital inputs,
DD0–DD9, are multiplexed on a single 10-bit bus. The
voltage reference determines the data converters’ full-
scale output voltages. See the Reference Configurations
section for setting reference voltage. The DACs utilize a
current-array technique with a 1mA (with 1.024V refer-
ence) full-scale output current driving a 400Ω internal
resistor resulting in a 400mV full-scale differential out-
put voltage. The MAX5864 is designed for differential
output only and is not intended for single-ended appli-
cation. The analog outputs are biased at 1.4V common
mode and designed to drive a differential input stage
with input impedance ≥70kΩ. This simplifies the analog
interface between RF quadrature upconverters and the
MAX5864. RF upconverters require a 1.3V to 1.5V com-
mon-mode bias. The internal DC common-mode bias
eliminates discrete level setting resistors and code-gen-
erated level-shifting while preserving the full dynamic
range of each transmit DAC. Table 2 shows the output
voltage vs. input code.
2 x V
REF
V
= V
- V
1 LSB =
REF
REFP REFN
256
V
V
REF
REF
1111 1111
1111 1110
1111 1101
1000 0001
1000 0000
0111 1111
(COM)
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1
0
+1
+125 +126 +127 +128
(COM)
INPUT VOLTAGE (LSB)
Figure 2. ADC Transfer Function
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
CHI
CHQ
CLK
t
t
DOI
DOQ
DA0–DA7
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
Figure 3. ADC System Timing Diagram
______________________________________________________________________________________ 15
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode V
=
REFDAC
1.024V, External Reference Mode V
= V
)
REFDAC
REFIN
OFFSET BINARY
DIFFERENTIAL OUTPUT VOLTAGE
INPUT DECIMAL CODE
(DD0–DD9)
V
1023
1023
REFDAC
2.56
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
1023
1022
513
512
511
1
×
×
×
×
V
1021
1023
REFDAC
2.56
V
3
1023
REFDAC
2.56
V
1
1023
REFDAC
2.56
−V
1
1023
REFDAC
2.56
×
×
−V
1021
1023
REFDAC
2.56
−V
1023
1023
REFDAC
2.56
×
0
CLK
t
t
DHQ
DSQ
Q: N-2
I: N-1
Q: N-1
Q: N
I: N+1
DD0–DD9
I: N
t
t
DHI
DSI
N-2
N-2
ID
N-1
N-1
N
N
QD
Figure 4. DAC System Timing Diagram
DAC Timing
3-Wire Serial Interface and
Operation Modes
Figure 4 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel (ID) is
latched on the falling edge of the clock signal, and Q-
channel (QD) data is latched on the rising edge of the
clock signal. Both I and Q outputs are simultaneously
updated on the next rising edge of the clock signal.
The 3-wire serial interface controls the MAX5864 opera-
tion modes. Upon power-up, the MAX5864 must be
programmed to operate in the desired mode. Use the
3-wire serial interface to program the device for the shut-
down, idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data
register sets the operation modes as shown in Table 3.
The serial interface remains active in all six modes.
16 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Table 3. MAX5864 Operation Modes
D7
(MSB)
FUNCTION
DESCRIPTION
D6
D5
D4
D3
D2
D1
D0
Device shutdown. REF is off, ADCs are
off, and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
Shutdown
X
X
X
X
X
0
0
0
set to zero or OV
.
DD
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
Idle
Rx
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
0
set to zero or OV
.
DD
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OV
.
DD
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
Tx
X
X
X
X
X
X
X
X
X
X
0
1
1
0
1
0
Xcvr
REF is on, ADCs and DACs are on.
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
Standby
X
X
X
X
X
1
0
1
OV
.
DD
X = Don’t care.
Shutdown mode offers the most dramatic power savings
by shutting down all the analog sections of the MAX5864
and placing the ADCs’ digital outputs in tri-state mode.
When the ADCs’ outputs transition from tri-state to on,
the last converted word is placed on the digital outputs.
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OV
DD
because the bus is not internally pulled up. The wake-
up time from standby mode to the Xcvr mode is domi-
nated by the 40µs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The DACs’ digital bus inputs must be zero or OV
DD
because the bus is not internally pulled up. The DACs’
previously stored data is lost when coming out of shut-
down mode. The wake-up time from shutdown mode is
dominated by the time required to charge the capacitors
at REFP, REFN, and COM. In internal reference mode
and buffered external reference mode, the wake-up time
is typically 40µs to enter Xcvr moed, 20µs to enter Rx
mode, and 40µs to enter Tx mode.
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI™/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following CS high-to-low transition, data is shift-
ed synchronously, MSB first, on the rising edge of the
serial clock (SCLK). After 8 bits are loaded into the seri-
al input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 5 shows the detailed
timing diagram of the 3-wire serial interface.
In idle mode, the reference and clock distribution circuits
are powered, but all other functions are off. The ADCs’
outputs are forced to tri-state. The DACs’ digital bus
inputs must be zero or OV , because the bus is not
DD
internally pulled up. The wake-up time from the idle mode
is 10µs required for the ADCs and DACs to be fully oper-
ational. When the ADCs’ outputs transition from tri-state to
on, the last converted word is placed on the digital out-
puts. In the idle mode, the supply current is lowered if the
clock input is set to zero or OV ; however, the wake-up
DD
time extends to 40µs.
QSPI is a trademark of Motorola, Inc.
______________________________________________________________________________________ 17
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
t
CSW
CS
t
t
t
t
t
CS
CSS
CP
CH
CL
SCLK
DIN
t
DS
LSB
MSB
t
DH
Figure 5. 3-Wire Serial Interface Timing Diagram
CS
SCLK
8-BIT DATA
DIN
t
OR t
R
ENABLE, x
WAKE, SD, ST_ (Rx)
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAO–DA7
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
ID/QD
t
OR t
T
ENABLE, X
WAKE, SD, ST_ (Tx)
Figure 6. MAX5864 Mode Recovery Timing Diagram
Mode Recovery Timing
Figure 6 shows the mode recovery timing diagram.
is the wake-up time when exiting shutdown, idle,
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
T
accepts a CMOS-compatible signal level set by OV
DD
from 1.8V to V . Since the interstage conversion of the
DD
WAKE
or standby mode and entering into Rx, Tx, or Xcvr
mode. t is the recovery time when switching
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:
ENABLE
between any Rx, Tx, or Xcvr mode. t
or t
is
WAKE
ENABLE
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
t
or t
times are measured after the 8-bit
ENABLE
WAKE
serial command is latched into the MAX5864 by CS
transition high. t for Xcvr mode is dominated by
ENABLE
the DAC wake-up time. The recovery time is 10µs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40µs to switch from shutdown or standby mode
to Xcvr mode.
1
SNR = 20 × log
2 × π × t × t
IN
AJ
where f represents the analog input frequency and
IN
t
AJ
is the time of the clock jitter.
18 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Clock jitter is especially critical for undersampling
Applications Information
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5864 clock input operates
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
with an OV /2 voltage threshold and accepts a 50%
DD
15% duty cycle.
Reference Configurations
The MAX5864 features an internal precision 1.024V
bandgap reference is stable over the entire power sup-
ply and temperature range. The REFIN input provides
two modes of reference operation. The voltage at REFIN
provides a V /2 DC level shift to the input. A 1:1 trans-
DD
former can be used, or a step-up transformer can be
selected to reduce the drive requirements. In general,
the MAX5864 provides better SFDR and THD with fully
differential input signals than single-ended signals,
especially for high-input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing com-
pared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5864 DACs’ differential
analog outputs to single ended.
(V ) sets reference operation mode (Table 4).
REFIN
In internal reference mode, connect REFIN to V
REF
.
DD
V
is an internally generated 0.512V. COM, REFP,
and REFN are low-impedance outputs with V
=
COM
= V /2 -
V
V
/2, V
= V /2 + V
/2, and V
DD
REF
REFP
DD
REF
REFN DD
/2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor.
In buffered external reference mode, apply 1.024V
10% at REFIN. In this mode, COM, REFP, and REFN
25Ω
IA+
are low-impedance outputs with V
= V /2, V
DD REFP
COM
0.1µF
22pF
= V /2 + V
/4, and V
= V /2 - V
/4.
REFIN
DD
REFIN
REFN
DD
V
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capaci-
tor. In this mode, the DAC’s full-scale output voltage
and common-mode voltage are proportional to the
IN
COM
IA-
0.33µF
0.1µF
external reference. For example, if the V
is
REFIN
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or 440mV, and the
common-mode voltage increases by 10%.
25Ω
25Ω
22pF
22pF
MAX5864
QA+
0.1µF
Table 4. Reference Modes
V
IN
V
REFERENCE MODE
REFIN
Internal reference mode. V is internally
0.33µF
0.1µF
REF
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor.
>0.8 x V
DD
QA-
Buffered external reference mode. An
external 1.024V 10% reference voltage
25Ω
22pF
is applied to REFIN. V
is internally
REF
1.024V 10%
generated to be V /2. Bypass REFP,
REFIN
REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a
0.1µF capacitor.
Figure 7. Balun-Transformer Coupled Single-Ended to
Differential Input Drive for ADCs
______________________________________________________________________________________ 19
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Using Op-Amp Coupling
ID+
V
Drive the MAX5864 ADCs with op amps when a balun
transformer is not available. Figures 9 and 10 show the
ADCs being driven by op amps for AC-coupled single-
ended, and DC-coupled differential applications.
Amplifiers such as the MAX4354/MAX4454 provide
high speed, high bandwidth, low noise, and low distor-
tion to maintain the input signal integrity. Figure 10 can
also be used to interface with the DAC differential ana-
log outputs to provide gain or buffering. The DAC dif-
ferential analog outputs cannot be used in single-
ended mode because of the internally generated
1.4VDC common-mode level. Also, the DAC analog
outputs are designed to drive a differential input stage
with input impedance ≥70kΩ. If single-ended outputs
are desired, use an amplifier to provide differential to
single-ended conversion and select an amplifier with
proper input common-mode voltage range.
OUT
MAX5864
ID-
QD+
V
OUT
QD-
Figure 8. Balun-Transformer Coupled Differential to Single-
Ended Output Drive for DACs
FDD and TDD Modes
The MAX5864 can be used in diverse applications
operating FDD or TDD modes. The MAX5864 operates
in Xcvr mode for FDD applications such as WCDMA-
3GPP (FDD) and 4G technologies. Also, the MAX5864
can switch between Tx and Rx modes for TDD applica-
tions like TD-SCDMA, WCDMA-3GPP (TDD),
IEEE802.11a/b/g, and IEEE802.16.
REFP
1kΩ
1kΩ
R
ISO
50Ω
V
IN
0.1µF
INA+
COM
INA-
C
IN
22pF
100Ω
100Ω
In FDD mode, the ADC and DAC operate simultaneous-
ly. The ADC bus and DAC bus are dedicated and must
be connected in 18-bit parallel (8-bit ADC and 10-bit
DAC) to the digital baseband processor. Select Xcvr
mode through the 3-wire serial interface and use the
conversion clock to latch data. In FDD mode, the
REFN
0.1µF
R
ISO
50Ω
C
22pF
IN
MAX5864 uses 34mW power at f
= 15.36MHz. This
CLK
is the total power of the ADC and DAC operating simul-
taneously.
REFP
MAX5864
In TDD mode, the ADC and DAC operate independent-
ly. The ADC and DAC bus are shared and can be con-
nected together, forming a single 10-bit parallel bus to
the digital baseband processor. Using the 3-wire serial
interface, select between Rx mode to enable the ADC
and Tx mode to enable the DAC. When operating in Rx
mode, the DAC does not transmit because the core is
disabled and in Tx mode, the ADC bus is tri-state. This
eliminates any unwanted spurious emissions and pre-
vents bus contention. In TDD mode, the MAX5864 uses
R
1kΩ
ISO
50Ω
V
IN
0.1µF
INB+
C
IN
22pF
100Ω
100Ω
1kΩ
REFN
0.1µF
R
50Ω
ISO
24.7mW power in Rx mode at f
= 15.36MHz, and
CLK
INB-
C
22pF
the DAC uses 24mW in Tx mode.
IN
Figure 9. Single-Ended Drive for ADCs
20 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
R4
600Ω
R5
600Ω
MAX5864
R
ISO
22Ω
R1
600Ω
INA-
C
IN
5pF
R2
600Ω
R6
600Ω
R7
600Ω
COM
R3
600Ω
R8
600Ω
R9
600Ω
R
ISO
22Ω
INA+
C
IN
5pF
R10
600Ω
R11
600Ω
Figure 10. ADC DC-Coupled Differential Drive
CLK
ADC
MAX2391
ADC
OUTPUT
MUX
QUADRATURE
DEMODULATOR
ADC
T/R
CLK
DAC
DAC
MAX2395
QUADRATURE
TRANSMITTER
DAC
INPUT
MUX
SERIAL BUS
MAX5864
Figure 11. Typical Application Circuit for TDD
_______________________________________________________________________________________ 21
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Figure 11 illustrates the MAX5864 working with the
MAX2391 and MAX2395 in TDD mode to provide a
complete radio front-end solution. Because the
MAX5864 DAC has full differential analog outputs with
a common-mode level of 1.4V, it can interface directly
with RF quadrature modulators while eliminating dis-
crete components and amplifiers used for level-shifting
circuits. Also, the DAC’s full dynamic range is pre-
served because the internally generated common-
mode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5864
ceramic capacitor in parallel with a 2.2µF capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33µF ceramic capacitor. Bypass REFIN to GND with
a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
the MAX5864 exposed backside paddle to the GND
plane. Join the two ground planes at a single point
such that the noisy digital ground currents do not inter-
fere with the analog ground plane. The ideal location
for this connection can be determined experimentally at
a point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
ADC has 1V
full-scale range and accepts input com-
P-P
mon-mode levels of V /2 ( 200mV). These features
DD
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
Grounding, Bypassing, and
Board Layout
The MAX5864 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surface-
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90° turns.
mount devices for minimum inductance. Bypass V
to
DD
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF capacitor. Bypass OV
to OGND with a 0.1µF
DD
7
6
6
1 LSB
5
4
5
4
3
2
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
AT STEP
011 (1/2 LSB )
3
2
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
AT STEP
001 (1/4 LSB )
1
0
1
0
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 12a. Integral Nonlinearity
Figure 12b. Differential Nonlinearity
22 _______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ADC Dynamic Parameter Definitions
Dynamic Parameter Definitions
Aperture Jitter
ADC and DAC Static Parameter Definitions
Figure 13 depicts the aperture jitter (t ), which is the
AJ
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the end-point method (DAC Figure 12a).
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
SNR(max) = 6.02dB x N + 1.76dB (in dB)
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
DAC Offset Error
Offset error (Figure 12a) is the difference between the
ideal and actual offset point. The offset point is the out-
put value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of devia-
tion between the measured transition point and the
ideal transition point with the offset error removed.
ENOB = (SINAD - 1. 76) / 6.02
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
ANALOG
INPUT
2
2
2
3
2
2
5
2
6
(V +V +V +V +V )
4
t
AD
THD = 20log
t
AJ
V
1
SAMPLED
DATA (T/H)
where V is the fundamental amplitude and V –V are
1
2
6
the amplitudes of the 2nd- through 6th-order harmonics.
HOLD
TRACK
TRACK
T/H
Figure 13. T/H Aperture Timing
______________________________________________________________________________________ 23
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset.
(V2 +V2 +... +V2)
2
3
n
THD = 20log
V
1
where V is the fundamental amplitude and V through
n
up to the Nyquist frequency.
1
2
Intermodulation Distortion (IMD)
V are the amplitudes of the 2nd through nth harmonic
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f and
1
f , are present at the inputs. The intermodulation prod-
2
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
ucts are (f
f ), (2 ✕ f ), (2 ✕ f ), (2 ✕ f
f ), (2 ✕ f
2 2
1
2
1
2
1
f ). The individual input tone levels are at -7dBFS.
1
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodula-
tion product relative to the input power of either input
tone when two tones, f and f , are present at the
1
2
inputs. The 3rd-order intermodulation products are (2 x
f ), (2 ✕ f f ). The individual input tone levels are
Pin Configuration
f
1
2
2
1
at -7dBFS.
TOP VIEW
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed
5%.
36
35
34
33
32
31
30
29
28
27
26
25
REFP
1
2
3
4
5
6
7
8
9
CS
V
SCLK
DIN
DD
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
IA+
IA-
V
DD
GND
CLK
GND
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
MAX5864
V
DD
QA-
QA+ 10
V
11
DD
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the full-
power bandwidth frequency.
GND 12
QFN
Chip Information
TRANSISTOR COUNT: 16,765
PROCESS: CMOS
24 ______________________________________________________________________________________
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
b
L
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
A
A1
A2
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0144
B
2
______________________________________________________________________________________ 25
Ultra-Low-Power, High-Dynamic-
Performance, 22Msps Analog Front End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0144
B
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明