ISL8700AIBZ [ROCHESTER]
DSP-ADDRESS SEQUENCER, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14;
| 型号： | ISL8700AIBZ |
| 厂家： | 
Rochester Electronics |
| 描述： | DSP-ADDRESS SEQUENCER, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14 双倍数据速率 光电二极管 外围集成电路 |
| 文件： | 总13页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL8700A, ISL8701A, ISL8702A,
ISL8703A, ISL8704A, ISL8705A
®
Data Sheet
October 12, 2006
FN6381.0
Adjustable Quad Sequencer
Features
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,
ISL8705A family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
High performance DSP, FPGA, µP and various sub-systems
require input power sequencing for proper functionality at
initial power up and the ISL870XA provides this function
while monitoring the distributed voltage for over and
undervoltage compliance.
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700A, ISL8702A, ISL8704A) and
ENABLE# (ISL8701A, ISL8703A, ISL8705A)
SEQ_EN (ISL8702A, ISL8703A) and
SEQ_EN# (ISL8704A, ISL8705A)
These ICs operate over the +3.3V to +24V nominal voltage
range. All have a user adjustable time from UV and OV
voltage compliance to sequencing start via an external
capacitor when in auto start mode and adjustable time delay
to subsequent ENABLE output signal via external resistors.
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Additionally, the ISL8702A, ISL8703A, ISL8704A and
ISL8705A provide I/O for sequencing on and off operation
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range.
Applications
• Power Supply Sequencing
• System Timing Function
Easily daisy chained for more than 4 sequenced signals.
Pinout
ISL870XA
(14 LD SOIC)
TOP VIEW
Altogether, the ISL870XA provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
14
Ordering Information
ENABLE_D
ENABLE_C
ENABLE_B
1
2
3
4
5
6
7
VIN
13
12
11
10
9
TD
PART NUMBER
(Note 1)
PART
TEMP.
PACKAGE
(Pb-free)
PKG.
DWG. #
TC
MARKING RANGE (°C)
ENABLE_A
OV
TB
ISL8700AIBZ*
ISL8701AIBZ*
ISL8702AIBZ*
ISL8703AIBZ*
ISL8704AIBZ*
ISL8705AIBZ*
ISL8700AIBZ
ISL8701AIBZ
ISL8702AIBZ
ISL8703AIBZ
ISL8704AIBZ
ISL8705AIBZ
-40 to +85 14 Ld SOIC M14.15
-40 to +85 14 Ld SOIC M14.15
-40 to +85 14 Ld SOIC M14.15
-40 to +85 14 Ld SOIC M14.15
-40 to +85 14 Ld SOIC M14.15
-40 to +85 14 Ld SOIC M14.15
TIME
UV
SEQ_EN (NC on ISL8700A/01A)
FAULT (NC on ISL8700A/01A)
GND
8
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
ISL870XAEVAL1 Evaluation Platform
3.3-24V
*Add “-T” suffix for tape and reel.
NOTES:
EN
Vo1
Vo2
Vo3
V04
DC/DC
VIN
Ru
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
SEQ_EN *
EN
UV
DC/DC
Rm
Rl
FAULT *
OV
EN
EN
GND TB TC TD TIME
DC/DC
DC/DC
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A
FIGURE 1. ISL870XA IMPLEMENTATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Absolute Maximum Ratings
Thermal Information
V
, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V
IN
Thermal Resistance (Typical, Note 2)
θ
(°C/W)
JA
110
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V +0.3V, to -0.3V
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IN
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 3.3V to 24V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Nominal V = 3.3V to +24V, T = T = -40°C to+85°C, Unless Otherwise Specified.
IN
A
J
PARAMETER
UV AND OV INPUTS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
V
1.16
1.21
1.10
104
10
1.28
V
V
UVRvth
V
1.06
1.18
UVFvth
V
V
- V
UVFvth
-
-
-
-
mV
nA
UVhys
UVRvth
UV/OV Input Current
I
UV
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current
TIME Pin Threshold
I
-
2.6
2.0
30
-
μA
V
TIME
V
1.9
2.25
TIME_VTH
Time from V Valid to ENABLE_A
IN
t
SEQ_EN = high, C
SEQ_EN = high, C
SEQ_EN = high, C
= open
= 10nF
= 500nF
-
-
μs
ms
ms
μs
Ω
VINSEQpd
TIME
TIME
TIME
t
t
-
7.7
435
-
-
VINSEQpd_10
VINSEQpd500
-
-
-
Time from V Invalid to Shutdown
IN
t
UV or OV to simultaneous shutdown
1
shutdown
ENABLE Output Resistance
ENABLE Output Low
R
I
I
= 1mA
= 1mA
-
100
0.1
15
-
EN
ENABLE
ENABLE
Vol
-
-
V
ENABLE Pull-down Current
Delay to Subsequent ENABLE Turn-on/off
I
ENABLE = 1V
10
155
3.5
-
-
240
6
mA
ms
ms
ms
pulld
t
R
R
R
= 120kΩ
= 3kΩ
= 0Ω
195
4.7
0.5
del_120
TX
TX
TX
t
del_3
t
-
del_0
SEQUENCE ENABLE AND FAULT I/O
V
V
Valid to FAULT Low
t
15
-
30
0.5
15
2.4
-
50
μs
μs
mA
V
IN
IN
FLTL
Invalid to FAULT High
t
-
-
FLTH
FAULT Pull-down Current
SEQ_EN Pull-up Voltage
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
BIAS
FAULT = 1V
10
-
V
SEQ_EN open
-
SEQ
Vil
-
0.3
-
V
SEQ_EN
Vih
1.2
-
-
V
SEQ_EN
SEQ_EN_ENA
t
SEQ_EN low to ENABLE_A low
0.2
1
μs
IC Supply Current
I
V
V
V
V
= 3.3V
-
-
-
-
191
246
286
2.3
-
400
-
μA
μA
μA
V
VIN_3.3V
IN
IN
IN
IN
I
= 12V
VIN_12V
VIN_24V
I
= 24V
V
Power On Reset
V
low to high
2.8
IN
IN_POR
FN6381.0
October 12, 2006
2
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Pin Descriptions
PINS
8700A 8701A 8702A 8703A 8704A 8705A PIN NAME
FUNCTION DESCRIPTION
NA
1
NA
2
NA
1
NA
2
NA
1
NA
2
ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks V upon bias.
IN
1
1
1
ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V < 1V.
IN
NA
2
NA
2
NA
2
ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks V upon bias.
IN
NA
3
NA
3
NA
3
ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V < 1V.
IN
NA
3
NA
3
NA
3
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks V upon bias.
IN
NA
4
NA
4
NA
4
ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V < 1V.
IN
NA
4
NA
4
NA
4
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks V upon bias.
IN
NA
NA
NA
ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
< 1V.
IN
5
6
5
6
5
6
5
6
5
6
5
6
OV
UV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
7
7
7
8
7
8
7
8
7
8
GND
IC ground.
NA
NA
FAULT
The V voltage when not within the desired UV to OV window will cause FAULT to be
IN
released to be pulled high to a voltage equal to or less than V via an external resistor.
IN
NA
NA
10
NA
NA
10
9
9
NA
9
NA
9
SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
NA
10
NA
10
10
10
TIME
This pin provides a 2.6µA current output so that an adjustable V valid to sequencing on
IN
and off start delay period is created with a capacitor to ground.
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
TB
A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
TC
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
V
IC Bias Pin Nominally 3.3V to 24V
IN
This pin requires a 1μF decoupling capacitor close to IC pin.
FN6381.0
October 12, 2006
3
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Functional Block Diagram
VIN (2.8V MIN - 27V MAX)
VIN
VREF
1.17V
VOLTAGE
REFERENCE
VIN
SEQ_EN
UV
INTERNAL VOLTAGE
3.5V
REGULATOR
+
-
eo
ENABLE_A
ENABLE_B
ENABLE_C
2.0V VIN POR
+
-
LOGIC
OV
FAULT
30μs
GND
TIME
V
TIME_VTH
ENABLE_D
PROGRAMMABLE
DELAY TIMER
VIN
2.6μA
TB
TC
TD
greater than V
TIME_VTH
the ISL8700A, ISL8702A, ISL8704A
Functional Description
ENABLE_A is released to go high via an external pull-up
resistor or a pull-up in a DC/DC convertor enable input, for
example. Conversely, ENABLE#_A output will be pulled low at
this time on an ISL8701A, ISL8703A, ISL8705A. The time
delay generated by the external capacitor is to assure
continued voltage compliance within the programmed limits, as
during this time any OV or UV condition will halt the start-up
The ISL870XA family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 3.3V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870XA initiate the pre-programmed A-B-C-D sequence of
the ENABLE (ISL8700A, ISL8702A, ISL8704A) or ENABLE#
(ISL8701A, ISL8703A, ISL8705A) outputs. Although this IC has
a bias range of 3.3V to 24V it can monitor any voltage >1.22V
via the external divider if a suitable bias voltage is otherwise
provided.
process. TIME cap is discharged once V
TIME_VTH
is met.
Once ENABLE_A is active (either released high on the
ISL8700A, ISL8702A, ISL8704A or pulled low, ISL8701A,
ISL8703A, ISL8705A) a counter is started and using the
resistor on TB as a timing component a delay is generated
before ENABLE_B is activated. At this time, the counter is
restarted using the resistor on TC as its timing component for
a separate timed delay until ENABLE_C is activated. This
process is repeated for the resistor on TD to complete the
A-B-C-D sequencing order of the ENABLE or ENABLE#
outputs. At any time during sequencing if an OV or UV event
is registered, all four ENABLE outputs will immediately return
to their reset state; low for ISL8700A, ISL8702A, ISL8704A
During initial bias voltage (V ) application the ISL8700A,
IN
ISL8702A, ISL8704A ENABLE outputs are held low once
V
= 1V whereas the ISL8701A, ISL8703A, ISL8705A
IN
ENABLE# outputs follow the rising V . Once V > the V bias
IN IN
power on reset threshold (POR) of 2.8V, V is constantly
IN
monitored for compliance via the input voltage resistor divider
and the voltages on the UV and OV pins and reported by the
FAULT output. Internally, voltage regulators generate 3.5V and
1.17V ±5% voltage rails for internal usage once V > POR.
IN
Once UV > 1.22V and with the SEQ_EN pin high or open,
(SEQ_EN# must be pulled low on ISL8704A, ISL8705A) the
auto sequence of the four ENABLE (ENABLE#) outputs begins
as the TIME pin charges its external capacitor with a 2.6µA
current source. The voltage on TIME is compared to the
and high for ISL8701A, ISL8703A, ISL8705A. C
is
TIME
immediately discharged after initial ramp up thus waiting for
subsequent voltage compliance to restart. Once sequencing
is complete, any subsequently registered UV or OV event will
trigger an immediate and simultaneous reset of all ENABLE or
ENABLE# outputs.
internal reference (V
) comparator input and when
TIME_VTH
FN6381.0
October 12, 2006
4
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
On the ISL8702A, ISL8703A, ISL8704A and ISL8705A,
requirement please see the next section.
enabling of on or off sequencing can also be signaled via the
SEQ_EN or SEQ_EN# input pin once voltage compliance is
met. Initially, the SEQ_EN pin should be held low and
released when sequence start is desired. The SEQ# is
internally pulled high and sequencing is enabled when it is
pulled low. The on sequence of the ENABLE outputs is as
previously described. The off sequence feature is only
available on the variants having the SEQ_EN or the
SEQ_EN# inputs, these being the ISL8702A, ISL8703A,
ISL8704A, ISL8705A. The sequence is D off, then C off, then
B off and finally A off. Once SEQ_EN (SEQ_EN#) is signaled
low (high), the TIME cap is charged to 2V once again. Once
this Vth is reached, ENABLE_D transitions to its reset state
and CTIM is discharged. A delay and subsequent sequence
off is then determined by TD resistor to ENABLE_C. Likewise,
a delay to ENABLE_B and then ENABLE_A turn-off is
determined by TC and TB resistor values respectively.
1. Determine if turn-on or shutdown limits are preferred. In this
example, we will determine the resistor values based on the
shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, Ir = divider
current
4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm+Rl = 1.1V/Ir @ UV = Rm+Rl = 1.1V/(10.8V/100kΩ) =
10.370kΩ
6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistor’s values.
With the ISL8700A, ISL8701A a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
In our example, with the closest standard values of
Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
Programming the ENABLE Output Delays
The delay timing between the four sequenced ENABLE outputs
are programmed with four external passive components. The
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
delay from a valid V (ISL8700A and ISL8701A) to
IN
ENABLE_A and SEQ_EN being valid (ISL8702A, ISL8703A,
ISL8704A, ISL8705A) to ENABLE_A is determined by the
value of the capacitor on the TIME pin to GND. The external
TIME pin capacitor is charged with a 2.6µA current source.
Once the voltage on TIME is charged up to the internal
reference voltage, (VTIME_VTH) the ENABLE_A output is
released out of its reset state. The capacitor value for a desired
Programming the Under and Overvoltage Limits
When choosing resistors for the divider remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ to1000kΩ range is
advisable with high precision resistors being used to reduce
monitoring error. Although for the ISL870XA, two dividers of two
resistors each can be employed to separately monitor the OV
delay (±10%) to ENABLE_A once V and SEQ_EN where
IN
applicable has been satisfied is determined by:
C
= t
/770kΩ
TIME VINSEQpd
and UV levels for the V voltage. We will discuss using a
single three resistor string for monitoring the V voltage,
IN
referencing Figure 1. In the three resistor divider string with Ru
(upper), Rm (middle) and Rl (lower), the ratios of each in
combination to the other two is balanced to achieve the desired
UV and OV trip levels. Although this IC has a bias range of 3.3V
to 24V, it can monitor any voltage >1.22V.
IN
Once ENABLE_A reaches V
, the TIME pin is pulled
TIME_VTH
low in preparation for a sequenced off signal via SEQ_EN. At
this time, the sequencing of the subsequent outputs is started.
ENABLE_B is released out of reset after a programmable time,
then ENABLE_C, then ENABLE _D, all with their own
programmed delay times.
The subsequent delay times are programmed with a single
external resistor for each ENABLE output providing maximum
flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
values determine the charge and discharge rate of an internal
capacitor comprising an RC time constant for an oscillator
whose output is fed into a counter generating the timing delay
to ENABLE output sequencing.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (gnd connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The R value for a given delay time is defined as:
TX
The following is a practical example worked out. For detailed
equatons on how to perform this operation for a given supply
R
= t /1667nF
del
TX
FN6381.0
October 12, 2006
5
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
This will give a window of 12 ±0.48V where the system is
An Advanced Tutorial on Setting UV and OV Levels
guaranteed not to be in fault and a limit of 12 ±1.5V beyond
which the system is guaranteed to be in fault.
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870XA than the earlier text.
It is wise to check both these voltages, for if the latter is made to
tight, the former will cease to exist. This point comes when Vtol
< Vhys/2 and results from the fact that the acceptable window
for the OV pin no longer aligns with the acceptable window for
the UV pin. In this case, the application will have to be changed
such that UV and OV are provided separate resistor strings. In
this case, the UV and OV thresholds can be individually
controlled by adjusting the relevant divider.
The following equation set can alternatively be used to work out
ideal values for a 3 resistor divider string of Ru, Rm and Rl.
These equations assume that V
is the center point between
REF
V
and V
(i.e. (V
+ V )/2 = 1.17V),
UVRvth
UVFvth
UVRvth
UVFvth
Iload is the load current in the resistor string (i.e. V /(Ru + Rm
IN
+ Rl)), V is the nominal input voltage and Vtol is the
IN
acceptable voltage tolerance, such that the UV and OV
thresholds are centered at V ± Vtol. The actual acceptable
IN
The previous example will give voltage thresholds of:
voltage window will also be affected by the hysteresis at the UV
and OV pins. This hysteresis is amplified by the resistor string
such that the hysteresis at the top of the string is:
with V rising
IN
UVr = V - Vtol + Vhys/2 = 11.5V and
IN
OVr = V + Vtol + Vhys/2 = 13.5V
IN
Vhys = V
UVhys
x V
/V
OUT REF
with V falling
IN
This means that the V ± Vtol thresholds will exhibit
IN
Ovf = V + Vtol - Vhys/2 = 12.5V and
IN
hysteresis resulting in thresholds of V + Vtol ± Vhys/2 and
IN
UVf = V - Vtol - Vhys/2 = 10.5V.
IN
V
- Vtol ± Vhys/2.
IN
So with a single three resistor string, the resistor values can
be calculated as:
There is a window between the V rising UV threshold and
IN
the V falling OV threshold where the input level is
IN
Rl = (V
REF
/Iload) (1 - Vtol/V )
IN
guaranteed not to be detected as a fault. This window exists
Rm = 2(V
x Vtol)/(V x Iload)
REF
IN
between the limits V ± (Vtol - Vhys/2). There is an
IN
Ru = 1/Iload x (V - V
IN
(1+Vtol/V ))
IN
REF
extension of this window in each direction up to
V
± (Vtol + Vhys/2), where the voltage may or may not be
IN
For the above example, with Vtol = 0.99V, assuming a
detected as a fault, depending on the direction from which it
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For
100µA Iload at V = 12V:
IN
Rl = 10.7kΩ
Rm = 1.9kΩ
Ru = 107.3kΩ
example, if V is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If V
IN IN
must remain within 12V ± 1.5V, Vtol = 1.5 - 1.03/2 = 0.99V.
FAULT
SEQ_EN
TIME
A
B
C
D
D
C
B
A
ENABLE OUTPUTS
FIGURE 2. ISL8702A OPERATIONAL DIAGRAM
FN6381.0
October 12, 2006
6
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
OVERVOLTAGE
LIMIT
t
FLTH
t
<t
FLTH
FLTL
UNDERVOLTAGE
LIMIT
t
FLTL
t
MONITORED VOLTAGE
FLTH
RAMPING UP AND DOWN
FAULT OUTPUT
FIGURE 3. ISL8702A, ISL8703A, ISL8704A, ISL8705A FAULT OPERATIONAL DIAGRAM
Typical Performance Curves
1.208
1.207
1.206
1.205
310
290
270
250
230
210
190
170
150
V
= 24V
IN
V
= 2.5V
1.204
1.203
1.202
1.201
1.200
1.199
1.198
IN
V = 12V
IN
V
= 12V
IN
V
0
= 2.5V
25
IN
V
= 24V
IN
-40
-10
0
25
TEMP (°C)
60
85
100
-40
-10
60
85
100
TEMP (°C)
FIGURE 5. V CURRENT
IN
FIGURE 4. UV/OV RISING THRESHOLD
Once the voltage monitoring FAULT is resolved and where
applicable, the SEQ_EN(#) is satisfied, sequencing of the
ENABLE_X(#) outputs begins. When sequence enabled the
ENABLE_A, ENABLE_B, ENABLE_C and lastly
ENABLE_D are asserted in that order and when SEQ_EN is
disabled the order is reversed. See Figures 8 and 9
demonstrating the sequenced enabling and disabling of the
ENABLE outputs. The timing between ENABLE outputs is
set by the resistor values on the TB, TC, TD pins as shown.
Figure 10 illustrates the timing from either SEQ_EN and/or
VMONITOR being valid to ENABLE_A being asserted with a
10nF TIME capacitor. Figure 11 shows that ENABLE_X
Applications Usage
Using the ISL870XAEVAL1 Platform
The ISL870XAEVAL1 platform is the primary evaluation
board for this family of sequencers. See Figure 16 for
photograph and schematic.The evaluation board is shipped
with an ISL8702A mounted in the left position and with the
other device variants loose packed. In the following
discussion, test points names are bold on initial occurrence
for identification.
The V test point is the chip bias and can be biased from
IN
3.3V to 24V. The VHI test point is for the ENABLE and
FAULT pull-up voltage which are limited to a maximum of
outputs are pulled low even before V = 1V. This is critical
IN
to ensure that a false enable is not signaled. Figure 12
illustrates the SEQ_EN# input disabling and enabling the
ISL8705A ENABLE# outputs. Notice the reversal in order
and delay timing from ENABLE_X# to ENABLE_X#.
Figure 13 shows the time from SEQ_EN transition with the
voltage ramping across the TIME capacitor to TIME Vth
being met. This results in the immediate pull down of the
TIME pin and simultaneous ENABLE_A enabling.
24V independent of V . The UV/OV resistor divider is set so
that a nominal 12V on the VMONITOR test point is compliant
and with a rising OV set at 13.2V and a falling UV set at
IN
10.7V. These three test points (V ,VHI and VMONITOR)
IN
are brought out separately for maximum flexibility in
evaluation.
VMONITOR ramping up and down through the UV and OV
levels will result in the FAULT output signaling the out of
bound conditions by being released to pull high to the VHI
voltage as shown in Figures 6 and 7.
FN6381.0
October 12, 2006
7
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
VMON FALLING
VMON RISING
VMON > OV
VMON > OV
LEVEL
VMON > UV
LEVEL
LEVEL
VMON > UV
LEVEL
FAULT OUTPUT
FAULT OUTPUT
FIGURE 6. VMONITOR RISING TO FAULT
FIGURE 7. VMONITOR FALLING TO FAULT
R
= 3k
TB
DELAY = 5ms
R
= 3k
TB
DELAY = 5ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
FIGURE 9. ENABLE_X TO ENABLE_X DISABLING
FIGURE 8. ENABLE_X TO ENABLE_X ENABLING
V
RISING
IN
C
= 10nF
TIME
DELAY = 8.5ms
ENABLE OUTPUTS TRACKS V TO < 0.8V
IN
1V/DIV
10ms/DIV
FIGURE 10. V /SEQ_EN VALID TO ENABLE_A
IN
FIGURE 11. ENABLE AS V RISES
IN
FN6381.0
October 12, 2006
8
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
SEQ_EN#
SEQ_EN
TIME
ENABLE_A
ENABLE_A#
ENABLE_B#
0.5V/DIV
ENABLE_C#
ENABLE_D#
FIGURE 12. ISL8705A ENABLE_X# TO ENABLE_X#
FIGURE 13. SEQ_EN TO ENABLE_A
VMONITOR OV
VMONITOR UV
FAULT = LOW
8µs/DIV
FIGURE 14. OV AND UV TRANSIENT IMMUNITY
FN6381.0
October 12, 2006
9
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Application Recommendations
Best practices V decoupling is required, a 1μF capacitor is
IN
recommended.
PIN 4
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700A, ISL8702A, ISL8704A parts
due to the ENABLEA and OV pins being adjacent. This
coupling can be reduced by adding a ground trace between
UV and the ENABLE/FAULT signals, as shown in Figure 15.
The PCB traces on OV and UV should be kept as small as
practical and the ENABLE_X and FAULT traces should
ideally not be routed under/over the OV/UV traces on
different PCB layers unless there is a ground or power plane
in between. Other methods that can be used to eliminate this
issue are by reducing the value of the resistors in the
network connected to UV and OV (R2, R3, R5 in Figure 16)
or by adding small decoupling capacitors to OV and UV (C2
and C7 in Figure 16). Both these methods act to reduce the
AC impedance at the nodes, although the latter method acts
to filter the signals which will also cause an increase in the
time that a UV/OV fault takes to be detected.
GND
PIN 5
FIGURE 15. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5
When the ISL870XA is implemented on a hot swappable
card that is plugged into an always powered passive back
plane an RC filter is required on the V pin to prevent a high
IN
dv/dt transient. With the already existing 1μF decoupling
capacitor the addition of a small series R (>50Ω) to provide a
time constant >50μs is all that is necessary.
FN6381.0
October 12, 2006
10
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
.
PULL-UP
RESISTORS
TIMING
COMPONENTS
UV/OV SET
RESISTORS
FIGURE 16. ISL870XAEVAL1 PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL
TABLE 1. ISL870XAEVAL1 LEFT CHANNEL COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
ISL8702A, Quad Under/Overvoltage Sequencer
UV Resistor for Divider String
COMPONENT DESCRIPTION
Intersil, ISL8702A, Quad Under/Overvoltage Sequencer
1.1kΩ 1%, 0603
U1
R3
R2
R5
C1
R1
R9
R7
VMONITOR Resistor for Divider String
OV Resistor for Divider String
88.7kΩ 1%, 0603
9.1kΩ 1%, 0603
C
R
R
R
Sets Delay from Sequence Start to First ENABLE
0.01μF, 0603
TIME
Sets Delay from Third to Fourth ENABLE
Sets Delay from First to Second ENABLE
Sets Delay from Second to Third ENABLE
120kΩ 1%, 0603
TD
TB
TC
3.01kΩ 1%, 0603
51kΩ 1%, 0603
R4, R6, R8, R10, ENABLE_X(#) and FAULT Pull-up Resistors
R11
4kΩ 10%, 0402
C3
Decoupling Capacitor
1μF, 0603
FN6381.0
October 12, 2006
11
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6381.0
October 12, 2006
12
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