ISL6840IU-T [ROCHESTER]
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MO-187AA, MSOP-8;
| 型号： | ISL6840IU-T |
| 厂家： | 
Rochester Electronics |
| 描述： | 1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MO-187AA, MSOP-8 信息通信管理 开关 光电二极管 |
| 文件： | 总13页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6840, ISL6841, ISL6842, ISL6843, ISL6845
®
数据资料
December 2008
FN9124.4
改善的业界标准单端电流模式 PWM 控制器
主要特点
•
•
•
•
•
•
•
1A MOSFET 驱动器
60μA 启动电流, 其峰值为 100μA
控制到输出的延迟是 30ns
高峰值电流模式控制固有的快速瞬变反应
可调开关频率高达 2MHz
20ns 升降时间以 1nF 输出负载
平衡的定时电容的放电电流适合于精确死区时间/最
大占空比控制
可调频率、低电源、电流模式 PWM 控制器的系列：
ISL6840, ISL6841, ISL6842、ISL6843、ISL6844 和
ISL6845 是设计用于大范围能量变换应用，包括升压、反馈
和隔离输出的结构。峰值电流模式控制可有效地处理能量瞬
变且有固有的过流保护。
这个先进的 BiCMOS 设计不但兼容了业界标准 384x 控制器
系列的引脚，而且显著地改善了其性能。其特点包括低运作
电流、60μA 启动电流、可调工作频率高达 2MHz 和 20ns 升
降时间的高峰值电流驱动力。
•
•
•
•
高带宽误差放大器
遍及输入、负载和温度范围的精密的容差电压基准
精密的容差电流门限值
不含 Pb 的包装
零件号码
上升欠压切断
最大占空比
应用
ISL6840
ISL6841
ISL6842
ISL6843
ISL6844
ISL6845
7.0V
7.0V
100%
50%
•
•
•
•
•
•
•
电信和信息电源
无线基站电源
档案服务器电源
工业动力系统
14.4V
8.4V
100%
100%
50%
个人计算机电源
隔离降压和反馈变换器
升压调节器
14.4V
8.4V
50%
插脚引线
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
(8-PIN SOIC, MSOP)
顶视图
COMP
FB
1
2
3
4
8
7
6
5
VREF
VDD
OUT
GND
CS
RTCT
(8-PIN DFN)
顶视图
COMP
VREF
1
2
3
4
8
7
6
5
FB
CS
VDD
OUT
GND
RTCT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143|Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
零件号码
温度范围
(°C)
包装
包装图号 #
定购资料
零件号码
温度范围
(°C)
包装
包装图号 #
8 Ld 2x3
DFN
(Pb-free)
8 Ld 2x3
DFN
ISL6844IRZ-T*
(See Note)
-40 to 105
-40 to 105
L8.2x3
L8.2x3
ISL6840IB
-40 to 105
-40 to 105
8 Ld SOIC
M8.15
M8.15
ISL6845IRZ-T
(See Note)
ISL6840IBZ
(See Note)
8 Ld SOIC
(Pb-free)
(Pb-free)
Add -T to part number for Tape and Reel packaging
ISL6840IU
-40 to 105
8 Ld MSOP
M8.118
*Contact Factory for Availability
ISL6840IUZ
(See Note)
8 Ld MSOP
(Pb-free)
-40 to 105
-40 to 105
-40 to 105
M8.118
M8.15
M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020
ISL6841IB
8 Ld SOIC
ISL6841IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6841IU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
M8.15
ISL6841IUZ
(See Note)
8 Ld MSOP
(Pb-free)
.
ISL6842IB
8 Ld SOIC
ISL6842IBZ
(See Note)
8 Ld SOIC
(Pb-free)
M8.15
ISL6842IU
8 Ld MSOP
M8.118
M8.118
M8.15
ISL6842IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6843IB
8 Ld SOIC
ISL6843IBZ
(See Note)
8 Ld SOIC
(Pb-free)
M8.15
ISL6843IU
8 Ld MSOP
M8.118
ISL6843IUZ
(See Note)
8 Ld MSOP
(Pb-free)
-40 to 105
-40 to 105
-40 to 105
M8.118
M8.15
M8.15
ISL6844IB
8 Ld SOIC
ISL6844IBZ
(See Note)
8 Ld SOIC
(Pb-free)
ISL6844IU
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
8 Ld MSOP
M8.118
M8.118
M8.15
ISL6844IUZ
(See Note)
8 Ld MSOP
(Pb-free)
ISL6845IB
8 Ld SOIC
ISL6845IBZ
(See Note)
8 Ld SOIC
(Pb-free)
M8.15
ISL6845IU
8 Ld MSOP
M8.118
M8.118
ISL6845IUZ
(See Note)
8 Ld MSOP
(Pb-free)
8 Ld 2x3
DFN
(Pb-free)
8 Ld 2x3
DFN
(Pb-free)
8 Ld 2x3
DFN
(Pb-free)
8 Ld 2x3
DFN
ISL6840IRZ-T*
(See Note)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
L8.2x3
L8.2x3
L8.2x3
L8.2x3
ISL6841IRZ-T*
(See Note)
ISL6842IRZ-T
(See Note)
ISL6843IRZ-T
(See Note)
(Pb-free)
2
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
VREF
5.00 V
VDD
VREF
UVLO
COMPARATOR
ENABLE
VDD OK
+
-
-
VREF FAULT
+
+
BG
-
VREF
UV COMPARATOR
GND
4.65V ↓ 4.80V ↑
A
BG
2.5 V
A=0.5
PWM
COMPARATOR
+
-
CS
100mV
ERROR
AMPLIFIER
2R
1.1V
CLAMP
ISL6841/4/5 ONLY
+
-
FB
Q
R
T
Q
COMP
OUT
VREF
S
R
Q
Q
2.6V
0.7V
RESET
DOMINANT
ON
OSCILLATOR
COMPARATOR
-
RTCT
+
CLOCK
P/N
UVLO ON/OFF
7.0 / 6.6V
14.3 / 8.8V
8.4 / 7.2V
8.4mA
ON
-40, -41
-42, -44
-43, -45
内部电路结构
3
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
CR5
+3.3V
+1.8V
C21
+ C15
+ C16
T1
R21
VIN+
C4
R3
CR4
+
+
C22
C17
C6
C20
C2
C19
CR2
C5
RETURN
CR6
Q1
R1
36-75V
R16
U2
R17
R18
C1
C3
R19
C14
R4
R22
R15
C13
VIN-
U3
R27
R20
U4
R26
COMP
VREF
CS
V
DD
FB
OUT
RTCT
GND
ISL684x
R6
R10
CR1
Q3
C12
C8
VR1
C11
R13
典型应用: 48V 输入双输出反馈转换器
4
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
额定值
热性能的资料
JA (oC/W)
θ
JC (oC/W)
6
N/A
Supply Voltage, VDD ------------------------------GND-0.3V to +20V
OUT------------------------------------------ GND - 0.3V to VDD + 0.3V
Signal Pins-------------------------------------------GND-0.3V to 6.0V
Peak GATE Current --------------------------------------------------- 1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) ----------- 2000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) ------------ 1000V
Thermal Resistance (Typical, Note 1)
θ
DFN Package (Note 2) ---------------------77
SOIC Package------------------------------- 100
MSOP Package------------------------------130
N/A
Maximum Junction Temperature ----------------------- -55oC to 150oC
Maximum Storage Temperature Range -------------- -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) ------------------300oC
(SOIC – Lead Tips Only)
运行条件
Supply Voltage Range (Typical)
ISL6840/1 --------------------------------------------- 7.5V-14VDC
ISL6843/5 --------------------------------------------------9-16VDC
ISL6842/4 ----------------------------------------------15V-18VDC
Temperature Range
ISL684xlx--------------------------------------------40oC to 105oC
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
Notes:
1)
θ
JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for
details.
2) For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3) All voltages are to be measured with respect to GND, unless otherwise specified.
Electrical Specifications
电气规范
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic.
VDD = 15V (Note 7), RT = 10KΩ, CT = 3.3nF, TA = -40oC to 105oC (Note 4), Typical values are at TA= 25oC.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT
START Threshold (ISL6840, ISL6841)
START Threshold (ISL6843, ISL6845)
START Threshold (ISL6842, ISL6844)
STOP Threshold (ISL6840, ISL6841)
STOP Threshold (ISL6843, ISL6845)
STOP Threshold (ISL6842, ISL6844)
Hysteresis (ISL6840, ISL6841)
6.5
7.8
13.3
6.1
6.7
8.0
-
7.0
8.4
14.3
6.6
7.2
8.8
0.4
0.8
7.5
9.0
15.3
6.9
7.7
9.6
-
V
V
V
V
V
V
V
Hysteresis (ISL6843, ISL6845)
-
-
Hysteresis (ISL6842, ISL6844)
-
5.4
-
V
Start-Up Current, IDD
VDD < START Threshold
(Note 5)
-
-
-
60
3.3
4.1
100
4.0
-
μA
mA
mA
Operating Current, IDD
Operating Supply Current, ID
Includes 1nF GATE loading
REFERENCE VOLTAGE
Over line (VDD = 12V to 18V), load,
temp
Overall Accuracy
4.925
5.000
5.050
V
Long Term Stability
Fault Voltage
TA = 125oC, 1000 hours (Note 6)
-
5
-
mV
V
4.40
4.60
4.65
4.80
4.85
VREF Good Voltage
VREF-
0.05
V
Hysteresis
50
165
-
250
-
mV
mA
Current Limit, Sourcing
-20
5
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Current Limit, Sinking
5
-
-
mA
Electrical Specifications
电气规范
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic.
VDD = 15V (Note 6), RT = 10KΩ, CT = 3.3nF, TA = -40oC to 105oC (Note 3), Typical values are at TA= 25oC. (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT SENSE
Input Bias Current
CS Offset Voltage
VCS = 1V
-1.0
95
-
1
μA
VCS = 0V (Note 6)
VCS = 0V (Note 6)
100
1.15
105
1.30
mV
COMP to PWM Comparator
Offset Voltage
0.80
V
V
Input Signal, Maximum
0.91
2.5
-
0.97
3
1.03
3.5
40
0 < VCS < 910mV, VFB = 0V
(Note 6)
Gain, ACS = DVCOMP/DVCS
CS to OUT Delay
V/V
nS
(Note 6)
25
ERROR AMPLIFIER
Open Loop Voltage Gain
Unity Gain Bandwidth
Reference Voltage
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
(Note 6)
60
3.5
90
-
dB
MHz
V
(Note 6)
5
-
VFB = VCOMP
2.475
-1.0
1.0
2.500
2.525
-0.2
1.0
V
V
V
V
FB = 0
μA
mA
mA
V
COMP = 1.5V, VFB = 2.7V
COMP = 1.5V, VFB = 2.3V
FB = 2.3V
-
-
-
-0.4
4.80
0.4
-
VREF
1.0
-
-
COMP VOL
VFB = 2.7V
-
V
Frequency = 120Hz, VDD = 12V to 18V
(Note 6)
60
80
PSRR
dB
OSCILLATOR
Frequency Accuracy
Initial, TJ = 25oC
T = 25oC (F18V - F12V)/F12V
(Note 6)
49
52
0.2
-
55
1.0
5
KHz
%
Frequency Variation with VDD
Temperature Stability
Amplitude, Peak to Peak
RTCT Discharge Voltage
Discharge Current
-
-
-
%
1.9
0.7
8.4
-
V
-
-
V
RTCT = 2.0V
7.2
9.5
mA
OUTPUT
Gate VOH
VDD - OUT, IOUT = -200mA
OUT - GND, IOUT = 200mA
COUT = 1nF (Note 6)
-
-
-
-
-
1.0
1.0
1.0
20
2.0
2.0
-
V
V
Gate VOL
Peak Output Current
Rise Time
A
COUT = 1nF (Note 6)
40
40
nS
nS
Fall Time
COUT = 1nF (Note 6)
20
PWM
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844, ISL6845
94
47
96
48
-
-
%
%
Maximum Duty Cycle
6
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications
电气规范
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic.
VDD = 15V (Note 6), RT = 10KΩ, CT = 3.3nF, TA = -40oC to 105oC (Note 3), Typical values are at TA= 25oC. (continued)
Minimum Duty Cycle
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844, ISL6845
-
-
-
-
0
0
%
%
Notes:
4. Specifications at -40oC are guaranteed by design, not production tested.
5. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
6. Guaranteed by design, not 100% tested in production.
7. Adjust VDD above the start threshold and then lower to 15V.
典型性能曲线图
1.001
1
1.02
1.01
1
0.999
0.998
0.997
0.996
0.99
0.98
0.97
0.995
-40
-10
20
50
80
110
-40 -25 -10
5
20 35 50 65 80 95 110
°
o
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
1-103
1.002
CT=
100pF
1
0.998
0.996
100
10
1
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
0.994
10 20 30 40 50 60
70 80 90 100
-40 -25 -10
5
20 35 50 65 80 95 110
Ω
RT (k
)
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RTCT vs FREQUENCY
7
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
各管脚简介
要优化抗扰度，用一个陶瓷电容器尽可能靠近并挎接在 VDD
RTCT
和 GND 引脚。
这是振荡器定时控制引脚。由这引脚间连接一电阻(RT)到
VREF
这是 5.00V 的基准电压输出端，且有+1.0/-1.5%的容差遍及
VREF 与和一定时电容(CT)到 GND 之间可设置工作频率和最大
输入、负载和温度范围。可连接 0.1μF 至 3.3μF 的电容至
GND 以作滤波这输出所需。
占空比。振荡器产生一个可调频率高达 2.0MHz 的锯齿波。
充电时间（TC)、 放电时间（TD）、 开关频率（f）和最大占
空比（Dmax）可用以下等式计算:
功能概述
TC ≈ 0.583 • RT • CT
(EQ. 1)
主要特点
0.0083 • RT − 4.3
TD ≈ −RT • CT • ln(
)
(EQ. 2)
ISL684x 电流模式 PWMs 为那些低成本反激式和正激式拓扑
结构的应用提供了一个理想的选择。因为其改善性能的远胜
过于业界标准零件, 所以 ISL684x 是新设计或更新现存设计的
优先选择。
0.0083 • RT − 2.4
f = 1/(TC +TD )
Dmax = TC • f
(EQ. 3)
(EQ. 4)
振荡器
在选择电容和电阻值所需指定的频率时，可用图4作为指南.
ISL684x 控制器有一个可调频率高达 2MHz 的锯齿振荡器。
在 RTCT 引脚连接一电阻至 VREF 和电容至 GND 可设置工
作频率。 (电阻和电容所需的指定頻率可參見图 4。)
软启动运作
COMP
COMP 是误差放大器的输出端和 PWM 比较器的输入端。控
制环频率补偿网络应连接在 COMP 和 FB 引脚之间。
FB
软启动必須在外部实施。以一方法为例 說明如下,电压钳位在
COMP。
通过这个引脚输出电压的反馈连接到误差放大器的倒相输
入， 而误差放大器的正相输入连接于内部的基准电压。
CS
VREF
COMP
GND
这是 PWM 比较器电流检测输入端。 输入信号的范围在典型
值 0 到 1.0V，且有 100mV 内部偏压。
GND
器件上所有功能和电源地都以这个引脚为基准。
OUT
这是电源开关元件的驱动输出端。它具有 1.0A 峰值电流驱动
MOSFET 门极。当 VDD 低于 UVLO 门限值时，门极输出就
会降低。
SOFT START
FIGURE 5. SOFT START
VDD
VDD 是电源输入端。总供应电流取决于 OUT 输出负载，而
总 IDD 电流是工作电流和平均输出电流之和。平均输出电流
与工作频率（f）和 MOSFET 门极电荷（Qg）成正比，可用
以下公式计算：
门极驱动器
ISL684x 可灌出和吸收1A 峰值电流。要限制峰值电流通過IC,
可放置一个外部电阻在IC的推拉输出(OUT引脚)和MOSFET
門极之間。而这个小串联电阻能阻尼由线组寄生电感和FET
的输入电容的共振所产生的振荡。
IOUT = Qg • f
(EQ. 5)
8
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
斜坡补尝
应用的最大占空比少于 50%时, 斜坡补尝可提高抗扰度, 尤其
在负载较小时。 测试表明：要优化抗扰度则需用一定数量的
斜坡补偿, 一般約是 10% 全方位的电流反馈信号。 若应用的
占空比大于 50% 时, 则需用斜坡补偿来防止不稳定，而所需
的最低量斜坡补偿是相当于电感下坡的一半。外加过量的斜
坡补偿，会导致控制环路由电流模式控制转化为电压模式控
制。
DOWNSLOPE
CURRENT SENSE SIGNAL
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
用以下方式可增加傾斜补偿的 CS 信号:
RTCT
VREF
CS
SLOPE COMPENSATION
FIGURE 7. SLOPE COMPENSATION
故障保护
VREF 跌落低于 4.65V 时会产生故障。当检测出故障时，
OUT 输出就会被截止。VREF 超过 4.80V 时, 则排除了故障,
且 OUT 会重新输出。
接地面
为这个器件能理想操作，应要仔细布局，特别是应用一
个好的接地面。其中独一部分的接地面必须设置为高的
di/dt 电流输出， 且VDD 必须以一个好的高频电容直接
连接到地(GND)。
9
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Small Outline Plastic Packages (SOIC)
N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
L
B M
H
E
SYMBOL
INCHES
MILLIMETERS
NOTES
-B-
MIN
MAX
MIN
MAX
1
2
3
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
-
-
SEATING PLANE
A
-A-
h x 45o
D
9
-
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-C-
α
3
4
-
e
A1
C
B
0.10(0.004)
0.050 BSC
1.27 BSC
0.25(0.010)
M
C
A M B S
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
5
6
7
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in
Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs and are measured at Datum Plane. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
L
N
α
8
8
0O
8O
0O
8O
Rev.0 12/93
4. Dimension “E” does not include interlead flash or
protrusions and are measured at Datum Plane. Interlead
flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a
visual index feature must be located within the
crosshatched area.
6.
“L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or
greater above the seating plane, shall not exceed a
maximum value of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are for reference only
10
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
M8.118 (JEDEC MO-187AA)
Mini Small Outline Plastic Packages
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
(MSOP)
N
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
E1
E
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
0.94
0.05
0.75
0.25
0.09
2.95
2.95
1.10
0.15
0.95
0.36
0.20
3.05
3.05
-
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B C
-
TOP VIEW
9
-
θ
4X
0.25
(0.010)
R1
L
c
R
GAUGE
PLANE
D
3
4
-
E1
e
SEATING
PLANE
-C-
θ
0.026 BSC
0.65 BSC
4X
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
-
SEATING
PLANE
0.10 (0.004)
-A-
C
C
b
L1
N
0.037 REF
0.95 REF
-H-
A1
e
8
8
7
-
D
0.20 (0.008)
C
R
0.003
0.003
5O
-
-
0.07
0.07
5O
-
-
SIDE VIEW
a
R1
0
-
C
L
15O
6O
15O
6O
-
E1
-B-
0O
0O
-
0.20 (0.008)
C D
END VIEW
α
Notes:
Rev.2 01/03
1. These package dimensions are within allowable
dimensions of JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs and are measured at Datum Plane. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or
protrusions and are measured at Datum Plane.Interlead
flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. Formed leads shall be planar with respect to one another
within 0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion.
Allowable dambar protrusion shall be 0.08mm (0.003
inch) total in excess of “b” dimension at maximum
material condition. Minimum space between protrusion
and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A- and -B- to be determined at Datum plane
-H-.
11. Controlling dimension: MILLIMETER. Converted inch
dimensions are for reference only.
11
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Dual Flat No-Lead Plastic Package (DFN)
2X
L8.2x3
0.15
C A
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
NOTES
A
A1
A3
b
0.90
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
0.32
1.75
1.90
-
E
-
6
INDEX
AREA
5,8
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
SIDE VIEW
C
A3
SEATING
PLANE
L
0.40
0.50
8
N
8
2
D2
D2/2
2
7
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10
M
C A B
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C
C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by
Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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