ISL6227IA [ROCHESTER]
DUAL SWITCHING CONTROLLER, 345kHz SWITCHING FREQ-MAX, PDSO28, 0.150 INCH, PLASTIC, SSOP-28;型号: | ISL6227IA |
厂家: | Rochester Electronics |
描述: | DUAL SWITCHING CONTROLLER, 345kHz SWITCHING FREQ-MAX, PDSO28, 0.150 INCH, PLASTIC, SSOP-28 开关 光电二极管 |
文件: | 总28页 (文件大小:1524K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6227
®
Data Sheet
May 4, 2009
FN9094.7
Dual Mobile-Friendly PWM Controller with
DDR Option
Features
• Provides Regulated Output Voltage in the Range 0.9V to
5.5V
The ISL6227 dual PWM controller delivers high efficiency
precision voltage regulation from two synchronous buck DC/DC
converters. It was designed especially to provide power
regulation for DDR memory, chipsets, graphics and other
system electronics in Notebook PCs. The ISL6227’s wide
input voltage range capability allows for voltage conversion
directly from AC/DC adaptor or Li-Ion battery pack.
• Operates From an Input Battery Voltage Range of 5V to
28V or From 3.3V/5V System Rail
• Complete DDR1 and DDR2 Memory Power Solution with
VTT Tracking VDDQ/2 and a VDDQ/2 Buffered Reference
Output
• Flexible PWM or HYS Plus PWM Mode Selection with
HYS Diode Emulation at Light Loads for Higher System
Efficiency
Automatic mode transition of constant-frequency synchronous
rectification at heavy load, and hysteretic (HYS)
diode-emulation at light load, assure high efficiency over a wide
range of conditions. The HYS mode of operation can be
disabled separately on each PWM converter if
• r
DS(ON)
Current Sensing
• Excellent Dynamic Response With Voltage Feed-Forward
and Current Mode Control Accommodating Wide Range
LC Filter Selections
constant-frequency continuous-conduction operation is desired
for all load levels. Efficiency is further enhanced by using the
lower MOSFET r
DS(ON)
as the current sense element.
• Undervoltage Lock-Out on VCC Pin
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and load transients. Input current
ripple is minimized by channel-to-channel PWM phase shift
of 0°, 90° or 180° (determined by input voltage and status of
the DDR pin).
• Power-Good, Overcurrent, Overvoltage, Undervoltage
Protection for Both Channels
• Synchronized 300kHz PWM Operation in PWM Mode
• Pb-Free Available (RoHS compliant)
Applications
The ISL6227 can control two independent output voltages
adjustable from 0.9V to 5.5V, or by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
• Notebook PCs and Desknotes
• Tablet PCs/Slates
• Hand-Held Portable Instruments
Ordering Information
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
In dual power supply applications the ISL6227 monitors the
output voltage of both CH1 and CH2. An independent PGOOD
(power good) signal is asserted for each channel after the
soft-start sequence has completed, and the output voltage is
within PGOOD window. In DDR mode CH1 generates the only
PGOOD signal.
ISL6227CA* ISL 6227CA -10 to +100 28 Ld QSOP M28.15
ISL6227CAZ* ISL 6227CAZ -10 to +100 28 Ld QSOP M28.15
(Note)
(Pb-Free)
ISL6227IA*
ISL 6227IA
-40 to +100 28 Ld QSOP M28.15
ISL6227IAZ* ISL 6227IAZ -40 to +100 28 Ld QSOP M28.15
(Note) (Pb-Free)
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage re-enters
regulation, PGOOD will go HIGH and normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage
ISL6227HRZ* ISL 6227HRZ -10 to +100 28 Ld QFN
(Note) (Pb-Free)
L28.5x5
ISL6227IRZ* ISL 6227IRZ -40 to +100 28 Ld QFN
(Note) (Pb-Free)
L28.5x5
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
drop across the r
of the lower MOSFET. If more precise
DS(ON)
current-sensing is required, an external current sense resistor
may be used.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6227
Pinouts
ISL6227
ISL6227
28 LD QSOP
28 LD 5X5 QFN
TOP VIEW
TOP VIEW
1
2
28
27
26
25
24
23
22
21
20
19
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
VCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
ISEN2
3
28 27 26 25 24 23 22
4
1
2
3
4
5
6
7
21
20
19
18
17
16
15
UGATE2
PHASE1
UGATE1
BOOT1
ISEN1
5
BOOT2
ISEN2
6
7
GND
29
8
EN1
EN2
EN2
9
VOUT1
VSEN1
VOUT2
VSEN2
EN1
VOUT2
VSEN2
OCSET2
10
VOUT1
VSEN1
OCSET1 11
SOFT1 12
DDR 13
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
8
9
10 11 12 13 14
VIN 14
Generic Application Circuits
OCSET1
Q1
Q2
L1
V
OUT1
+1.80V
PWM1
+
C1
V
IN
EN1
EN2
+5V TO +28V
Q3
Q4
VCC
L2
V
OUT2
DDR
PWM2
+5V
OCSET2
+1.20V
+
C2
ISL6227 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
OCSET1
Q1
Q2
L1
VDDQ
+2.50V
PWM1
+
C1
V
EN1
EN2
IN
+5V TO 28V
Q3
Q4
VCC
L2
DDR
VTT
PWM2
+5V
PG2/VREF
OCSET2
+1.25V
+
C2
VREF
+1.25V
ISL6227 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
FN9094.7
May 4, 2009
2
ISL6227
Absolute Maximum Ratings
Thermal Information
Bias Voltage, V . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.5V
CC
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +28.0V
IN
QSOP Package (Note 2)
80
36
N/A
6
. . . . . . . . . . . . .
QFN Package (Notes 3, 4)
PHASE, UGATE . . . . . . . . . . . . . . . . . . . GND -5V (Note 1) to 33.0V
BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +33.0V
BOOT with Respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V
. . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
+ 0.3V
CC
Recommended Operating Conditions
Bias Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.0V ±5%
CC
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.0V to +28.0V
IN
Ambient Temperature Range . . . . . . . . . . . . . . . . . -10°C to +100°C
Junction Temperature Range. . . . . . . . . . . . . . . . . -10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. 250ns transient. See Confining The Negative Phase Node Voltage Swing in Application Information Section
2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
5. Limits established by characterization and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER
VCC SUPPLY
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Bias Current
I
LGATEx, UGATEx Open, VSENx forced above
regulation point, V > 5V
IN
-
-
1.8
-
3.0
1
mA
µA
CC
Shut-down Current
VCC UVLO
I
CCSN
Rising VCC Threshold
Falling VCC Threshold
V
4.3
4
4.45
4.14
4.5
V
V
CCU
CCD
V
4.34
V
IN
Input Voltage Pin Current (Sink)
Shut-Down Current
I
-
-
-
-
35
1
µA
µA
VIN
I
VINS
OSCILLATOR
PWM1 Oscillator Frequency
f
Commercial, ISL6227C
Industrial, ISL6227I
255
300
300
2
345
kHz
kHz
V
c
240
345
Ramp Amplitude, pk-pk
Ramp Amplitude, pk-pk
Ramp Offset
V
V
V
V
= 16V (Note 5)
= 5V (Note 5)
-
-
-
-
-
-
-
-
-
-
R1
R2
IN
IN
0.625
1
V
V
(Note 5)
V
ROFF
Ramp/V Gain
IN
G
V
V
≥ 4.2V (Note 5)
≤ 4.1V (Note 5)
125
250
mV/V
mV/V
RB1
RB2
IN
Ramp/V Gain
IN
G
IN
REFERENCE AND SOFT-START
Internal Reference Voltage
V
-
0.9
-
-
V
REF
Reference Voltage Accuracy
-1.0
+1.0
%
FN9094.7
May 4, 2009
3
ISL6227
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
Soft-Start Current During Start-Up
Soft-Start Complete Threshold
PWM CONVERTERS
SYMBOL
TEST CONDITIONS
MIN
TYP
-4.5
1.5
MAX
UNITS
µA
I
-
-
-
-
SOFT
V
(Note 5)
V
ST
Load Regulation
0.0mA < I
(Note 5)
< 5.0A; 5.0V < V
< 28.0V
BATT
-2.0
-
+2.0
%
nA
%
VOUT1
VSEN Pin Bias Current
I
-
-
80
4
-
-
VSEN
Minimum Duty Cycle
D
min
Maximum Duty Cycle
D
-
87
134
75
115
-
%
max
VOUT Pin Input Impedance
Undervoltage Shut-Down Level
Overvoltage Protection
I
VOUT = 5V
-
-
kΩ
%
VOUT
V
Fraction of the set point; ~2µs noise filter
Fraction of the set point; ~2µs noise filter
70
110
80
-
UVL
V
%
OVP1
GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
R
V
V
V
V
= 5V
= 5V
= 5V
= 5V
-
-
-
-
4
8
4
8
3
Ω
Ω
Ω
Ω
2UGPUP
CC
CC
CC
CC
R
2.3
4
2UGPDN
R
R
2LGPUP
1.1
2LGPDN
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
ISEN Sourcing Current
OCSET Sourcing Current Range
EN - Low (Off)
V
Fraction of the set point; ~3µs noise filter
Fraction of the set point; ~3µs noise filter.
84
89
92
120
1
%
%
µA
V
PG-
V
110
115
PG+
I
V
= 5.5V
-
-
-
PGLKG
PULLUP
V
I
= -4mA
0.5
1
PGOOD
PGOOD
(Note 5)
-
-
-
-
-
-
260
20
0.8
-
µA
µA
V
2
-
EN - High (On)
2.0
-
V
Continuous-Conduction-Mode(CCM)
Enforced (HYS Operation Inhibited)
VOUTX pulled low
0.1
V
Automatic CCM/HYS Operation
Enabled
VOUTX connected to the output
0.9
-
-
V
DDR - Low (Off)
-
3
-
-
0.8
-
V
V
V
DDR - High (On)
DDR REF Output Voltage
V
DDR = 1, I
= 0...10mA
0.99*
V
1.01*
DDREF
REF
OC2
V
V
OC2
OC2
DDR REF Output Current
I
DDR = 1 (Note 5)
-
10
12
mA
DDREF
FN9094.7
May 4, 2009
4
ISL6227
Typical Operation Performance
100
100
90
80
70
60
50
40
30
20
EFF@ 5V
EFF@ 12V
EFF@ 12V
90
80
70
60
50
40
30
20
EFF@ 19.5V
EFF@ 19.5V
EFF@ 19.5V, PWM
EFF@ 5V, PWM
EFF@ 5V
EFF@ 12V, PWM
EFF@ 12V, PWM
EFF@ 5V, PWM
EFF@ 19.5V, PWM
0.10
10
0
10
0
0.01
1.00
10.0
0.01
0.10
1.00
10.0
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 1. EFFICIENCY OF CHANNEL 1, 2.5V,
HYS/PWM MODE
FIGURE 2. EFFICIENCY OF CHANNEL 2, 1.8V,
HYS/PWM MODE
2.54
1.83
V
@ 19.5V
OUT
V
V
@ 19.5V
@ 12V
OUT
2.53
2.52
2.51
2.50
2.49
2.48
2.47
1.82
1.81
1.80
1.79
V
@ 12V
OUT
OUT
V @ 12V, PWM
OUT
V
@ 19.5V, PWM
OUT
V
@ 19.5V, PWM
OUT
V
@ 5V, PWM
OUT
V
@ 5V, PWM
OUT
V
@ 12V, PWM
OUT
V
@ 5V
OUT
V
@ 5V
OUT
1.78
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 3. OUTPUT VOLTAGE OF CHANNEL 1 vs LOAD
FIGURE 4. OUTPUT VOLTAGE OF CHANNEL 2 vs LOAD
308
0.9025
75% QUANTILE
75% QUANTILE
0.9020
306
304
0.9015
FREQUENCY MEAN
302
0.9010
VREF MEAN
300
298
0.9005
0.9000
25% QUANTILE
25% QUANTILE
296
294
292
290
288
286
0.8995
0.8990
0.8985
0.8980
0.8975
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. SWITCHING FREQUENCY OVER-TEMPERATURE
FIGURE 6. REFERENCE VOLTAGE ACCURACY
OVER-TEMPERATURE
FN9094.7
May 4, 2009
5
ISL6227
Typical Operation Performance (Continued)
VO1
VO1
Vo1
VPHASE1
VPHASE1
ILO1
ILO1
VO2
VO2
FIGURE 7. LOAD TRANSIENT (0A TO 3A AT CHANNEL 1)
(DIODE EMULATION MODE)
FIGURE 8. LOAD TRANSIENT (0A TO 3A AT CHANNEL 1)
(FORCED PWM MODE)
VO1
VO1
VPHASE2
VPHASE2
ILO2
Ilo2
ILO2
VO2
Vo2
VO2
FIGURE 9. LOAD TRANSIENT (0A TO 2A AT CHANNEL 2)
(DIODE EMULATION MODE)
FIGURE 10. LOAD TRANSIENT (0A TO 3A AT CHANNEL 2)
(FORCED PWM MODE)
VIN1
VIN1
VO1
VO1
VO2
VO2
FIGURE 11. INPUT STEP-UP TRANSIENT AT PWM MODE
FIGURE 12. INPUT STEP-UP TRANSIENT AT HYS MODE
FN9094.7
May 4, 2009
6
ISL6227
Typical Operation Performance (Continued)
VIN1
VIN1
VO1
VO1
VO2
VO2
FIGURE 13. INPUT STEP-DOWN TRANSIENT AT PWM MODE
FIGURE 14. INPUT STEP-DOWN TRANSIENT AT HYS MODE
EN1
EN1
PG1
PG1
SOFT1
SOFT1
VO1
VO1
FIGURE 15. SOFT-START INTERVAL AT ZERO INITIAL
VOLTAGE OF VO
FIGURE 16. SOFT-START INTERVAL WITHNON-ZERO INITIAL
VOLTAGE OF VO
VO1
VO1
VPHASE1
VPHASE1
ILO1
ILO1
l
VO2
VO2
FIGURE 17. OPERATION AT LIGHT LOAD OF 100mA,
CHANNEL 1
FIGURE 18. OPERATION AT HEAVY LOAD OF 4A,
CHANNEL 1
FN9094.7
May 4, 2009
7
ISL6227
Typical Operation Performance (Continued)
VO1
VO1
Vo1
PG1
PG1
PG1
PG1
ILO1
ILO1
Ilo1
Vo2
VO2
VO2
Vo2
FIGURE 19. OVERCURRENT PROTECTION AT CHANNEL 1
FIGURE 20. SHORT-CIRCUIT PROTECTION AT CHANNEL 1
VO1
VO1
VPHASE1
VPHASE2
ILO1
ILO2
VO2
VO2
FIGURE 21. MODE TRANSITION OF HYS→ _PWM
FIGURE 22. MODE TRANSITION OF PWM→ HYS
VTT
EN1
EN1
OCSET
OCSET
PG1
PG1
VDDQ
SOFT1
VCC
Vo1
VO1
FIGURE 24. V
CC
POWER-UP IN DDR MODE
FIGURE 23. NORMAL SHUTDOWN, I
= 1.5A
OUT
FN9094.7
May 4, 2009
8
ISL6227
Typical Operation Performance (Continued)
VDDQ
VDDQ
PGOOD1
PGOOD1
VTT
VTT
IL1
IL1
FIGURE 25. VIN = 19V, VDDQ 3A STEP LOAD, VTT 0A LOAD
FIGURE 26. VIN = 19V, VDDQ 3A STEP LOAD, VTT 3A LOAD
VDDQ
VDDQ
VDDQ
VTT
VTT
VTT
OCSET2
OCSET2
OOCCSSEETT22
IL2
IL2
IL2
FIGURE 27. VIN = 19V, LOAD STEP ON VTT,
VDDQ HYS MODE, 0.14A
FIGURE 28. VIN = 19V, LOAD STEP ON VTT,
VDDQ PWM MODE, 0.14A
VDDQ
VTT
VTT
VIN
EN1
VTT
VDDQ
IL1
OCSET2
FIGURE 29. INPUT LINE TRANSIENT IN DDR MODE
FIGURE 30. VTT FOLLOWS VDDQ, ENABLE 2 IS HIGH
FN9094.7
May 4, 2009
9
ISL6227
OCSET1
Functional Pin Description
This pin is a buffered 0.9V internal reference voltage. A
resistor from this pin to ground sets the overcurrent
threshold for the first controller.
GND
Signal ground for the IC.
LGATE1, LGATE2
SOFT1, SOFT2
These are the outputs of the lower MOSFET drivers.
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 4.5µA
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin in the soft-start
process with the SOFT pin voltage as reference. When the
SOFT pin voltage is higher than 0.9V, the error amplifier will
use the internal 0.9V reference to regulate output voltage.
PGND1, PGND2
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters.
PHASE1, PHASE2
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
In the event of undervoltage and overcurrent shutdown, the
soft-start pin is pulled down though a 2k resistor to ground to
discharge the soft-start capacitor.
UGATE1, UGATE2
DDR
These pins provide the gate drive for the upper MOSFETs.
When the DDR pin is low, the chip can be used as a dual
switcher controller. The output voltage of the two channels
can be programmed independently by VSENx pin resistor
dividers. The PWM signals of Channel 1 and Channel 2 will
be synchronized 180° out-of-phase. When the DDR pin is
high, the chip transforms into a complete DDR memory
solution. The OCSET2 pin becomes an input through a
resistor divider tracking to VDDQ/2. The PG2/REF pin
becomes the output of the VDDQ/2 buffered voltage. The
VDDQ/2 voltage is also used as the reference to the error
amplifier by the second channel. The channel phase-shift
synchronization is determined by the VIN pin when DDR = 1
as described in VIN below.
BOOT1, BOOT2
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
ISEN1, ISEN2
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and Overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
VIN
EN1, EN2
This pin has multiple functions. When connected to battery
voltage, it provides battery voltage to the oscillator as a
feed-forward for the rejection of input voltage variation. The
ramp of the PWM comparator is proportional to the voltage
on this pin (see Table 1 and Table 2 for details). While the
DDR pin is high in the DDR application, and when the VIN
pin voltage is greater than 4.2V when connecting to a
battery, it commands 90° out-of-phase channel
synchronization, with the second channel lagging the first
channel, to reduce inter-channel interference. When the pin
voltage is less than 4.2V, this pin commands in-phase
channel synchronization.
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current is taken from VCC and VIN. EN1
and EN2 can be used independently to enable either
Channel 1 or Channel 2.
VOUT1, VOUT2
These pins, when connected to the converter’s respective
outputs, set the converter operating in a mixed hysteretic
mode or PWM mode, depending on the load conditions. It
also provides the voltage to the chip to clamp the PWM error
amplifier in hysteretic mode to achieve smooth HYS/PWM
transition. When connected to ground, these pins command
forced continuous conduction mode (PWM) at all load levels.
PG1
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is out of -11% to +15% of the set value.
VSEN1, VSEN2
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
FN9094.7
May 4, 2009
10
ISL6227
Typical Application
PG2/REF
This pin has a double function, depending on the mode of
operation.
Figures 31 and 32 show the application circuits of a dual
channel DC/DC converter for a notebook PC.
When the chip is used as a dual channel PWM controller
(DDR = 0), the pin provides an open drain PGOOD2 function
for the second channel the same way as PG1. The pin is
pulled low when the second channel output is out of
-11% to +15% of the set value.
The power supply in Figure 31 provides +2.5V and +1.8V
voltages for memory and the graphics interface chipset from
a +5.0VDC to a 28VDC battery voltage.
Figure 32 illustrates the application circuit for a DDR memory
power solution. The power supply shown in Figure 32
generates +2.5V VDDQ voltage from a battery. The +1.25V
VTT termination voltage tracks VDDQ/2 and is derived from
+2.5V VDDQ. To complete the DDR memory power
requirements, the +1.25V reference voltage is provided
through the PG2 pin.
In DDR mode (DDR = 1), this pin is the output of the buffer
amplifier that takes VDDQ/2 voltage applied to OCSET2 pin
from the resister divider. It can source a typical 10mA
current.
OCSET2
In a dual channel application with DDR = 0, a resistor from
this pin to ground sets the overcurrent threshold for the
second channel controller. Its voltage is the buffered internal
0.9V reference.
In the DDR application with DDR = 1, this pin connects to the
center point of a resistor divider tracking the VDDQ/2. This
voltage is then buffered by an amplifier voltage follower and
sent to the PG2/REF pin. It sets the reference voltage of
Channel 2 for its regulation.
VCC
This pin powers the controller.
FN9094.7
May 4, 2009
11
ISL6227
V
VCC (5V)
IN
Cdc
4.7µF
D1
D2
BAT54W
BAT54W
VCC
VIN
GND
DDR
Cin1
10
Cbt2
Cbt1
Rbt2
0.15µF
0.15µF
BOOT1
BOOT2
F
µ
Cin2
10µF
Rbt1
0Ω
0Ω
UGATE1
PHASE1
UGATE2
PHASE2
Lo1
4.7µH
Lo2
V2 (1.8V)
V1 (2.5V)
Q1
Q2
4.7µH
Rs2
2.0k
Rs1
2.0k
Rfb11
17.8k
ISEN1
ISEN2
LGATE2
PGND2
VOUT2
VSEN2
Co11
220µF 4.7µ
Co12
Co21
Co22
4.7
LGATE1
PGND1
VOUT1
VSEN1
F
Cfb2
220
µF
µF
Cfb1
0.01µF
0.01µF
FDS6912A
FDS6912A
Rfb21
10k
Rfb22
10k
PG1
PG2
EN2
Rfb12
10k
U1
EN1
SOFT1
SOFT2
OCSET2
OCSET1
Csoft2
0.01µF
Csoft1
0.01
F
µ
Rset2
100k
Rset1
100k
ISL6227
FIGURE 31. TYPICAL APPLICATION CIRCUIT AS DUAL SWITCHER, VOUT1 = 2.5V, VOUT = 1.8V
Vin
VCC (5V)
Cdc
4.7µF
D1
BAT54W
D2
VDDQ
BAT54W
VIN
VCC
GND
DDR
Cbt2
Cin1
10µF
Cbt1
0.15µF
Rbt1
Rbt2
Cin2
4.7µF
0.15µF
BOOT1
BOOT2
0Ω
0Ω
UGATE1
PHASE1
ISEN1
UGATE2
PHASE2
Lo1
4.6µH
Lo2
1.5µH
VTT (1.25V)
VDDQ (2.5V)
Q1
Q2
Rs2
1.0k
Rs1
2.0k
Rfb1
17.8k
ISEN2
Co21
220µF
Co11
4.7
F
Co22
4.7µF
Co13
LGATE1
PGND1
VOUT1
VSEN1
LGATE2
PGND2
F
µ
µ
220
Cfb1
0.01µF
FDS6912A
FDS6912A
VSEN2
Vref (VDDQ/2)
PG2_REF
Cref
4.7µF
VDDQ
VOUT2
PG1
Rfb12
10K
Rd1
10k
U1
EN1
EN2
OCSET2_VDDQ/2
SOFT1
VDDQ/2
Cf
0.1µF
Csoft2 (N/U)
0.01µF
Rd2
10k
OCSET1
SOFT2
Csoft1
0.01µF
Rset1
100k
ISL6227
FIGURE 32. TYPICAL APPLICATION AS DDR MEMORY POWER SUPPLY, VDDQ = 2.5V, VTT = 1.25V
FN9094.7
May 4, 2009
12
Block Diagram
BOOT1
UGATE1
PHASE1
PGND1
LGATE1
VCC
BOOT2
UGATE2
PHASE2
PGND2
LGATE2
VCC
PG1
EN1 VOUT1
VCC GND
VOUT2 EN2 REF/PG2
DDR = 1
DDR = 0
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
POR
MODE CHANGE COMP 1
MODE CHANGE COMP 2
ENABLE
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
PWM OR HYS MODE
HYSTERETIC COMPARATOR 2
HYSTERETIC COMPARATOR 1
ΔV
HYS
= 15mV
15pF
ΔV
= 15mV
HYS
OV UV
PGOOD
OV UV
PGOOD
15pF
1MΩ
DDR MODE
CONTROL
1MΩ
VOLTS/SEC
CLAMP
VOLTS/SEC
CLAMP
500kΩ
500kΩ
VSEN2
300kΩ
300kΩ
VSEN1
1.25pF
1.25pF
OC1 DDR OC2
4.4kΩ
4.4kΩ
(200kΩ, DDR = 1)
PWM1
PWM2
SOFT2
ERROR AMP 1
ERROR AMP 2
+
0.9V
REF
DDR = 0
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
DDR = 1
ISEN2
SOFT1
ISEN1
+
0.9V
REF
DDR EN1 EN2
VIN
CH1/CH2 φ
140Ω
140Ω
0
1
1
1
1
1
0V ⇔ 28.0V
4.2 < VIN < 28.0V
VIN < 4.2
180°
90°
0°
CURRENT
SAMPLE
CURRENT
SAMPLE
CURRENT
SAMPLE
CURRENT
SAMPLE
OCSET2
OCSET1
DDR = 0
0.9V REFERENCE
0.9V REFERENCE
+
DDR = 1
OC1
OC2
1/33.1
ISEN1
1/2.9
OCSET1
1/2.9
OCSET2
1/33.1
ISEN2
VIN
DDR
VCC
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
DDR VTT
REFERENCE
DDR VREF
BUFFER AMP
ISL6227
When the SOFT pin voltage reaches 0.9V, the output voltage
Theory of Operation
comes into regulation, (see block diagram). When the SOFT
voltage reaches 1.5V, the power good (PGOOD) and the
mode control is enabled. The soft-start process is depicted in
Figure 33.
Operation
The ISL6227 is a dual channel PWM controller intended for
use in power supplies for graphic chipsets, SDRAM, DDR
DRAM, or other low voltage power applications in modern
notebook and sub-notebook PCs. The IC integrates two
control circuits for two synchronous buck converters. The
output voltage of each controller can be set in the range of
0.9V to 5.5V by an external resistive divider.
EN
1
1.5V
The synchronous buck converters can operate from either
an unregulated DC source, such as a notebook battery, with
a voltage ranging from 5.0V to 28V, or from a regulated
system rail of 3.3V or 5V. In either operational mode the
controller is biased from the +5V source.
0.9V
SOFT
2
VOUT
3
PGOOD
4
The controllers operate in the current mode with input
voltage feed-forward which simplifies feedback loop
compensation and rejects input voltage variation. An
integrated feedback loop compensation dramatically
reduces the number of external components.
M1.00ms
Ch1 5.0V
Ch3 1.0V
Ch2 2.0V
Ch4 5.0V
FIGURE 33. START-UP
Depending on the load level, converters can operate either
in a fixed 300kHz frequency mode or in a HYS mode.
Switch-over to the HYS mode of operation at light loads
improves converter efficiency and prolongs battery life. The
HYS mode of operation can be inhibited independently for
each channel if a variable frequency operation is not
desired.
Even though the soft-start pin voltage continues to rise after
reaching 1.5V, this voltage does not affect the output
voltage. During the soft-start, the converter always operates
in continuous conduction mode independent of the load level
or VOUT pin connection.
The soft-start time (the time from the moment when EN
becomes high to the moment when PGOOD is reported) is
determined by Equation 1:
The ISL6227 has a special means to rearrange its internal
architecture into a complete DDR solution. When the DDR
pin is set high, the second channel can provide the capability
to track the output voltage of the first channel. The buffered
reference voltage required by DDR memory chips is also
provided.
1.5V × Csoft
----------------------------------
=
(EQ. 1)
t
SOFT
4.5μA
The time it takes the output voltage to come into regulation
can be obtained from Equation 2:
Initialization
t
= 0.6 × t
(EQ. 2)
RISE
SOFT
The ISL6227 initializes if at least one of the enable pins is
set high. The Power-On Reset (POR) function continually
monitors the bias supply voltage on the VCC pin, and
initiates soft-start operation when EN1 or EN2 is high after
the input supply voltage exceeds 4.45V. Should this voltage
drop lower than 4.14V, the POR disables the chip.
During soft-start stage before the PGOOD pin is ready, the
undervoltage protection is prohibited. The overvoltage and
overcurrent protection functions are enabled.
If the output capacitor has residue voltage before startup,
both lower and upper MOSFETs are in off-state until the
soft-start capacitor charges equal the VSEN pin voltage.
This will ensure the output voltage starts from its existing
voltage level.
Soft-Start
When soft-start is initiated, the voltage on the SOFT pin of
the enabled channel starts to ramp up gradually with the
internal 4.5µA current charging the soft-start capacitor. The
output voltage follows the soft-start voltage with the
converter operating at 300kHz PWM switching frequency.
FN9094.7
May 4, 2009
14
ISL6227
The two channels can be programmed to operate in different
Output Voltage Program
modes depending on the VOUTx connection and the load
current. Once both channels operate in the PWM mode,
however, they will be synchronized to the 300kHz switching
clock. The 180° phase shift reduces the noise couplings
between the two channels and reduces the input current ripple.
The output voltage of either channel is set by a resistive divider
from the output to ground. The center point of the divider is
connected to the VSEN pin as shown in Figure 34. The
output voltage value is determined by Equation 3:
0.9V • (R1 + R2)
---------------------------------------------
V
=
(EQ. 3)
O
The critical discontinuous conduction current value for the
PWM to HYS mode switch-over can be calculated by
Equation 4:
R2
where 0.9V is the value of the internal reference. The VSEN
pin voltage is also used by the controller for the power good
function and to detect undervoltage and overvoltage
conditions.
(V – V ) • V
O
IN
O
(EQ. 4)
----------------------------------------------------
=
I
HYS
2 • F
• L • V
O IN
SW
The HYS mode to PWM switch-over current I
HYS1
determined by the activation time of the HYS mode
is
V
IN
Q1
controller. It is affected by the ESR, the inductor value, the
input and output voltage.
UGATE
ISEN
R
CS
L1
V
O
The HYS mode control can improve converter efficiency with
reduced switching frequency. The efficiency is further
improved by the diode emulation scheme in discontinuous
conduction mode. The diode emulation scheme does not
allow the inductor sink current from the output capacitor,
thereby reducing the circulating energy. It is achieved by
sensing the free-wheeling current going through the
synchronous MOSFET through Phase node voltage polarity
change after the upper MOSFET is turned off. Before the
current reverses direction, the lower MOSFET gate pulses
are terminated.
C
C1
Z
Q2
R1
LGATE
VOUT
VSEN
OCSET
ISL6227
R2
R
OC
FIGURE 34. OUTPUT VOLTAGE PROGRAM
The PWM-HYS and HYS-PWM switch-over is provided
automatically by the mode control circuit, which constantly
monitors the inductor current through phase voltage polarity,
and alters the way the gate driver pulse signal is generated.
Operation Mode Control
VOUTx pin programs the two channels of ISL6227 in two
different operational modes:
Mode Transition
For a buck regulator, if the load current is higher than critical
1. If VOUTx is connected to ground, the channel will be put
into a fixed switching frequency of 300kHz CCM, also
known as forced PWM mode regardless of load
conditions.
value I
, the voltage drop on the synchronous MOSFET
HYS1
in the free-wheeling period is always negative, and vice
versa. The mode control circuit monitors the phase node
voltage in the off-period. The polarity of this voltage is used
as the criteria for whether the load current is greater than the
critical value, and thus determines whether the converter will
operate in PWM or HYS mode.
2. If the VOUTx is connected to the output voltage, the
channel will operate in either fixed 300kHz PWM mode or
HYS mode, depending on the load conditions. It operates
in the PWM mode when the load current exceeds the
critical discontinuous conduction value, otherwise it will
operate in a HYS mode, as shown in the following table.
To prevent chatter between operating modes, the circuit
looks for eight sequentially matching polarity signals before it
decides to perform a mode change. The algorithm is true for
both CCM-HYS and HYS-CCM transitions.
INDUCTOR
CURRENT
OPERATION
MODE
VOUT PIN
In the HYS mode, the PWM comparator and the error
amplifier, that provided control in the CCM mode, are put in a
clamped stage and the hysteretic comparator is activated. A
change is also made to the gate logic. The synchronous
MOSFET is controlled in diode emulation fashion, hence the
current in the synchronous MOSFET will be kept in one
direction only. Figures 35 and 36 illustrate the mode change
by counting eight switching cycles.
GND
Any value
Forced PWM
HYS
Connects to output voltage
Connects to output voltage
≤ I
HYS
>I
PWM
HYS1
FN9094.7
May 4, 2009
15
ISL6227
and the input voltage through the VIN pin are used to
VOUT
IIND
determine the error amplifier output voltage and the duty
cycle. The error amplifier stays in an armed state while
waiting for the transition to occur. The transition decision
point is aligned with the PWM clock. When the need for
transition is detected, there is a 500ns delay between the
first/last pulse of the PWM controller from the last/first pulse
of the hysteretic mode controller.
t
t
PHASE
COMP
t
t
1
2
3
4 5
6 7 8
Current Sensing
The current on the lower MOSFET is sensed by measuring
its voltage drop within its on-time. In order to activate the
current sampling circuitry, two conditions need to be met.
(1) the Lgate is high and (2) the phase pin sees a negative
voltage for regular buck operation, which means the current
is freewheeling through lower MOSFET. For the second
channel of the DDR application, the phase pin voltage needs
to be higher than 0.1V to activate the current sensing circuit
for bidirectional current sensing. The current sampling
finishes at about 400ns after the lower MOSFET has turned
on. This current information is held for current mode control
and overcurrent protection. The current sensing pin can
source up to 260µA. The current sense resistor and OCSET
resistor can be adjusted simultaneously for the same
overcurrent protection level, however, the current sensing
gain will be changed only according to the current sense
resistor value, which will affect the current feedback loop
gain. The middle point of the Isen current can be at 75µA,
but it can be tuned up and down to fit application needs.
MODE
PWM
HYSTERETIC
OF
OPERATION
FIGURE 35. CCM—HYSTERETIC TRANSITION
VOUT
IIND
t
t
1
2
3
4 5
6
7
8
PHASE
COMP
t
t
HYSTERETIC
MODE
OF
OPERATION
PWM
If another channel is switching at the moment the current
sample is finishing, it could cause current sensing error and
phase voltage jitter. In the design stage, the duty cycles and
synchronization have to be analyzed for all the input voltage
and load conditions to reduce the chance of current sensing
error. The relationship between the sampled current and
MOSFET current is given by Equation 5:
FIGURE 36. HYSTERETIC—CCM TRANSITION
If load current slowly increases or decreases, mode
transition will occur naturally, as described in Figures 35 and
36; however, if there is an instantaneous load current
increase resulting in a large output voltage drop before the
hysteretic mode controller responds, a comparator with
threshold of 20mV below the reference voltage will be
tripped, and the chip will jump into the forced PWM mode
immediately. The PWM controller will process the load
transient smoothly.
I
(R
+ 140) = r
I
DS(ON) D
(EQ. 5)
SEN CS
Which means the current sensing pin will source current to
make the voltage drop on the MOSFET equal to the voltage
generated on the sensing resistor, plus the internal resistor,
along the ISEN pin current flowing path.
Once the PWM controller is engaged, eight consecutive
switching cycles of negative inductor current are required to
transition back to the hysteretic mode. In this way, chattering
between the two modes is prevented. Current sinking during
the 8 PWM switching cycle dumps energy to input,
smoothing output voltage load step-down.
Feedback Loop Compensation
Both channel PWM controllers have internally compensated
error amplifiers. To make internal compensation possible
several design measures were taken.
• The ramp signal applied to the PWM comparator has been
made proportional to the input voltage by the VIN pin. This
keeps the product of the modulator gain and the input
voltage constant even when the input voltage varies.
As a side effect to this design, the comparator may be
triggered consistently if the ESR of the capacitor is so big
that the output ripple voltage exceeds the 20mV window,
resulting in a pure PWM pulse.
• The load current proportional signal is derived from the
voltage drop across the lower MOSFET during the PWM
off time interval, and is subtracted from the error amplifier
The PWM error amplifier is put in clamped voltage during the
hysteretic mode. The output voltage through the VOUT pin
FN9094.7
May 4, 2009
16
ISL6227
output signal before the PWM comparator input. This
effectively creates an internal current control loop.
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
The resistor connected to the ISEN pin sets the gain in the
current sensing. The following expression estimates the
required value of the current sense resistor, depending on
the maximum continuous load current, and the value of the
VRAMP
AMPLITUDE
VIN PIN CONNECTION
Ch1
Input Voltage
Input voltage >4.2V
Input voltage <4.2V
Vin/8
1.25V
MOSFETs r
current.
, assuming the ISEN pin sources 75µA
DS(ON)
GND
1.25V
I
• r
Ch2
Input voltage >4.2V
GND
0.625V
1.25V
MAX
DS(ON)
------------------------------------------
(EQ. 6)
R
=
– 140Ω
CS
75μA
Because the current sensing circuit is a sample-and-hold
type, the information obtained at the last moment of the
sampling is used. This current sensing circuit samples the
inductor current very close to its peak value. The current
The small signal transfer function from the error amplifier
output voltage V to the output voltage V can be written in
Equation 8:
c
o
feedback essentially injects a resistor R in series with the
i
s
Wz
⎛
⎝
⎞
--------
+ 1
original LC filter as shown in Figure 37, where the
sample-and-hold effect of the current loop has been ignored.
Vc and Vo are small signal components extracted from its
DC operation points.
R
⎠
o
(EQ. 8)
--------------------------------------- ---------------------------------------------------------
G(s) = G
m
R + DCR + R
s
s
i
o ⎛
⎞ ⎛
⎞
------------
------------
+ 1
+ 1
⎝
⎠ ⎝
⎠
Wp1
Wp2
The DC gain is derived by shorting the inductor and opening
the capacitor. There is one zero and two poles in this transfer
function. The zero is related to ESR and the output
capacitor.
Ri
Lo
DCR
+
Co
ESR
+
Gm*Vc
Ro
Vo
-
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output
capacitor can be regarded as a short circuit. By
-
FIGURE 37. THE EQUIVALENT CIRCUIT OF THE POWER
STAGE WITH CURRENT LOOP INCLUDED
approximation, the poles and zero are inversely proportional
to the time constants, associated with inductor and capacitor,
by Equations 9, 10 and 11:
The value of the injected resistor can be estimated by
Equation 7:
V
r
DS(ON)
1
IN
(EQ. 7)
-----------------------
Wz =
--------------------------------------------
R =
• 4.4kΩ
(EQ. 9)
i
ESR*C
V
R
+ 140
o
ramp CS
1
R is in kΩ, and r and R are in Ω . V divided by V
DS CS IN ramp
is defined as Gm, which is a constant 8dB or 18dB for both
,
------------------------------------------------------------------------------
i
Wp1 =
(EQ.10)
(EQ.11)
||
(ESR + (R + DCR) R )*C
i
o
o
channels in dual switcher applications, when V is above
IN
3V. Refer to Table 1 for the ramp amplitude in different V
IN
||
R + DCR + ESR
----------------------------------------------------------
R
o
i
pin connections. The feed-forward effect of the V is
Wp2 =
IN
L
o
reflected in Gm. V is defined as the error amplifier output
C
voltage.
Since the current loop separates the LC resonant poles into
two distant poles, and ESR zero tends to cancel the high
frequency pole, the second order system behaves like a first
order system. This control method simplifies the design of
the internal compensator and makes it possible to
accommodate many applications having a wide range of
parameters.
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VRAMP
AMPLITUDE
VIN PIN CONNECTIONS
Ch1 and Ch2 Input Voltage Input voltage >4.2V
Input voltage <4.2V
VIN/8
The schematics for the internal compensator is shown in
Figure 38.
1.25V
GND
1.25V
FN9094.7
May 4, 2009
17
ISL6227
resistor R , output LC filter, and voltage feedback network,
the system loop gain can be accurately analyzed and
CS
1.25pF
500k
modified by the system designers based on the application
requirements.
1M 15pF
TO PWM
COMPARATOR
300k
60
50
VSEN
-
+
Vc
0.9V
4.4k
40
30
LC FILTER
ISEN
20
COMPENSATOR
10
VO/VC
0
FIGURE 38. THE INTERNAL COMPENSATOR
-10
-20
-30
-40
-50
-60
LOOP GAIN
Its transfer function can be written as Equation 12:
5
s
2πf
s
2πf
⎛
⎝
⎞ ⎛
⎠ ⎝
⎞
+ 1
--------------
--------------
1.857 • 10
+ 1
⎠
z1
z2
--------------------------------------------------------------------------------------------
Gcomp(s) =
(EQ.12)
s
⎛
⎞
---------------
s
+ 1
⎝
⎠
2πf
3
4
5
6
p1
100
1•10
1•10
FREQUENCY (Hz)
1•10
1•10
where:
FIGURE 39. THE BODE PLOT OF THE LC FILTER,
COMPENSATOR, CONTROL TO OUTPUT
f
= 6.98kHz, f = 380kHz, and f = 137kHz
z2 p1
z1
VOLTAGE TRANSFER FUNCTION, AND SYSTEM
LOOP GAIN
Outside the ISL6227 chip, a capacitor C can be placed in
z
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 34. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as Equation 13:
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing necessary amplification,
level shift, and shoot-through protection. It bears some
functions that help to optimize the IC performance over a
wide range of the operational conditions. As MOSFET
switching time can vary dramatically from type to type, and
with the input voltage, the gate control logic provides
adaptive dead time by monitoring real gate waveforms of
both the upper and the lower MOSFETs.
R
sR C + 1
1 z
2
-----------------------------------------------------------------
Gfd(s) =
(EQ.13)
||
+ R s(R R )C + 1
R
1
2
1
2
z
The ratio of R and R is determined by the output voltage
1
2
set point; therefore, the position of the pole and zero
frequency in the above equation may not be far apart;
however, they can improve the loop gain and phase margin
with the proper design.
Dual-Step Conversion
The C can bring the high frequency transient output voltage
z
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of C .
z
The ISL6227 dual channel controller can be used either in
power systems with a single-stage power conversion, when
the battery power is converted into the desired output
voltage in one step, or in the systems where some
intermediate voltages are initially established. The choice of
the approach may be dictated by the overall system design
criteria, or the approach may be a matter of voltages
available to the system designer, as in the case of PCI card
applications.
From the analysis above, the system loop gain can be
written as Equation 14:
(EQ.14)
Gloop(s) = G(s) • Gcomp(s) • Gfd(s)
Figure 39 shows the composition of the system loop gain. As
shown in the graph, the power stage becomes a well
damped second order system as compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
over frequency at about 30kHz. With a given set of
When the output voltage is regulated from low voltage such
as 5V, the feed-forward ramp may become too shallow,
creating the possibility of duty-factor jitter; this is particularly
relevant in a noisy environment. Noise susceptibility, when
operating from low level regulated power sources, can be
improved by connecting the VIN pin to ground, by which the
feed-forward ramp generator will be internally reconnected
from the VIN pin to the VCC pin, and the ramp slew rate will
be doubled.
parameters, including the MOSFET r
, current sense
DS(ON)
FN9094.7
May 4, 2009
18
ISL6227
first eight clock cycles, normal operation is restored and the
Voltage Monitor and Protections
overcurrent circuit resets itself at the end of sixteenth clock
cycles; see Figure 40.
The converter output is monitored and protected against
extreme overload, short circuit, overvoltage, and
undervoltage conditions. A sustained overload on the output
sets the PGOOD low and latches off the offending channel of
the chip. The controller operation can be restored by cycling
the VCC voltage or toggling both enable (EN) pins to low to
clear the latch.
PGOOD
1
8 CLK
IL
SHUTDOWN
2
VOUT
Power Good
In the soft-start process, the PGOOD is established after the
soft pin voltage is at 1.5V. In normal operation, the PGOOD
window is 100mV below the 0.9V and 135mV higher than
0.9V. The VSEN pin has to stay within this window for
PGOOD to be high. Since the VSEN pin is used for both
feedback and monitoring purposes, the output voltage
deviation can be coupled directly to the VSEN pin by the
capacitor in parallel with the voltage divider as shown in
Figure 4. In order to prevent false PGOOD drop, capacitors
need to parallel at the output to confine the voltage deviation
with severe load step transient. The PGOOD comparator
has a built-in 3µs filter. PGOOD is an open drain output.
3
μ
M 10.0 s
Ch1 5.0V
Ch3 1.0A
Ch2 100mV
Ω
FIGURE 40. OVERCURRENT PROTECTION
Due to the nature of the used current sensing technique,
and to accommodate a wide range of the r
variation,
DS(ON)
the value of the overcurrent threshold should set at about
180% of the nominal load value. If more accurate current
protection is desired, a current sense resistor placed in
series with the lower MOSFET source may be used. The
inductor current going through the lower MOSFET is sensed
and held at 400ns after the upper MOSFET is turned off;
therefore, the sensed current is very close to its peak value.
The inductor peak current can be written as Equation 16:
Overcurrent Protection
In dual switcher application, both PWM controllers use the
lower MOSFETs on-resistance r
to monitor the
DS(ON),
current for protection against shorted outputs. The sensed
current from the ISEN pin is compared with a current set by
a resistor connected from the OCSET pin to ground:
(V – V ) • V
o
IN
o
(EQ.16)
-------------------------------------------
+ I
load
I
=
peak
2L • F
• V
IN
o
SW
10.3V
--------------------------------------------------------
R
=
As seen from Equation 16, the inductor peak current
changes with the input voltage and the inductor value once
an output voltage is selected.
(EQ.15)
SET
I
• r
OC
DS(ON)
--------------------------------------
+ 8μA
R
+ 140Ω
CS
where, I
is a desired overcurrent protection threshold and
OC
After overcurrent protection is activated, there are two ways
to bring the offending channel back: (1) Both EN1 and EN2
have to be held low to clear the latch, (2) To recycle the VCC
of the chip, the POR will clear the latch.
R
is the value of the current sense resistor connected to
CS
the ISEN pin. The 8µA is the offset current added on top of
the sensed current from the ISEN pin for internal circuit
biasing.
Undervoltage Protection
If the lower MOSFET current exceeds the overcurrent
threshold, a pulse skipping circuit is activated. The upper
MOSFET will not be turned on and the lower MOSFET
keeps conducting as long as the sampled current is higher
than the threshold value, limiting the current supplied by the
DC voltage source. The current in the lower MOSFET will be
sampled at the internal 300kHz oscillator frequency and
monitored. When the sampled current is lower than the OC
threshold value, the following UGATE pulse will be released
and it allows turning on the upper MOSFET based on the
voltage regulation loop. This kind of operation remains for
eight clock cycles after the overcurrent comparator was
tripped for the first time. If after the first eight clock cycles the
sampled current exceeds the overcurrent threshold again,
within a time interval of another eight clock cycles, the
overcurrent protection latches and disables the offending
channel. If the overcurrent condition goes away during the
In the process of operation, if a short circuit occurs, the output
voltage will drop quickly. Before the overcurrent protection
circuit responds, the output voltage will fall out of the required
regulation range. The chip comes with undervoltage protection.
If a load step is strong enough to pull the output voltage lower
than the undervoltage threshold, the offending channel latches
off immediately. The undervoltage threshold is 75% of the
nominal output voltage. Toggling both pins to low, or recycling
VCC, will clear the latch and bring the chip back to operation.
Overvoltage Protection
Should the output voltage increase over 115% of the normal
value due to the upper MOSFET failure, or for other reasons,
the overvoltage protection comparator will force the
synchronous rectifier gate driver high. This action actively
pulls down the output voltage and eventually attempts to
blow the battery fuse. As soon as the output voltage is within
FN9094.7
May 4, 2009
19
ISL6227
regulation, the OVP comparator is disengaged. The
MOSFET driver will restore its normal operation. When the
OVP occurs, the PGOOD will drop to low as well.
For the VTT channel where output is derived from the VDDQ
output, some control and protective functions have been
significantly simplified. For example, the overcurrent, and
overvoltage, and undervoltage protections for the second
channel controller are disabled when the DDR pin is set
high. The hysteretic mode of operation is also disabled on
the VTT channel to allow sinking capability to be
independent from the load level. As the VTT channel tracks
the VDDQ/2 voltage, the soft-start function is not required,
and the SOFT2 pin may be left open, in the event both
channels are enabled simultaneously. However, if the VTT
channel is enabled later than the VDDQ, the SOFT2 pin
must have a capacitor in place to ensure soft-start. In case of
overcurrent or undervoltage caused by short circuit on VTT,
the fault current will propagate to the first channel and shut
down the converter.
This OVP scheme provides a ‘soft’ crowbar function, which
helps clamp the voltage overshoot, and does not invert the
output voltage when otherwise activated with a continuously
high output from lower MOSFET driver - a common problem
for OVP schemes with a latch.
DDR Application
High throughput Double Data Rate (DDR) memory ICs are
replacing traditional memory ICs in the latest generation of
Notebook PCs and in other computing devices. A novel
feature associated with this type of memory are the
referencing and data bus termination techniques. These
techniques employ a reference voltage, VREF, that tracks
the center point of VDDQ and VSS voltages, and an
additional VTT power source where all terminating resistors
are connected. Despite the additional power source, the
overall memory power consumption is reduced compared to
traditional termination.
The VREF voltage will be present even if the VTT is
disabled.
Channel Synchronization in DDR Applications
The presence of two PWM controllers on the same die
requires channel synchronization, to reduce inter-channel
interference that may cause the duty factor jitter and
increased output ripple.
The added power source has a cluster of requirements that
should be observed and considered. Due to the reduced
differential thresholds of DDR memory, the termination
power supply voltage, VTT, closely tracks VDDQ/2 voltage.
The PWM controller is at greatest noise susceptibility when
an error signal on the input of the PWM comparator
approaches the decision making point. False triggering may
occur, causing jitter and affecting the output regulation.
Another very important feature of the termination power
supply is the capability to operate at equal efficiency in
sourcing and sinking modes. The VTT supply regulates the
output voltage with the same degree of precision when
current is flowing from the supply to the load, and when the
current is diverted back from the load into the power supply.
A common approach used to synchronize dual channel
converters is out-of-phase operation. Out-of-phase
operation reduces input current ripple and provides a
minimum interference for channels that control different
voltage levels.
The ISL6227 dual channel PWM controller possesses
several important enhancements that allow re-configuration
for DDR memory applications, and provides all three
voltages required in a DDR memory compliant computer.
When the DDR pin is connected to GND for dual switcher
applications, the channels operate 180° out-of-phase. When
used in a DDR application with cascaded converters (VTT
generated from VDDQ), several methods of synchronization
are implemented in the ISL6227. In the DDR mode, when
the DDR pin is connected to VCC, the channels operate
either with 0° phase shift, when the VIN pin is connected to
the GND, or with 90° phase shift if the VIN pin is connected
to a voltage higher than 4.2V.
To reconfigure the ISL6227 for a complete DDR solution, the
DDR pin should be set high permanently to the VCC rail.
This activates some functions inside the chip that are
specific to DDR memory power needs.
In the DDR application presented in Figure 32, the first
controller regulates the VDDQ rail to 2.5V. The output
voltage is set by external dividers Rfb1 and Rfb12. The
second controller regulates the VTT rail to VDDQ/2. The
OCSET2 pin function is now different, and serves as an
input that brings VDDQ/2 voltage, created by the Rd1 and
Rd2 divider, inside the chip, effectively providing a tracking
function for the VTT voltage.
The following table lists the different synchronization
schemes and their usage:
DDR PIN
VIN PIN
VIN pin >4.2V
SYNCHRONIZATION
180° out of phase
0° phase
0
1
1
VIN pin voltage <4.2V
VIN pin voltage >4.2V
The PG2 pin function is also different in DDR mode. This pin
becomes the output of the buffer, whose input is connected
to the center point of the R/R divider from the VDDQ output
by the OCSET2 pin. The buffer output voltage serves as a
1.25V reference for the DDR memory chips. Current
capability of this pin is 10mA (12mA max).
90° phase shift
FN9094.7
May 4, 2009
20
ISL6227
current of the ISEN pin to meet the overcurrent protection
Application Information
Design Procedures
GENERAL
and the change the current loop gain. The lower the current
sensing resistor, the higher gain of the current loop, which
can damp the output LC filter more.
A ceramic decoupling capacitor should be used between the
VCC and GND pin of the chip. There are three major
currents drawn from the decoupling capacitor:
A higher value current-sensing resistor will decrease the
current sense gain. If the phase node of the converter is very
noisy due to poor layout, the sensed current will be
contaminated, resulting in duty cycle jittering by the current
loop. In such a case, a bigger current sense resistor can be
used to reduce both real and noise current levels. This can
help damp the phase node wave form jittering.
1. the quiescent current, supporting the internal logic and
normal operation of the IC
2. the gate driver current for the lower MOSFETs
3. and the current going through the external diodes to the
bootstrap capacitor for upper MOSFET.
Sometimes, if the phase node is very noisy, a resistor can be
put on the ISEN pin to ground. This resistor together with the
In order to reduce the noisy effect of the bootstrap capacitor
current to the IC, a small resistor, such as 10Ω, can be used
with the decoupling capacitor to construct a low pass filter for
the IC, as shown in Figure 41. The soft-start capacitor and
the resistor divider setting the output voltage is easy to
select as discussed in the “Block Diagram” on page 13.
R
can divide the phase node voltage down, seen by the
CS
internal current sense amplifier, and reduce noise coupling.
Sizing the Overcurrent Setpoint Resistor
The internal 0.9V reference is buffered to the OCSET pin
with a voltage follower (refer to the equivalent circuit in
Figure 42). The current going through the external
TO BOOT
overcurrent set resistor is sensed from the OCSET pin. This
current, divided by 2.9, sets up the overcurrent threshold and
compares with the scaled ISEN pin current going through
VCC
5V
10Ω
R
with an 8µA offset. Once the sensed current is higher
CS
than the threshold value, an OC signal is generated. The first
OC signal starts a counter and activates a pulse skipping
function. The inductor current will be continuously monitored
through the phase node voltage after the first OC trip. As
long as the sensed current exceeds the OC threshold value,
the following PWM pulse will be skipped. This operation will
be the same for 8 switching cycles. Another OC occurring
between 8 to 16 switching cycles would result in a latch off
with both upper and lower drives low. If there is no OC within
8 to 16 switching cycles, normal operation resumes.
FIGURE 41. INPUT FILTERING FOR THE CHIP
Selection of the Current Sense Resistor
The value of the current sense resistor determines the gain
of the current sensing circuit. It affects the current loop gain
and the overcurrent protection setpoint. The voltage drop on
the lower MOSFET is sensed within 400ns after the upper
MOSFET is turned off. The current sense pin has a 140Ω
resistor in series with the external current sensing resistor.
The current sense pin can source up to a 260µA current
while sensing current on the lower MOSFET, in such a way
that the voltage drop on the current sensing path would be
equal to the voltage on the MOSFET.
ISEN
PHASE
140Ω
-
+
R
_
+
8uµA
CS
+
+
Σ
r
DS(ON)
I
(R
+ 140Ω) = I r
(EQ.17)
SOURCING CS D DS(ON)
+33.1
I
SENSE
OC
SET
-
+
I
can be assumed to be the inductor peak current. In a
+
-
OC
D
0.9V
worst case scenario, the high temperature r
increase to 150% of the room temperature level. During
could
DS(ON)
R
AMPLIFIER REFERENCE
SET
COMPARATOR
+2.9
overload condition, the MOSFET drain current I could be
D
130% higher than the normal inductor peak. If the inductor
has 30% peak-to-peak ripple, I would equal to 115% of the
D
load current. The design should consider the above factors
FIGURE 42. EQUIVALENT CIRCUIT FOR OC SIGNAL
GENERATOR
so that the maximum I
will not saturate to 260µA
under worst case conditions. To be safe, I should
SOURCING
SOURCING
be less than 100µA in normal operation at room
temperature. The formula in the earlier discussion assumes
a 75µA sourcing current. Users can tune the sourcing
FN9094.7
May 4, 2009
21
ISL6227
Based on the above description and functional block
diagram, the OC set resistor can be calculated as
Equation 18:
The inductor copper loss can be significant in the total
system power loss. Attention has to be given to the DCR
selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated
temperature. Saturated inductors could result in nuisance
OC, or OV trip.
10.3V
---------------------------------------------------
=
R
set
I
r
OC DS(ON)
(EQ.18)
--------------------------------
+ 8μA
R
+ 140
CS
Output voltage ripple and the transient voltage deviation are
factors that have to be taken into consideration when
selecting an output capacitor. In addition to high frequency
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by Equations 22
and 23:
I
is the inductor peak current and not the load current.
OC
Since inductor peak current changes with input voltage, it is
better to use an oscilloscope when testing the overcurrent
setting point to monitor the inductor current, and to
determine when the OC occurs. To get consistent test results
on different boards, it is best to keep the MOSFET at a fixed
temperature.
I
The MOSFET will not heat-up when applying a very low
frequency and short load pulses with an electronic load to
the output.
pp
---------------------
ΔV
=
(EQ.22)
(EQ.23)
c
8C F
o
sw
ΔV
= I
ESR
As an example, assume the following:
esr
p – p
• The maximum normal operation load current is 1
These two components constitute a large portion of the total
output voltage ripple. Several capacitors have to be
paralleled in order to reduce the ESR and the voltage ripple.
If the output of the converter has to support another load
with high pulsating current, more capacitors are needed in
order to reduce the equivalent ESR and suppress the
voltage ripple to a tolerable level.
• The inductor peak current is 1.15x to 1.3x higher than the
load current, depending on the inductor value and the
input voltage
• The r
has a 45% increase at higher temperature
should set at least 1.8 to 2 times higher than the
DS(ON)
I
OC
maximum load current to avoid nuisance overcurrent trip.
To support a load transient that is faster than the switching
frequency, more capacitors have to be used to reduce the
voltage excursion during load step change. Another aspect
of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS
current specified on the capacitors, to prevent the capacitor
from over-heating.
Selection of the LC Filter
The duty cycle of a buck converter is a function of the input
voltage and output voltage. Once an output voltage is fixed,
it can be written as Equation 19:
V
o
---------
D(V ) =
(EQ.19)
IN
V
IN
Selection of the Input Capacitor
When the upper MOSFET is on, the current in the output
inductor will be seen by the input capacitor. Even though this
current has a triangular shape top, its RMS value can be
fairly approximated by Equation 24:
The switching frequency, F , of ISL6227 is 300kHz. The
sw
peak-to-peak ripple current going through the inductor can
be written as Equation 20:
V (1 – D(V ))
o
IN
(EQ.20)
----------------------------------------
=
I
pp
(EQ.24)
F
L
o
sw
lin
(V ) = D(V )*I
IN load
rms IN
As higher ripple current will result in higher switching loss
and higher output voltage ripple, the peak-to-peak current of
the inductor is generally designed with a 20% to 40%
peak-to-peak ripple of the nominal operation current. Based
on this assumption, the inductor value can be selected with
Equation 20. In addition to the mechanical dimension, a
shielded ferrite core inductor with a very low DC resistance,
DCR, is preferred for less core loss and copper loss. The DC
copper loss of the inductor can be estimated by Equation 21:
This RMS current includes both DC and AC components.
Since the DC component is the product of duty cycle and
load current, the AC component can be approximated by
Equation 25:
2
(EQ.25)
li
(V ) = (D(V ) – D(V ) )I
nac IN
IN
IN
load
AC components will be provided from the input capacitor.
The input capacitor has to be able to handle this ripple
current without overheating and with tolerable voltage ripple.
In addition to the capacitance, a ceramic capacitor is
generally used between the drain terminal of the upper
2
(EQ.21)
P
= I
DCR
copper
load
FN9094.7
May 4, 2009
22
ISL6227
MOSFET and the source terminal of the lower MOSFET, in
order to clamp the parasitic voltage ringing at the phase
node in switching.
Q
is used because when the MOSFET drain-to-source
gd
voltage has fallen to zero, it gets charged. Similarly, the turn-off
time can be estimated based on the gate charge and the gate
drivers sinking current capability.
Choosing MOSFETs
The total power loss of the upper MOSFET is the sum of the
switching loss and the conduction loss. The temperature rise on
the MOSFET can be calculated based on the thermal
impedance given on the datasheet of the MOSFET. If the
temperature rise is too much, a different MOSFET package
size, layout copper size, and other options have to be
considered to keep the MOSFET cool. The temperature rise
can be calculated by Equation 30:
For a notebook battery with a maximum voltage of 28V, at
least a minimum 30V MOSFETs should be used. The design
has to trade off the gate charge with the r
MOSFET:
of the
DS(ON)
• For the lower MOSFET, before it is turned on, the body
diode has been conducting. The lower MOSFET driver will
not charge the miller capacitor of this MOSFET.
• In the turning off process of the lower MOSFET, the load
current will shift to the body diode first. The high dv/dt of
the phase node voltage will charge the miller capacitor
through the lower MOSFET driver sinking current path.
(EQ.30)
T
= θ P
ja totalpower loss
rise
The MOSFET gate driver loss can be calculated with the
total gate charge and the driver voltage V . The lower
CC
MOSFET only charges the miller capacitor at turn-off.
This results in much less switching loss of the lower
MOSFETs.
(EQ.31)
P
= V
Q F
cc gs sw
driver
The duty cycle is often very small in high battery voltage
applications, and the lower MOSFET will conduct most of
Based on Equation 31, the system efficiency can be
estimated by the designer.
the switching cycle; therefore, the lower the r
lower MOSFET, the less the power loss. The gate charge for
this MOSFET is usually of secondary consideration.
of the
DS(ON)
Confining the Negative Phase Node Voltage Swing
with Schottky Diode
At each switching cycle, the body diode of the lower MOSFET
will conduct before the MOSFET is turned on, as the inductor
current is flowing to the output capacitor. This will result in a
negative voltage on the phase node. The higher the load
current, the lower this negative voltage. This voltage will ring
back less negative when the lower MOSFET is turned on.
The upper MOSFET does not have this zero voltage
switching condition, and because it conducts for less time
compared to the lower MOSFET, the switching loss tends to
be dominant. Priority should be given to the MOSFETs with
less gate charge, so that both the gate driver loss, and
switching loss, will be minimized.
A total 400ns period is given to the current sample-and-hold
circuit on the ISEN pin to sense the current going through the
lower MOSFET after the upper MOSFET turns off. An
excessive negative voltage on the lower MOSFET will be
treated as overcurrent. In order to confine this voltage, a
schottky diode can be used in parallel with the lower MOSFET
for high load current applications. PCB layout parasitics should
be minimized in order to reduce the negative ringing of phase
voltage.
For the lower MOSFET, its power loss can be assumed to be
the conduction loss only.
2
P
(V ) ≈ (1 – D(V ))I
r
(EQ.26)
lower IN
IN load DS(ON)Lower
For the upper MOSFET, its conduction loss can be written as
Equation 27:
2
P
(V ) = D(V )I
r
(EQ.27)
uppercond IN
IN load DS(ON)upper
and its switching loss can be written as Equation 28:
The second concern for the phase node voltage going into
negative is that the boot strap capacitor between the BOOT
and PHASE pin could get be charged higher than VCC voltage,
exceeding the 6.5V absolute maximum voltage between BOOT
and PHASE when the phase node voltage became negative. A
resistor can be placed between the cathode of the boot strap
diode and BOOT pin to increase the charging time constant of
the boot cap. This resistor will not affect the turn-on and off of
the upper MOSFET.
V
I
T
f
V
I T f
IN peak off sw
(EQ.28)
IN vally on sw
------------------------------------------- --------------------------------------------
P
(V ) =
+
uppersw IN
2
2
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with the
given gate driver parameters in the “Electrical Specifications”
Table on page 3. For example, if the gate driver turn-on path of
MOSFET has a typical on-resistance of 4W, its maximum
turn-on current is 1.2A with 5V VCC. This current would decay
as the gate voltage increased. With the assumption of linear
current decay, the turn-on time of the MOSFETs can be written
with Equation 29:
Schottky diode can reduce the reverse recovery of the lower
MOSFET when transition from freewheeling to blocking,
therefore, it is generally good practice to have a Schottky
diode closely parallel with the lower MOSFET. B340LA, from
Diodes, Inc.®, can be used as the external Schottky diode.
2Q
gd
(EQ.29)
----------------
t
=
on
I
driver
FN9094.7
May 4, 2009
23
ISL6227
the opposite side of the board. For example, prospective
Tuning the Turn-on of Upper MOSFET
layer arrangement on a 4 layer board is shown below:
The turn-on speed of the upper MOSFET can be adjusted by
the resistor connecting the boot cap to the BOOT pin of the
chip. This resistor can confine the voltage ringing on the boot
capacitor from coupling to the boot pin. This resistor slows
down only the turn-on of the upper MOSFET.
1. Top Layer: ISL6227 signal lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
If the upper MOSFET is turned on very fast, it could result in
a very high dv/dt on the phase node, which could couple into
the lower MOSFET gate through the miller capacitor,
causing momentous shoot-through. This phenomenon,
together with the reverse recovery of the body diode of the
lower MOSFET, can over-shoot the phase node voltage to
beyond the voltage rating of the MOSFET. However, a bigger
resistor will slow the turn-on of the MOSFET too much and
lower the efficiency. Trade-offs need to be made in choosing
a suitable resistor value.
It is a good engineering practice to separate the power
voltage and current flowing path from the control and logic
level signal path. The controller IC will stay on the signal
layer, which is isolated by the signal ground to the power
signal traces.
Component Placement
The control pins of the two-channel ISL6227 are located
symmetrically on two sides of the IC; it is desirable to
arrange the two channels symmetrically around the IC.
System Loop Gain and Stability
The system loop gain is a product of three transfer functions:
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATEx, UGATEx, PHASEx, BOOTx,
and ISENx traces can be short.
1. the transfer function from the output voltage to the
feedback point,
2. the transfer function of the internal compensation circuit
from the feedback point to the error amplifier output voltage,
Place the components in such a way that the area under the
ISL6227 has fewer noise traces with high dv/dt and di/dt,
such as gate signals and phase node signals.
3. and the transfer function from the error amplifier output to
the converter output voltage.
Signal Ground and Power Ground Connection
These transfer functions are written in a closed form in the
“Theory of Operation” on page 14. The external capacitor, in
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, could be used
as signal ground beneath the ISL6227. The best tie-point
between the signal ground and the power ground is at the
negative side of the output capacitor on each channel, where
there is less noise. Noisy traces beneath the ISL6227 are
not recommended.
parallel with the upper resistor of the resistor divider, C , can
z
be used to tune the loop gain and phase margin. Other
component parameters, such as the inductor value, can be
changed for a wider cross-over frequency of the system loop
gain. A body plot of the loop gain transfer function with a 45°
phase margin (a 60° phase margin is better) is desirable to
cover component parameter variations.
GND and VCC
At least one high quality ceramic decoupling cap should be
used across these two pins. A via can tie Pin 1 to signal
ground. Since Pin 1 and Pin 28 are close together, the
decoupling cap can be put close to the IC.
Testing the Overvoltage on Buck Converters
For synchronous buck converters, if an active source is used
to raise the output voltage for the overvoltage protection test,
the buck converter will behave like a boost converter and
dump energy from the external source to the input. The
overvoltage test can be done on ISL6227 by connecting the
VSEN pin to an external voltage source or signal generator
through a diode. When the external voltage, or signal
generator voltage, is tuned to a higher level than the
overvoltage threshold (the lower MOSFET will be on), it
indicates the overvoltage protection works. This kind of
overvoltage protection does not require an external schottky
in parallel with the output capacitor.
LGATE1 and LGATE2
These are the gate drive signals for the bottom MOSFETs of
the buck converter. The signal going through these traces
have both high dv/dt and high di/dt, with high peak charging
and discharging current. These two traces should be short,
wide, and away from other traces. There should be no other
weak signal traces in parallel with these traces on any layer.
PGND1 and PGND2
Each pin should be laid out to the negative side of the
relevant output capacitor with separate traces.The negative
side of the output capacitor must be close to the source node
of the bottom MOSFET. These traces are the return path of
LGATE1 and LGATE2.
Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
FN9094.7
May 4, 2009
24
ISL6227
PHASE1 and PHASE2
PG1 and PG2/REF
For dual switcher operations, these two lines are less noise
sensitive. For DDR applications, a capacitor should be
placed to the PG2/REF pin.
These traces should be short, and positioned away from other
weak signal traces. The phase node has a very high dv/dt with
a voltage swing from the input voltage to ground. No trace
should be in parallel with these traces. These traces are also
the return path for UGATE1 and UGATE2. Connect these pins
to the respective converter’s upper MOSFET source.
DDR
This pin should connect to VCC in DDR applications, and to
signal ground in dual switcher applications.
Pin 5 and Pin 24, the UGATE1 and UGATE2
VIN
These pins have a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should wide, short,
and away from other traces similar to the LGATEx.
This pin connects to battery voltage, and is less noise sensitive.
Copper Size for the Phase Node
Big coppers on both sides of the Phase node introduce
parasitic capacitance. The capacitance of PHASE should be
kept very low to minimize ringing. If ringing is excessive, it
could easily affect current sample information. It would be
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application.
BOOT1 and BOOT2
These pins di/dt are as high as that of the UGATEx;
therefore, the traces should be as short as possible.
ISEN1 and ISEN2
The ISEN trace should be a separate trace, and
Identify the Power and Signal Ground
independently go to the drain terminal of the lower MOSFET.
The current sense resistor should be close to ISEN pin.
The input and output capacitors of the converters, the source
terminals of the bottom switching MOSFET PGND1, and
PGND2, should be closely connected to the power ground.
The other components should connect to signal ground.
Signal and power ground are tied together at the negative
terminal of the output capacitors.
The loop formed by the bottom MOSFET, output inductor,
and output capacitor, should be very small. The source of
the bottom MOSFET should tie to the negative side of the
output capacitor in order for the current sense pin to get the
voltage drop on the r
.
DS(ON)
Decoupling Capacitor for Switching MOSFET
EN1 and EN2
It is recommended that ceramic caps be used closely
connected to the drain side of the upper MOSFET, and the
source of the lower MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET. Refer to Figure 43
These pins stay high in enable mode and low in idle mode
and are relatively robust. Enable signals should refer to the
signal ground.
VOUT1 and VOUT2
for the power component placement.
.
-
+
+
-
VIN
These pins connect either to the output voltage or to the
signal ground. They are signal lines and should be kept
away from noisy lines.
VSEN1 and VSEN2
8
7
1
There is usually a resistor divider connecting the output
voltage to this pin. The input impedance of these two pins is
high because they are the input to the amplifiers. The correct
layout should bring the output voltage from the regulation
point to the SEN pin with kelvin traces. Build the resistor
divider close to the pin so that the high impedance trace is
shorter.
2
-
-
SI4816DY
6
5
3
4
V
OUTPUT
CAP
O
+
INDUCTOR
OCSET1 and OCSET2
L
O
In dual switcher mode operation, the overcurrent set resistor
should be put close to this pin. In DDR mode operation, the
voltage divider, which divides the VDQQ voltage in half,
should be put very close to this pin. The other side of the OC
set resistor should connect to signal ground.
FIGURE 43. A GOOD EXAMPLE POWER COMPONENT
REPLACEMENT. IT SHOWS THE NEGATIVE OF INPUT
AND OUTPUT CAPACITOR AND SOURCE OF THE
MOSFET ARE TIED AT ONE POINT.
SOFT1 and SOFT2
The soft-start capacitors should be laid out close to this pin.
The other side of the soft-start cap should tie to signal ground.
FN9094.7
May 4, 2009
25
ISL6227
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X
3.0
5.00
0.50
24X
A
6
B
PIN #1 INDEX AREA
28
22
6
PIN 1
INDEX AREA
1
21
3 .10 ± 0 . 15
15
7
(4X)
0.15
8
14
0.10 M C A B
- 0.07
TOP VIEW
28X 0.55 ± 0.10
BOTTOM VIEW
4
28X 0.25
+ 0.05
SEE DETAIL "X"
C
0.10
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08
C
( 4. 65 TYP )
(
( 24X 0 . 50)
SIDE VIEW
3. 10)
(28X 0 . 25 )
( 28X 0 . 75)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9094.7
May 4, 2009
26
ISL6227
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
AREA
0.25(0.010)
M
B M
H
E
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
-B-
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.394
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
10.00
3.98
NOTES
A
A1
A2
B
0.053
0.004
-
-
1
2
3
-
L
0.25
0.010
SEATING PLANE
A
-
-A-
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
D
h x 45°
C
D
E
-
-C-
3
α
4
A2
e
A1
C
e
0.025 BSC
0.635 BSC
-
B
0.10(0.004)
H
h
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
0.17(0.007) M
C
A M B S
5
L
6
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
N
α
28
28
7
0°
8°
0°
8°
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 1 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9094.7
May 4, 2009
27
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